JPS5931799B2 - semiconductor memory cell - Google Patents
semiconductor memory cellInfo
- Publication number
- JPS5931799B2 JPS5931799B2 JP51150944A JP15094476A JPS5931799B2 JP S5931799 B2 JPS5931799 B2 JP S5931799B2 JP 51150944 A JP51150944 A JP 51150944A JP 15094476 A JP15094476 A JP 15094476A JP S5931799 B2 JPS5931799 B2 JP S5931799B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- semiconductor memory
- cell
- information
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
Description
【発明の詳細な説明】
（１）発明の利用分野
本発明は、半導体記憶セルに関するものであり、更に詳
わしく言えば、情報保持時と選択時（読出しまたは書込
み時）とでコレクタ負荷を切換える型の半導体記憶セル
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a semiconductor memory cell, and more specifically, the present invention relates to a semiconductor memory cell. The present invention relates to a switching type semiconductor memory cell.
（２）従来技術
従来から、高速用のバイポーラメモリ集積回路用のメモ
リセルとして、情報保持時と選択時とでセルのコレクタ
負荷抵抗を大きく切換え（選択時に低くする）ると同時
に大きな読出し電流を流す型のものが知られている。(2) Prior art Conventionally, as a memory cell for a high-speed bipolar memory integrated circuit, the collector load resistance of the cell is largely switched between when retaining information and when selecting (lowering when selecting), and at the same time a large read current is generated. A flushable type is known.
その例を第１図ａ−ｆに示す。、これらのセルで使用さ
れているダイオードは、通常のＰＮ接合ダイオードであ
つてもよいしショットキーダイオードであつてもよい。
これらのセルのうち第１図ａ−ｄに示すものについては
、たとえば特公昭４６−１３７８１号に詳細に述べられ
ている。これらのセルは、情報保持時には負荷抵抗が大
きいため保持電流Ｉｓｔが少なくてよく、低消費電力の
メモリを構成できる。Examples are shown in FIGS. 1a-f. , the diodes used in these cells may be normal PN junction diodes or Schottky diodes.
Of these cells, those shown in FIGS. 1a-d are described in detail in, for example, Japanese Patent Publication No. 13781/1983. Since these cells have a large load resistance when holding information, the holding current Ist may be small, and a memory with low power consumption can be constructed.
一方、選択時には負荷抵抗が小さくなり大きな読出し電
流工Ｒが流せるので、動作速度は速い。以上の特徴を充
分に生かすには、メモリ容量が大きくなればなる程、情
報保持時の負荷抵抗Ｒｓをと動作時の負荷抵抗ＲＲとの
比を大きくする必要がある。しかし、第１図に示したよ
うな従来型のメモリセルでは、ＲｓをとＲＲとの比をあ
まり大きくすると、電流がＩｓｔからＩＲへと切換わる
途中で、セルの情報保持ができなくなる。On the other hand, when selected, the load resistance is small and a large read current R can be applied, so the operating speed is fast. In order to make full use of the above characteristics, the larger the memory capacity becomes, the larger the ratio between the load resistance Rs during information retention and the load resistance RR during operation must be increased. However, in the conventional memory cell shown in FIG. 1, if the ratio between Rs and RR is too large, the cell will no longer be able to retain information while the current is switched from Ist to IR.
たとえば、第１図ｅの型のセルについてＩＲの値を横軸
にセルの信号振幅（セルの２つのトランジスタのベース
電圧の差）を縦軸にとつて示すと、第２図のようにノ
なる。このように、Ｒｓを、！Ｉ、ＲＲの比が大きい時
（第２図の場合は約５００）には、Ｒｓｔで電位が決ま
つている状態からＲＲで電位が決まる状態へと転移する
途中で非常に電位差が小さい状態を必ず経ることになる
。このことは、電圧降下、セフ ル信号振幅、飽和等の
点で、Ｒｓｔに大きなＩＲを流すことは不可能なため、
ＩＲがまだ完全に増加しないうちにセルの負荷をＲＲと
するようなメ、７−モリセル構成をとる必要性より生じ
ている。For example, for a cell of type e in Figure 1, if the IR value is plotted on the horizontal axis and the cell's signal amplitude (difference between the base voltages of the two transistors in the cell) is plotted on the vertical axis, then the node shown in Figure 2 is plotted.
Become. In this way, Rs. When the ratio of I and RR is large (approximately 500 in the case of Figure 2), a state where the potential difference is very small is created during the transition from a state where the potential is determined by Rst to a state where the potential is determined by RR. It will definitely pass. This means that it is impossible to flow a large IR through Rst due to voltage drop, safe signal amplitude, saturation, etc.
This arises from the need to adopt a 7-Moly cell configuration in order to increase the cell load to RR before IR has completely increased.
このような事情は、第１図の他のセルにも全て同様であ
る。したがつて、従来型のセルでは、ＲｓｔとＲＲの比
、つまりＩＲとＩ８ｔの比には限度があつた。（３）発
明の目的
本発明の目的は、小さなＩ８ｔから大きなＩＲへとセル
電流が増加する途中の過渡的な状態でも、セル電位差が
あまり減少しないメモリセルを提供することである。This situation is the same for all the other cells in FIG. Therefore, in conventional cells, there is a limit to the ratio between Rst and RR, that is, the ratio between IR and I8t. (3) Aim of the Invention An object of the invention is to provide a memory cell in which the cell potential difference does not decrease much even in a transient state where the cell current increases from a small I8t to a large IR.
したがつて、本発明に従がえば、低消費電力で高速のメ
モリセルを得ることができる。（４）実施例
以下、本発明を実施例を参照して詳細に説明する。Therefore, according to the present invention, a high-speed memory cell with low power consumption can be obtained. (4) Examples Hereinafter, the present invention will be explained in detail with reference to examples.
第３図のａ−ｄは、第１図のＡ，ｄ，ｅ，ｆのそれぞれ
に本発明の概念を適用した例である。3A to 3D are examples in which the concept of the present invention is applied to A, d, e, and f of FIG. 1, respectively.
第１図のｂおよびｃは、ダイオードに直列抵抗がなく、
そのため大電流のＩＲに対してセル電位差が零に近づき
本質的にＩＲ／Ｉ８ｔ比を比常に大きく（たとえば１０
００以上）にとることは不可能なので、第３図からは除
いている。この実施例に示すように、本発明の第３図の
実施例ａ−ｄではＲ８ｔと並列にコンデンサＣｓが挿入
されている。b and c in Figure 1 have no series resistance in the diode;
Therefore, for large current IR, the cell potential difference approaches zero, essentially increasing the IR/I8t ratio (for example, 10
00 or higher), it is excluded from Figure 3. As shown in this embodiment, in embodiments ad of FIG. 3 of the present invention, a capacitor Cs is inserted in parallel with R8t.
情報保持時には、このコンデン ！サにほぼ８ｔｘＲＳ
ｔの電圧が蓄えられている。この電圧は、８ｔからＩＲ
へと電流が切換わる問、コンデンサに蓄えられるため、
過渡的なセル電位の減少を防ぎ得る。また、第３図ｅは
、第１図のｅに本発明の概念を適用したもう１つの実施
５例であり、Ｃｓはダイオードと並列に入つている。
この場合、Ｒｓｔ》ＩＲであるので、Ｉ８ｔからＸＲへ
と切換わる過渡状態では、コンデンサＣ８はＲｓｔと並
列に人つた場合と同様な働きをして、過渡時の情報破壊
を防止する。第４図は、本発明の効果を示す図である。When retaining information, this condensation! Almost 8txRS
A voltage of t is stored. This voltage is from 8t to IR
When the current switches to , it is stored in the capacitor, so
This can prevent a transient decrease in cell potential. FIG. 3e shows another fifth embodiment in which the concept of the present invention is applied to e in FIG. 1, and Cs is connected in parallel with the diode.
In this case, since Rst>IR, in the transient state when switching from I8t to XR, the capacitor C8 functions in the same way as when it is connected in parallel with Rst, thereby preventing information destruction during the transient. FIG. 4 is a diagram showing the effects of the present invention.
Ｃ８が零の時（勿論浮遊容量分は含んでいる）では、過
渡時でのセル電位差の長小値（０１−ＶＯＯ）Ｍｍは、
情報保持時のセル電位差（Ｃ１−００）Ｓｔａｎｄｂｙ
の１４％まで減少し、確実にセルの情報は破壊される。
Ｃｓを増加して行くと、第４図に示すように、（ＶＯｌ
−ＶｃＯ）Ｍｍは（Ｖｃｌ−ＶＯＯ） Ｓｔａｎｄｂｙ
に近づき、過渡状態でもセル電位差の減少が少なく、情
報破壊を避けることができる。When C8 is zero (of course, stray capacitance is included), the length (01-VOO) Mm of the cell potential difference during transient is:
Cell potential difference during information retention (C1-00) Standby
The cell information is definitely destroyed.
As Cs increases, (VOl
-VcO) Mm is (Vcl-VOO) Standby
, the cell potential difference decreases little even in a transient state, and information destruction can be avoided.
なお、この結果は、第３図のｃおよびｅに対して得られ
た結果を示したものであるが、ａおよびｄに対しても同
様な結果が得られている。以上、本発明を交さ接続型の
特定のメモリセルを実施例として述べてきたが、本発明
の概念は、情報保持時と選択時とで負荷インピーダンス
を切換えるあらゆるメモリセルに適用できることは、言
うまでもなかろう。Note that this result shows the results obtained for c and e in FIG. 3, but similar results were also obtained for a and d. Although the present invention has been described above using a specific cross-connected memory cell as an embodiment, it goes without saying that the concept of the present invention can be applied to any memory cell whose load impedance is switched between when storing information and when selecting information. I wonder.
また、コンデンサＣ８の実現方法も種々考え得るが、ど
のような方法で構成してもよい。Further, various methods of realizing the capacitor C8 can be considered, and any method may be used to construct the capacitor C8.
好ましい方法の一例は、たとえば特開昭５１１３０８５
８号に述べられている。An example of a preferred method is, for example, Japanese Patent Application Laid-Open No. 5113085.
It is stated in No. 8.
このようなコンデンサの構成方法は、本発明にはどのよ
うなものを使用してもよいので、これ以上の説明はしな
い。Any method of constructing such a capacitor may be used in the present invention and will not be further described.
第１図は、情報保持時と選択時とでコレクタ負荷を切換
える型の従来型のメモリセルの回路図、第２図は、従来
型のセルの負荷抵抗切換えの比を制限する特性を説明す
る図、第３図は本発明の実施例のメモリセルの回路図、
第４図は本発明の効効果を示す実験結果。Figure 1 is a circuit diagram of a conventional memory cell that switches the collector load between information retention and selection, and Figure 2 explains the characteristics that limit the load resistance switching ratio of the conventional cell. 3 is a circuit diagram of a memory cell according to an embodiment of the present invention,
FIG. 4 shows experimental results showing the effectiveness of the present invention.
Claims (1)
第２のトランジスタを有し、該第１、第２のトランジス
タのコレクタには、負荷インピーダンスが情報保持時に
は大、選択時には小となるような負荷回路がそれぞれ接
続された半導体記憶セルにおいて、前記負荷回路と実質
的に並列にコンデンサが接続されることを特徴とする半
導体記憶セル。 ２ 前記負荷回路は、負荷インピーダンス切替用のダイ
オード抵抗との直列回路を含むことを特徴とする特許請
求の範囲第１項記載の半導体記憶セル。 ３ 前記コンデンサは、前記ダイオードに並列に接続さ
れたことを特徴とする特許請求の範囲第２項記載の半導
体記憶セル。[Scope of Claims] 1. A first collector, the collector and the base being interconnected and connected to each other;
In a semiconductor memory cell having a second transistor, a load circuit is connected to the collectors of the first and second transistors so that the load impedance is large when information is retained and small when information is selected. A semiconductor memory cell characterized in that a capacitor is connected substantially in parallel with a circuit. 2. The semiconductor memory cell according to claim 1, wherein the load circuit includes a series circuit with a diode resistor for switching load impedance. 3. The semiconductor memory cell according to claim 2, wherein the capacitor is connected in parallel to the diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51150944A JPS5931799B2 (en) | 1976-12-17 | 1976-12-17 | semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51150944A JPS5931799B2 (en) | 1976-12-17 | 1976-12-17 | semiconductor memory cell |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58236193A Division JPS59151390A (en) | 1983-12-16 | 1983-12-16 | Semiconductor storage cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5375829A JPS5375829A (en) | 1978-07-05 |
| JPS5931799B2 true JPS5931799B2 (en) | 1984-08-04 |
Family
ID=15507819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51150944A Expired JPS5931799B2 (en) | 1976-12-17 | 1976-12-17 | semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931799B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60168221U (en) * | 1984-04-18 | 1985-11-08 | パイオニア株式会社 | keyboard switch unit |
-
1976
- 1976-12-17 JP JP51150944A patent/JPS5931799B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60168221U (en) * | 1984-04-18 | 1985-11-08 | パイオニア株式会社 | keyboard switch unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5375829A (en) | 1978-07-05 |
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