JPS5931753B2 - coin sorting device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a device for sorting coins by measuring characteristics such as material, thickness, diameter, etc. of coins using an electrical method, and accurately determines the authenticity of coins by incorporating an error range. It brings about change.

One embodiment will be described in detail below with reference to the drawings.

Inspection of the characteristics of coins using electrical methods generally involves the frequency of the excitation coil, which is caused by eddy current loss within the coin, which is caused by placing the coin in an alternating magnetic field induced by the excitation coil.
This is done by inspecting changes in inductance or the like, or by adding a detection coil and measuring the phase difference between the excitation coil and the detection coil based on the eddy current loss.

The measurement results obtained by such an electrical method are expressed in analog quantities, and by first converting the analog quantities into digital quantities, the operation for determining the coin's authenticity and denomination is started. FIG. 1 shows a detector 1 that inspects the characteristics of a coin by measuring a phase difference, and an inspection circuit 2 that outputs information necessary for a coin determination operation in digital quantities based on the inspection results.

The configuration of the detector 1 is such that an excitation coil IA and a detection coil IB are arranged with a coin passage 5 in between, and voltage or current changes in the excitation coil IA and detection coil IB based on the passage of a coin 6 are output to the inspection circuit λ. It is. The test circuit 2 inputs AC signals indicating voltage or current output from the excitation coil IA and the detection coil IB into waveform shaping circuits T and 8, converts them into rectangular waves, and outputs the rising outputs of both from a set of flip-flop circuits 9 and 8. The phase difference is detected by using it as a reset input. Therefore, the Q of the flip-flop circuit 9
The output is generated during a period corresponding to the phase difference width, but this phase difference is measured by counting clock pulses during the period when the flip-flop circuit 9 generates the Q output. There is. For example, if the inspection circuit 2 is configured so that the gate 10 is opened by the Q output of the flip-flop circuit 9 and the clock pulses output from the clock pulse generator 11 are counted by the counter 12, the measured phase difference is immediately necessary for the coin judgment operation. This information is generated in the test circuit 2 in digital quantities. While the coin 6 rolls through the coin path 5 and is inspected by the detector 1, this phase difference is not always constant, and its value becomes maximum when the detector 1 and the coin 6 overlap. Therefore, while the coin 6 is being inspected by the detector unit, the flip-flop circuit 9 detects a number of phase differences, and captures the largest of these detected phase differences and uses it as the measurement result. It is used for authenticity and denomination determination information. FIG. 2 shows the configuration of a maximum value detection circuit l for extracting the maximum phase difference from the inspection circuit 2.

The comparison circuit 14 compares the count content C of the counter 12 included in the test circuit 2 with the content R of the register 15, and outputs a signal if C>R, and a signal b if R>C. . In the initial state, the content C of the register 15 is "O", so when a certain value indicating the phase difference is counted by the counter 12, a signal is generated since C>R, and the AND
Input to gates Al, A2, A3, A4, and A5. Since one of these AND gates Al, A2, A3, A4, and A5 is connected to each bit of the counter 12, the count content C of the counter 12 is changed to the register 15 when the a signal arrives.
will be transferred to. Eventually, the counter 12 counts a value indicating the next phase difference, and the comparator 14 compares this value with the value transferred to the register 15 earlier. At this time as well, C>R, the a signal is generated, and the count contents of the counter 12 are transferred to the register 15 again. Thus counter 1
2, each time the flip-flop circuit 9 outputs an output indicating a phase difference, the counted contents are sequentially compared with the previous counted contents in the comparator 14. Eventually, as mentioned above, when the coin 6 reaches the position where it overlaps the detector ↑, the phase difference will show the maximum value, but at this stage it cannot be confirmed that it is the maximum, and this value is also transferred to the register 15. . When the coins 6 move slightly away from the overlapping position, the phase difference becomes smaller, and the comparator 1 shows that the value counted by the counter 12 is smaller than the maximum value stored in the register 15.
4, and an R>C(7)b signal is generated. Therefore, when the b signal is generated, it is confirmed that the value currently stored in the register 15 is the maximum value, and the value of the register 15 is applied to the AND gates All, Al2, Al3, Al4, A.
It can be shown as the maximum value via l5.
In this way, the authenticity and coin type of the coin 6 are determined based on the phase difference maximum value information outputted from the maximum value detection circuit u, but the maximum value detection circuit V3 in particular is not essential to the present invention. This may be omitted if this determination is made using the total phase difference information outputted from the inspection circuit 2 as a measurement result.

FIG. 3 shows a coin determination circuit based on phase difference maximum value information outputted from the maximum value detection circuit. The readout memory 3 is composed of, for example, a diode matrix,
Input lines are provided corresponding to the number of bits indicating maximum phase difference value information, and output lines are connected to exclusive OR circuits 16, 17, 18, and 19, respectively, arranged according to the four types of coins. . The readout memory 3 can then indicate when the phase difference is measured by the detector 1, the test circuit 2 and the maximum value detection circuit I for each coin type along the address represented by the 5-bit input line. The upper and lower limits of the range are stored respectively. When the readout memory 3 is presented with these stored addresses through the input line, it outputs a signal indicating the upper limit value or the lower limit value through one of the output lines. The exclusive OR circuits 16, 17, 18, and 19 each have two output lines for signals indicating the upper and lower limit values of the corresponding coin type, and these output lines are connected to the exclusive OR circuit via a latch circuit 20. It is connected to circuits 16, 17, 18, and 19. Third
The circles in the figure indicate the state in which the output line and the input line are short-circuited by forward connection of the diode 21 as shown in Fig. 4.
Memory is performed by a combination of these. Third
In the figure, when the maximum value detection circuit 13 outputs the maximum phase difference value information which is the measurement result of the coin 6, it is possible to determine which coin type the maximum phase difference falls within the upper and lower limit value range. can be determined.

At this time, for address designation of the read memory 3, a signal having the same quality as the output of the maximum value detection circuit 2 is outputted from the arithmetic circuit 22. First, the arithmetic circuit 22 uses the phase difference maximum value information outputted from the maximum value detection circuit 1 as is for addressing. When this phase difference maximum value information is within the upper and lower limit value range of any coin type, nothing can be read at this address, and next, from the phase difference maximum value information, "1
” is subtracted and presented as the address. In this way, the values obtained by subtracting 1 one by one are read out as addresses and presented to the readout memory 3, and when the address storing the lower limit value is presented as a result of the subtraction, the readout memory 3 receives a signal indicating the lower limit value. occurs on the output line, and the corresponding latch circuit 20 enters the set state. In addition, in the initial state, which latch circuit 2
Assume that the state is set to 0. Therefore, when a certain latch circuit 20 is set to the set state by such a search, an output is generated from the corresponding exclusive OR circuit (hereinafter referred to as EOR), and the coin 6 is determined to be the coin type set in this EOR. It turns out that In this way, if the phase difference maximum value information falls within the upper limit value/lower limit value range of any coin type, any EOR l6, l7, l8 and l9 produce outputs, but the following problem may also occur here. In other words, if the coin 6 is a counterfeit coin and does not fall within the upper and lower limit ranges of any coin type, according to the above-mentioned detection operation, the arithmetic circuit 2
As a result of the subtraction of 2, a signal indicating the upper limit value is first read out and an output is generated from the EOR in order to set the latch circuit 20. In order to prevent this, in this embodiment, the arithmetic circuit 22 subtracts "1" from the maximum phase difference value information regardless of the presence or absence of the output of any of the EORs 16, 17, 18, and 19, and the result is 0. The operation of presenting the address as an address continues until . In this case, even if a certain EOR generates an output with a signal indicating the upper limit value, when the next signal indicating the lower limit value arrives, both EORs reach the [H] level and the output is stopped. However, when the phase difference maximum value information is within a certain EOR upper limit value/lower limit value range, only the signal indicating the lower limit value is input, so this EOR that once produced an output will not stop outputting due to the subtraction operation. . Further, even if the subtraction progresses further and other EORs produce an output at a signal indicating the upper limit value, the output is stopped when a signal indicating the lower limit value arrives, as described above. Also, the EO whose upper and lower limits are values larger than the maximum phase difference information
Since the latch circuits 20 each maintain their set states, naturally no output is generated from this EOR. Therefore, when the arithmetic circuit 22 indicates [0], EORl6,l
Only one of 7, l8, and l9 is producing an output, or none of them is producing an output. Therefore, if an output is generated, the coin 6 is determined to be the coin type corresponding to the EOR, and if no output is generated, the coin 6 is determined to be a counterfeit coin. Further, EOR can be set by detecting "O" at the end of subtraction up to "O". By such scan operation, a set of latch circuits 20 and EOR
Coin determination device 4A arranged for each coin type according to the configuration of
, 4B, 4C, and 4D, the circuit can be simplified because the setting of the allowable error range for determining the coin 6 as a genuine coin requires only two people to send signals indicating the upper and lower limits.

Further, in the embodiment, the scan operation is continued until the arithmetic circuit 22 outputs "0", but this is for the purpose of distinguishing EOR, which temporarily produces an output during the scan, as described above. Therefore, which EOR l6, l7, l8, l9 was read out first after scanning?
If the circuit configuration is such that it is possible to distinguish between the upper limit value and the lower limit value, the scan operation up to "O" is not necessary. In other words, if it is the upper limit, coin 6 is counterfeit.
If it is the lower limit value, it is determined that the signal corresponds to the coin type corresponding to the input EOR. The present invention, which has been described in detail above, relates to a coin sorting device that determines coins by inspecting their characteristics based on electrical methods, and extracts information to be determined from the inspection results by a detector and converts this information into digital data. The present invention proposes that an inspection circuit is provided to output a measurement result in terms of quantity, and the coin is judged by digital processing at a later stage.

Therefore, the measurement results for genuine coins, which serve as reference values, are first read out and stored in memory, but by taking the error range into account, setting the upper and lower limits and performing a scan operation, the coins can be measured. Since the addressing signal which ensures the reliable selection and commands the readout of the memory in the readout memory is the same as the signal output from the test circuit, the circuit can be easily constructed.

[Brief explanation of the drawing]

FIG. 1 shows a detector and a test circuit, FIG. 2 shows the configuration of a maximum value detection circuit, FIG. 3 shows a readout memory and a coin determining device, and FIG. 4 shows details of FIG. 3. Explanation of main drawing numbers, 1...Detector, 2...
・Test circuit, 3...Readout memo I8 4A, 4
B, 4C, 4D... Coin determination device.

Claims (1)

[Claims] 1. A detector that electrically tests the characteristics of a coin, a test circuit that outputs a measurement result to be judged based on the test result of the characteristics as a digital amount of a predetermined number of bits, and a A readout memory that stores upper and lower limit values of measurement results based on the characteristics of the coin along the addresses indicated by the number of bits, and a signal indicating the upper and lower limit values read from the memory are two inputs. It consists of a coin judgment device arranged for each coin type, and it sequentially subtracts the value obtained by the inspection circuit in the direction of "0" and reads the subtraction result sequentially indicated by the number of bits from the memory. A coin sorting device that outputs an address designation signal, and if there is a coin determining device to which only a signal indicating the lower limit value is input, the coin is determined to be a coin compatible with the coin determining device.