JPS5930330A - Digital frequency display system - Google Patents

Digital frequency display system

Info

Publication number
JPS5930330A
JPS5930330A JP14016582A JP14016582A JPS5930330A JP S5930330 A JPS5930330 A JP S5930330A JP 14016582 A JP14016582 A JP 14016582A JP 14016582 A JP14016582 A JP 14016582A JP S5930330 A JPS5930330 A JP S5930330A
Authority
JP
Japan
Prior art keywords
frequency
display
transmission
cpu
frequency display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14016582A
Other languages
Japanese (ja)
Other versions
JPH0322109B2 (en
Inventor
Koji Akiyama
秋山 好司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP14016582A priority Critical patent/JPS5930330A/en
Publication of JPS5930330A publication Critical patent/JPS5930330A/en
Publication of JPH0322109B2 publication Critical patent/JPH0322109B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
    • H03J1/0016Indicating arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transceivers (AREA)

Abstract

PURPOSE:To attain a convenient frequency display system, by constituting the system so that a frequency display device holds the transmssion frequency display when a full brake-in operation is selected at the switching of transmission/reception. CONSTITUTION:A VCO constitutes a PLL control oscillating circuit together with a reference oscillator, a programmable frequency divider and a phase comparator. A CPU stores a receiving frequency and supplies it to a display device, and when the CPU selects the full brake-in mode, the CPU stores and displays the transmission frequency at the 1st transmission. The CPU is provided with a timer having a prescribed time from the fall of a mark signal and when the next mark signal is inputted within the time, the transmission frequency of the display is held at if no input is given within the prescribed time, the display is restored to the receiving frequency.

Description

【発明の詳細な説明】 この発明はCW送受信機のフルブレークイン動作時にお
けるデジタル周波数表示方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital frequency display method during full break-in operation of a CW transceiver.

ここでCW送受信機と称するのは、実際にはCW専用機
はほとんど存在しないで、SSBやAMとCWの兼用モ
ードが大部分であるので、以下に挙げる回路構成例にお
いても、複モード機のCW動作関係部のみを抜き出して
、CW動作のみを説明することになる。
The reason why we call it a CW transmitter/receiver here is because there are almost no CW-only machines in reality, and most of them are in SSB or AM/CW mode. Only the CW operation-related parts will be extracted and only the CW operation will be explained.

第1図はCW送受信機の回路構成と周波数構成(1) の代表例である。受信時はアンテナ1よシ送受切換リレ
ー2を通った1 000 kHzの信号波は、受信ミク
サ3で局部発振周波数]、 4.55 kHzと混合し
て、455kH2の中間周波となり、検波器5でBFO
6の456 kHzとの差出力である1、 kHzのト
ーン信号を作る。
Figure 1 shows a typical example of the circuit configuration and frequency configuration (1) of a CW transceiver. During reception, the 1 000 kHz signal wave that has passed through the antenna 1 and the transmission/reception switching relay 2 is mixed with the local oscillation frequency of 4.55 kHz by the reception mixer 3 to become an intermediate frequency of 455 kHz, which is output by the detector 5. BFO
A tone signal of 1. kHz, which is the difference output from 456 kHz of 6.

送信時はキャリア発振器7の455 kHzを送信ミク
サ8で局部発振器4の周波数と混合して送信周波数とす
る。送信周波数が受信周波数と同一の場合は問題ないか
ら説明は省略する。送信周波数を101.0 kHzと
するためには送信時の局部発振周波数は1465 kH
zとしなければならない。これは現在普通に使用されて
いるPLL発振回路では送信時の周波数と受信時の周波
数をそれぞれ別個に設定することは容易にできるので問
題はない。
At the time of transmission, the 455 kHz of the carrier oscillator 7 is mixed with the frequency of the local oscillator 4 by the transmission mixer 8 to obtain a transmission frequency. If the transmission frequency is the same as the reception frequency, there is no problem, so the explanation will be omitted. In order to set the transmission frequency to 101.0 kHz, the local oscillation frequency during transmission must be 1465 kHz.
Must be z. This is not a problem in the currently commonly used PLL oscillation circuits because it is easy to set the transmitting frequency and the receiving frequency separately.

周波数表示は局部周波数を補正器9で補正(この場合は
−455)し、表示器10でデジタル表示するので、受
信時は受信周波数、送信時は送信周波数を表示する。と
ころで、CW時の自動送受信切換方法にはセミブレーク
イン方式とフルプレーt 9 ) フィン方式とがある。セミブレークインは一部キーを押
して電波が発射されると、キーを上げて電波を止めても
、保持時間の間は回路は送信状態のままになっているか
ら、連続送信中は周波数表示は送信周波数となっている
。これに対し、フルブレークインはキーを押している間
は送信状態で電波が発射されるが、キーを上げたスペー
ス時には受信状態であるのが特長であるから、送信時に
はマークで送信周波数、スペースで受信周波数と、交互
に急速に変化し、これに従って周波数表示も変化するが
、実際問題として1つの表示器で2つの周波数を表示す
ることは出来ないし、周波数カウンタ計測ではダート時
間の関係で正しい計測も不可能であるから、送信中は周
波数表示器は無意味な表示をすることになる。
For frequency display, the local frequency is corrected by the corrector 9 (-455 in this case) and digitally displayed on the display 10, so that the receiving frequency is displayed when receiving, and the transmitting frequency is displayed when transmitting. By the way, automatic transmission/reception switching methods during CW include a semi-break-in method and a full-plate t9) fin method. With semi-break-in, when a radio wave is emitted by pressing a certain key, even if you raise the key to stop the radio wave, the circuit remains in the transmitting state during the hold time, so the frequency display will not display during continuous transmission. This is the transmission frequency. On the other hand, with full break-in, radio waves are emitted in the transmitting state while the key is held down, but when the key is raised to the space, the radio waves are in the receiving state. The received frequency alternates rapidly, and the frequency display also changes accordingly, but as a practical matter, it is not possible to display two frequencies on one display, and frequency counter measurements cannot be performed correctly due to dart time. Since this is also impossible, the frequency display will display meaningless information during transmission.

この発明は[7−″ジタル周波数表示を有するCW送受
信機において、送信と受信の転換にフルブレークイン動
作を選択した状態では、キーイング中は周波数表示器が
送信周波数表示を保持するように構成したことを特徴と
するデジタル周波数表示方式」であって、CW送受信機
において、受信時には周波数表示器は受信周波数を表示
し、フルブレークイン送信時には、信号のスペース時に
は受信状態であっても表示周波数はマーク時と同じ送信
周波数を保持することにょシ、あたかもセミブレークイ
ンと同様の(ただしスペース時に受信できるフルブレー
クインの特長は失わ々い)、受信時は受信周波数を表示
し、送信時は送信周波数を表示する、実際上で便宜の大
きい周波数表示方式%式% 次に本発明を実施する上での具体的手段について述べる
が、前記のような周波数表示上の問題を生ずるのは主と
して送受信機の局部発振周波数が送信周波数と受信周波
数を決定し、また同時に周波数表示器を制御する形式の
機器で、最近多く実用されているCPU (Centr
al Processor Unit)制御の局部発振
回路はこれに属するから、実施例としてもCPU制御の
局部発振回路について説明することにする。
This invention provides a CW transmitter/receiver having a 7-" digital frequency display, in which the frequency display maintains the transmit frequency display during keying when full break-in operation is selected for switching between transmit and receive. In a CW transmitter/receiver, the frequency display displays the received frequency during reception, and during full break-in transmission, the displayed frequency does not change even in the reception state when the signal is spaced. By maintaining the same transmit frequency as when marking, it is similar to semi-break-in (however, the feature of full break-in that can be received during space is lost), the receive frequency is displayed when receiving, and the transmit frequency is displayed when transmitting. A practical and convenient frequency display method % type % Next, we will discuss specific means for implementing the present invention, but it is mainly the transmitter/receiver that causes the above-mentioned frequency display problem. The local oscillation frequency of the CPU determines the transmitting frequency and the receiving frequency, and at the same time controls the frequency display.
Since the local oscillation circuit controlled by the CPU (Processor Unit) belongs to this category, the local oscillation circuit controlled by the CPU will be explained as an example.

第2図はCPU制御の送受信機回路の構成の概要示すブ
ロック図である。図中の受信部と送信部は第1図と同様
であるから細部は省略しである。第1図の局部発振器3
は第2図のVCO(電圧制御発振器)に相当し、このV
COは少々くも基準発振器・プログラマブル分周器・位
相比較器と共にPLL制御発振回路を構成している。V
COの周波数はプログラマブル分周器に外部よシ与える
デジタルデータで決まシ、初期にはアップダウン・カウ
ンタを使用したが、現在ではCPU機能の一部として実
行でき、周波数表示器に対する表示値のプリセット補正
や一時記憶もマイクロプログラミングによシ行なってい
るので、本発明の要求する動作条件を容易に満足するこ
とができる。
FIG. 2 is a block diagram schematically showing the configuration of a CPU-controlled transmitter/receiver circuit. The receiving section and transmitting section in the figure are the same as those in FIG. 1, so details are omitted. Local oscillator 3 in Figure 1
corresponds to the VCO (voltage controlled oscillator) in Figure 2, and this V
The CO constitutes a PLL controlled oscillation circuit together with a spider reference oscillator, a programmable frequency divider, and a phase comparator. V
The frequency of the CO is determined by digital data supplied externally to a programmable frequency divider. Initially, an up/down counter was used, but now it can be implemented as part of the CPU function and can be used to preset the displayed value on the frequency display. Since correction and temporary storage are also performed by microprogramming, the operating conditions required by the present invention can be easily satisfied.

すなわち、CPUは予め受信周波数を記憶し表示器に供
給しているが、フルブレークイン・モードを選択すると
、最初の送信でCPUは送信周波数を記憶し表示する。
That is, the CPU stores the reception frequency in advance and supplies it to the display, but when the full break-in mode is selected, the CPU stores and displays the transmission frequency at the first transmission.

CPUはマーク信号の立下シから一定時間のタイマを設
け、その時間内に次のマーク信号が入力すれば表示の送
信周波数をホールドし、所定時間内に入力されなければ
表示は受信部(5) 波数にもどす。このホールドタイムは一般に0.5〜1
秒程度が適肖であるが運用者の好みに応じて調整できる
ようにしておくのが良く、エレキ−の場合にはスピード
調節のVRと連動させると便利である。または送信符号
の短点と長短の長さをソフトウェア・タイマで計測し、
最適値(例えば短点の10倍くらい)を自動保持するよ
うにしてもよい。
The CPU sets a timer for a certain period of time from the fall of the mark signal, and if the next mark signal is input within that time, the display transmission frequency is held; if the next mark signal is not input within the predetermined time, the display is ) Return to wave number. This hold time is generally 0.5 to 1
Approximately seconds are appropriate, but it is better to be able to adjust it according to the operator's preference, and in the case of an electric guitar, it is convenient to link it with VR for speed adjustment. Or measure the short and long points of the transmitted code with a software timer,
The optimal value (for example, about 10 times the dot) may be automatically held.

さらに、周波数表示に限定することなく、モード表示そ
の他の受信と送信で異なる表示に対しても本発明の要旨
は適用できるものである。
Furthermore, the gist of the present invention is not limited to frequency display, but can also be applied to mode display and other displays that differ between reception and transmission.

【図面の簡単な説明】 第1図はCW送受信機の回路構成と周波数構成の説明に
供するブロック図、第2図はCPU制御の送受信機回路
の構成の概要を示すブロック図である。 1・・・アンテナ、2・・・送受切換リレー、3・・・
受信ミクサ、4・・・局部発振器、7・・・キャリア発
振器、8・・・送信ミクサ。 (6)
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram for explaining the circuit configuration and frequency configuration of a CW transmitter/receiver, and FIG. 2 is a block diagram showing an outline of the configuration of a CPU-controlled transmitter/receiver circuit. 1...Antenna, 2...Transmission/reception switching relay, 3...
Reception mixer, 4... Local oscillator, 7... Carrier oscillator, 8... Transmission mixer. (6)

Claims (1)

【特許請求の範囲】[Claims] デジタル周波数表示を有するCW送受信機において、送
信と受信の転換にフルブレークイン動作を選択した状態
では、キーイング中は周波数表示器が送信周波数を保持
するように構成したことを特徴とするデジタル周波数表
示方式。
A CW transceiver having a digital frequency display, characterized in that the frequency display is configured to hold the transmission frequency during keying when full break-in operation is selected for switching between transmission and reception. method.
JP14016582A 1982-08-12 1982-08-12 Digital frequency display system Granted JPS5930330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14016582A JPS5930330A (en) 1982-08-12 1982-08-12 Digital frequency display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14016582A JPS5930330A (en) 1982-08-12 1982-08-12 Digital frequency display system

Publications (2)

Publication Number Publication Date
JPS5930330A true JPS5930330A (en) 1984-02-17
JPH0322109B2 JPH0322109B2 (en) 1991-03-26

Family

ID=15262387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14016582A Granted JPS5930330A (en) 1982-08-12 1982-08-12 Digital frequency display system

Country Status (1)

Country Link
JP (1) JPS5930330A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0226835U (en) * 1988-08-05 1990-02-21
JPH0344942U (en) * 1989-09-07 1991-04-25

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546389U (en) * 1978-09-19 1980-03-26

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7315350A (en) * 1973-11-09 1975-05-13 Akzo Nv NEW AMINOGUANIDINE COMPOUNDS.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546389U (en) * 1978-09-19 1980-03-26

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0226835U (en) * 1988-08-05 1990-02-21
JPH0344942U (en) * 1989-09-07 1991-04-25

Also Published As

Publication number Publication date
JPH0322109B2 (en) 1991-03-26

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