JP3180403B2 - Transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission / reception apparatus of a communication system for performing transmission and reception in a time-division manner by making them different in time.

[0002]

2. Description of the Related Art In a TDMA / TDD transmission / reception apparatus used in a telepoint system or the like, a transmission frequency and a reception frequency are the same. Then, transmission and reception are separated in time and performed in a time-division manner.

[0003] As described above, a period in which transmission is performed (referred to as a transmission packet or a transmission slot) and a period in which reception is performed (referred to as a reception packet or a reception slot) are temporally separated. High use efficiency of transmission channel.

[0004] TDMA for performing such transmission and reception
The transmission circuit and the reception circuit of the transmission / reception device of the / TDD system are:
For example, it is configured as shown in FIG.

In FIG. 6, reference numeral 110 denotes a transmitting circuit,
Indicates a receiving circuit. Then, in the transmission circuit 110,
The audio signal is sent from the input terminal 111 to the digital transmission processing circuit 1
The signal is supplied to the transmission unit 12 and subjected to processing for transmission by the TDMA / TDD method, and the processed audio signal is extracted into a transmission packet.

The digital transmission processing circuit 112
The baseband transmission signal output from the
Is supplied to the 3, it is converted to the modulated signal to a predetermined intermediate frequency signal f _1. Here, in general, a PLL circuit (phase locked loop circuit) is used for modulation by the modulation circuit 113, and a signal frequency-modulated by a carrier signal (intermediate frequency signal f ₁ ) is controlled by the PLL circuit. obtain. Then, the intermediate frequency signal f ₁ output from the modulation circuit 113 is supplied to the mixer 114.

A PLL constituted by a PLL circuit
Frequency signal f output from frequency synthesizer 131
₂ (hereinafter, this frequency signal f ₂ is referred to as a channel selection signal) is supplied to a mixer 114, which mixes the intermediate frequency signal f ₁ with the channel selection signal f ₂ ,
It is converted into a signal f ₃ of the transmission frequency. Then, the transmission signal f ₃ having the transmission frequency is supplied to the antenna 133 via the amplifier 115, the band-pass filter 116, and the high-frequency switch circuit 132, and the antenna 133 wirelessly transmits the signal. The channel selection signal is a signal whose frequency changes according to the frequency of the transmission / reception channel.

On the other hand, in the receiving circuit 120, the signal transmitted during the period of the received packet is received by the antenna 133. Note that the frequency of the reception signal is equal to the frequency of the transmission signal transmitted from the transmission circuit 110.

The received signal f ₃ is supplied to the high-frequency switch circuit 132, the band-pass filter 121 and the amplifier 12.
1 to the mixer 123. And PL
The channel selection signal f ₂ output from the L frequency synthesizer 131 is supplied to the mixer 123, and the mixer 123 mixes the received signal with the channel selection signal f ₂ to produce an intermediate frequency signal f ₁ (first intermediate frequency signal). Is converted. Then, the first intermediate frequency signal f ₁ is
The mixture is supplied to the mixer 125 through the section 24. Then, an oscillation signal f ₄ having a constant frequency output from the local oscillator 126 is supplied to the mixer 125, and the mixture in the mixer 125 is changed to a second intermediate frequency signal f ₅ . This second intermediate frequency signal f
₅ to the demodulation circuit 128 via the bandpass filter 127.
And demodulates the signal demodulated for transmission. The demodulated signal is supplied to the digital reception processing circuit 129,
Processing for reception by the A / TDD method is performed, and the processed audio signal is obtained at the output terminal 130.

In the TDMA / TDD transmission / reception apparatus shown in FIG. 6, the transmission channel selection signal generation circuit in the transmission circuit 110 and the reception channel One frequency synthesizer 131 is also used as a selection signal generation circuit.

[0011]

By the way, in the TDMA / TDD system used in a telepoint system or the like, a transmission packet and a reception packet have a relatively short time. It is necessary to strictly control the transmission timing and the reception timing in the communication. However, for example, in the transmitting / receiving device shown in FIG.
The processing time in the receiving circuit 120 and the transmitting circuit 1
Due to the processing time at 10, the timing actually transmitted from the antenna 133 and the timing received are different. Further, the processing time in the receiving circuit 120 and the processing time in the transmitting circuit 110 change according to actual use conditions such as a change in characteristics due to a temperature change and a change in characteristics of each circuit component over time. Proper control is not possible. Therefore, it is difficult to accurately perform communication at the timing specified by the communication method only by controlling the timing of receiving the signal received by the receiving circuit and the timing of transmitting and transmitting the signal to the transmitting circuit in a constant state.

[0012] In view of the above, the present invention provides a TDMA / TD.
An object of the present invention is to enable transmission / reception timing to be favorably controlled in a transmission / reception device in which communication is performed in a time-sharing manner such as the D system.

[0013]

According to the present invention, as shown in FIGS. 1 and 2, for example, one channel is divided into a transmission packet and a reception packet, and a transmission packet and a reception packet of one channel are transmitted. And a transmission / reception apparatus that performs reception in a time-division manner, a first switch 51 provided on a reception circuit side for switching between a path from an antenna and a path from a transmission circuit, and a path to the antenna and a path to the reception circuit. A second switch 46 provided on the side of the transmitting circuit to be switched, a control means 10 for controlling the first and second switches so that the transmitting circuit and the receiving circuit conduct when measuring the group delay; Is provided through a modulation circuit on the transmission circuit side and a demodulation circuit on the reception circuit side to perform group delay measurement.
Further, in this case, the control means 20 determines the relationship between the guard band time, which is the time between the preset reception packet and the transmission packet, and the time of the end and start times of the actual reception packet and transmission packet. , The measurement of the group delay is controlled. In the case described above
When the group delay measuring means 20 measures the group delay,
Processing using a frequency different from the reception frequency and reception frequency
It is something to do. In the case described above, the group
The delay measuring means 20 detects that the power of the transmitting / receiving device is turned on.
It is designed to work at the moment. Also, the present invention
For example, as shown in FIG. 1 and FIG.
To transmit data and receive data via the receive channel.
In a transmitting / receiving apparatus for receiving data, a transmitting circuit and a receiving circuit
When the power of the circuit and the transceiver is turned on, data is
Use a frequency different from the transmission / reception frequency when transmitting / receiving
The signal of the specific pattern is transmitted to the modulation circuit 41 on the transmission circuit side.
Detected through the demodulation circuit 59 on the receiving circuit side to detect group delay
Group delay measuring means 20 for performing measurement, and group delay measuring means 20
The transmitting circuit and the receiving circuit correspond to the group delay measured by
Timing correction means for correcting timing in communication circuits
Step 10 is provided.

[0014]

In this manner, the group delay time in the transmission / reception device can be determined, and the transmission timing of transmission data to the transmission circuit and the reception timing from the reception circuit can be accurately determined, and is defined by the communication system. Communication can be performed accurately at the timing.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

In this embodiment, the present invention is applied to a TDMA / TDD transmission / reception apparatus. In FIG. 1, reference numeral 1 denotes a microphone, and an audio signal picked up by the microphone 1 is supplied to a digital processing circuit 2, The data is converted into digital data by the processing circuit 2, and the converted digital data is supplied to the frame conversion circuit 3 to be digital data of a transmission packet defined by the TDMA / TDD method. The transmission circuit in the transmission / reception circuit 4 performs transmission processing such as modulation, and transmits the signal from the antenna 5.

The reception signal supplied to the transmission / reception circuit 4 via the antenna 5 is subjected to reception processing such as demodulation by the reception circuit in the transmission / reception circuit 4 and supplied to the frame conversion circuit 3. Then, in the processing in the frame conversion circuit 3, the digital data of the received packet in the format specified by the TDMA / TDD method is converted into baseband serial data, and this serial data is converted into an analog audio signal by the digital processing circuit 2, The converted audio signal is output from the speaker 6.

Here, in this example, transmission and reception in the transmission / reception circuit 4 are performed under the control of a control unit 10 composed of a microcomputer. Further, under the control of the control unit 10, the transmission / reception circuit 4
The group delay time can be measured at

Next, a specific configuration of the transmitting / receiving circuit 4 is shown in FIG.
As a configuration on the transmission side, first, transmission data supplied from the frame conversion circuit 3 via the terminal 4a is supplied to the modulation circuit 41 to be frequency-modulated, and the modulated data is mixed by the mixer 42. To supply. And this mixer 4
In step 2, the frequency signal (channel selection signal) supplied from the PLL frequency synthesizer 43 is mixed with the modulated data to generate a signal of a transmission frequency (transmission channel). Then, the signal of this transmission frequency is passed through a bandpass filter 4.
4. The signal is supplied to the antenna 5 via the amplifier 45, the high-frequency switch circuit 46, and the attenuator 47 and transmitted. In this case, the operating states of the modulation circuit 41, the mixer 42, the amplifier 45, the high-frequency switch circuit 46, and the attenuator 47 are controlled by the control unit 10. Further, instead of supplying transmission data from the frame conversion circuit 3 via the terminal 4a, a random pulse from the measurement circuit 20 can be supplied to the modulation circuit 41.
The supply of the random pulse is performed under the control of the control unit 10.

Further, as a configuration on the receiving side, the antenna 5
The received signal supplied from the filter via the attenuator 47 is transmitted to the high-frequency switch circuit 51 and the band-pass filter 5.
2. It is supplied to the mixer 54 via the amplifier 53. Then, the mixer 54 mixes the channel selection signal supplied from the PLL frequency synthesizer 43 with the received signal,
Obtain a first intermediate frequency signal. Then, the first intermediate frequency signal is supplied to the mixer 46 via the band pass filter 55, and a constant frequency signal supplied from the oscillator 57 is mixed to obtain a second intermediate frequency signal. Then, the second intermediate frequency signal is demodulated by the demodulation circuit 5 through the band-pass filter 58.
9 to demodulate the signal modulated for transmission. Then, the demodulated signal is supplied to the frame conversion circuit 3 via the terminal 4b. In this case, the high-frequency switch circuit 5
The operation state of the controller 1, the amplifier 53, the mixers 54 and 56, and the demodulation circuit 59 is controlled by the control unit 10. The data demodulated by the demodulation circuit 59 is also supplied to the measurement circuit 20 side.

The transmission side and the reception side of the transmission / reception circuit 4 are normally operated alternately in the communication of the TDMA / TDD system. The transmission side and the reception side are simultaneously operated under the control of the unit 10, and the signal obtained by the transmission side modulation circuit 41 is subjected to modulation processing and demodulation processing for transmission and reception, and output from the reception side demodulation circuit 59. It is possible to make it. That is, at the time of measuring the group delay, the high-frequency switch circuit 46 of the transmission system and the high-frequency switch 51 of the reception system are simultaneously operated, and the attenuation process is also performed by the attenuator 47. The signal is supplied to the receiving system without being supplied to the antenna 5 side.

However, when measuring the group delay by simultaneously operating the transmitting side and the receiving side, the frequency of the channel selection signal output from the PLL frequency synthesizer 43 is slightly changed from that at the time of transmission / reception. The processing is performed at a frequency slightly higher or lower than the transmission frequency or the reception frequency. For example, in a telepoint system, 86
A band from 4.05 MHz to 868.15 MHz is expected to be used as a transmission frequency, but when measuring group delay, processing is performed at a frequency slightly above or slightly below this band.

Next, the configuration of the measuring circuit 20 and its surroundings will be described with reference to FIG. 1. A clock generating circuit 21 is provided in the measuring circuit 20, and a clock (clock) output by the clock generating circuit 21 is provided. The system clock of the transmission / reception device is supplied to the frequency divider 22, and the frequency of 1 / N (N
Is 1 or more). Then, the output of the frequency divider 22 is supplied to the random pulse generation circuit 23 to generate a random pulse synchronized with the frequency divided output.

The output of the frequency divider 22 is output to an AND gate 2
The control signal is supplied from the control unit 10 to the other input terminal of the AND gate 24. And
The logical product output of the AND gate 24 is supplied to the counter 25. In this case, the control signal supplied from the control unit 10 to the AND gate 24 is a signal that changes at a timing at which an instruction to output a random pulse is issued.

FIG. 3 shows an example of the configuration of the random pulse generating circuit 23. For example, a clock obtained at an input terminal 23a is supplied to a plurality of D flip-flops 23b and 23.
c, 23d, 23e, and 23f. And each D
The outputs of the flip-flops 23b to 23f are connected so as to be sequentially supplied to the D input of the subsequent stage. In this case, the last stage D
The output of the flip-flop 23f is
After performing an exclusive OR operation with the output of the D flip-flop 23d at g, the signal is supplied to the D input of the first-stage D flip-flop 23b. Then, the final stage D flip-flop 2
The output of 3f is supplied to the output terminal 23h as a random pulse.

The random pulse generated in this way is supplied to the transmission circuit side of the transmission / reception circuit 4. in this case,
The output of the random pulse from the random pulse generation circuit 23 is performed when the group delay is measured by the control of the control unit 10.

The data output from the receiving circuit side of the transmitting / receiving circuit 4 is supplied to a digital PLL circuit 7 and a data latch circuit 8, and the data output from the receiving circuit side is synchronized with the output of the PLL circuit 7. Is latched by the data latch circuit 8. Then, the latched data is transferred to the measuring circuit 20.
The data is supplied to the data collating circuit 26 in the. Note that the output of the PLL circuit 7 is also supplied to the control unit 10.

When the data matching circuit 26 detects the supply of the same pulse data as the random pulse output from the random pulse generation circuit 23, it supplies a match signal to the counter 25 and the latch circuit 27.

In the counter 25, the clock generation circuit 21
Is supplied, and the clock is counted. In this case, the output of the AND gate 24 is used as a count start signal, and the coincidence signal supplied from the data matching circuit 26 is used as a count stop signal. The counter 25 counts in this way, and the counter 25 counts the clock from when the random pulse is output from the random pulse generation circuit 23 to when the data matching circuit 26 detects a match.

Then, the data of the count value is supplied to the latch circuit 27. In the latch circuit 27, at the timing when the match signal is supplied from the data matching circuit 26,
The data of the count value is latched, and the latched data is supplied to the control unit 10 as an output of the measurement circuit 20.

Accordingly, the time data from the output of the random pulse by the random pulse generation circuit 23 to the detection of the random pulse by the data collation circuit 26 is transmitted to the control unit 10 from the measurement circuit 20 by the clock count value. Supplied as data. Here, since the random pulse output from the random pulse generation circuit 23 is a signal that has been subjected to transmission and reception processing in the transmission and reception circuit 4, the time required for transmission processing (T ₁ ) and the time required for reception processing (T _{1 2} ) is added to the count value data (T ₁ + T ₂ ). In the following description, T
_1, the shown values such as T ₂ are time itself, also be used as data indicating the time.

Next, processing of the count value data (time data) in the control section 10 will be described with reference to FIG.

In FIG. 4, reference numeral 11 denotes a rack of the measuring circuit 20.
Indicates the terminal to which the count value data is supplied from the switch circuit 27.
You. Here, the count value data obtained at this terminal 11
Is the time data T described above.₁+ T_TwoThen, this terminal 1
Data T obtained in 1₁+ T _TwoTo the first latch circuit 12
And the latched data T₁+ T_TwoTo arithmetic circuit 1
Supply 3 Reference numeral 14 denotes a data memory,
The transmission packet in the TDMA / TDD system is stored in the memory 14.
Guard band T, which is the time between the received packet and_Threeof
The data is stored in advance and this data T_ThreeTo the arithmetic circuit 13
To supply.

Then, in the arithmetic circuit 13, the time data T
₁+ T_TwoAnd guard band data T_ThreeCalculate the difference between
Data T_FourAnd In this case, the time
Data T₁+ T_TwoIs the guard band data T_ThreeLarger than
Determine how small it is. Then, the obtained data T
_FourIs supplied to the second latch circuit 15 to be latched. Ma
In addition, T₁+ T_Two+ T_ThreeAlso ask for this
Data T₁+ T_Two+ T_ThreeSupplied to the third latch circuit 16.
Feed and latch. Then, the second latch circuit 15
Latched data T_FourTo the third latch circuit 16.
Touched data T₁+ T_Two+ T_ThreeAnd the timing system
Is supplied to the control unit 17 and both data T_FourAnd T ₁+ T_Two+ T_Three
Between the frame conversion circuit 3 and the transmission / reception circuit 4 based on
The data for transmission (transmission packet) and the data for reception
(Reception packet) supply timing and transmission / reception circuit
The operation timing of each circuit in 4 is controlled.

The measurement of the group delay using the measurement circuit 20 under the control of the control unit 10 may be performed when the power of the communication device is turned on or when the communication is started. The latch data T ₄ and T ₁ + T ₂ + T ₃ in the control unit 10 are updated each time the measurement is performed.
Specifically, for example, when the communication device is a telephone,
The hook switch may be operated to turn on the main power supply, or an incoming signal may be received to start communication. In any case, it is necessary to perform transmission and reception in this communication device in a state where it does not interfere.

Next, the control state of the transmission / reception timing based on the measurement result of the measurement circuit 20 under the control of the control unit 10 will be described with reference to FIG.

[0037] A of FIG. 5 shows the setting state of the transmission packet and received packet and between the guard band T ₃ by the communication device of the present embodiment is defined by the TDMA / TDD scheme applied, the guard band T ₃ In the provided state, the transmission packet and the reception packet are alternately wirelessly transmitted. Here, in the communication device of this example, it is assumed that the timing transmitted from the antenna 5 and the timing received by the antenna 5 need to be performed at the timing indicated by A in FIG. Due to the delay, the timing at which the baseband signal for transmission is supplied from the frame conversion circuit 3 to the transmission / reception circuit 4 and the timing at which the baseband signal received from the transmission / reception circuit 4 is supplied to the frame conversion circuit 3 Must be shifted by a time corresponding to the group delay.

Hereinafter, the processing at this timing will be described.
Then, the time is calculated by the arithmetic circuit 13 in the control unit 10.
Data T₁+ T_TwoAnd guard band data T_ThreeLarge difference with
The control state differs depending on the size. That is, T_Three> T₁+ T_Twoso
In some cases, T_Three≤T₁+ T _TwoIs different from when
Is done, T_Three> T₁+ T_TwoWhen
The processing at the timing shown in FIG.
Before or after demodulation for reception)
You. In this case, it is output from the frame conversion circuit 3.
The data of the transmission packet has a guard band time T_ThreeIs over
Time T₁Is output only from before.
Then, based on the output timing, the transmission / reception circuit 4
On the transmitting side performs transmission processing such as modulation. In addition,
Of the baseband demodulated by the demodulation circuit 59 in the communication circuit 4
The data of the received packet has a guard band time T_ThreeIs over
Time T_TwoSupplied to the frame conversion circuit 3 with a delay
Let

[0039] Here, from the end of the packet received baseband until starts outputting the transmission packet of the baseband becomes the time T _4. Therefore, in the processing on the baseband side, the data T ₄ latched by the latch circuit 15 (see FIG. 4) of the control unit 10 is processed until the output of the transmission packet starts after the reception packet ends. From the end of the transmission packet to the start of the reception packet, the data T ₁ + T ₂ + T ₃ latched by the latch circuit 16 (see FIG. 4) of the control unit 10 is reached. Is the guard band time in the processing.

Next, when T ₃ ≦ T ₁ + T ₂ ,
The processing at the timing shown in FIG. 5C is performed on the baseband side (ie, before being modulated for transmission or reception or after being demodulated). Also in this case, the data of the transmission packet output from the frame conversion circuit 3 has the guard band time T ₃
Than the timing of ending the transmission process is performed is outputted from the pre-by time T _1. At this time, only the time T ₄ the transmission packet and received packet overlap. Also, data of the received packet demodulated baseband demodulation circuit 59 of the transmitting and receiving circuit 4 to supply to the frame conversion circuit 3 from Owa guard band time T ₃ with a delay of time T _2.

In this way, by performing processing on the baseband side by shifting the time T ₁ or T ₂ from the end of the guard band time T ₃ , the timing transmitted from the antenna 5 and the antenna 5 The reception timing is the timing as specified by A in FIG. 5, and communication in which transmission and reception are performed in a time-sharing manner can be performed at accurate timing. Then, since this timing setting is corrected every time the group delay is measured, the timing is adjusted in real time, and even if there is a change over time of each component of the communication device or a change due to temperature characteristics, etc. , Time-division communication is always performed with good timing.

However, in the timing process shown in FIG. 5C, while the demodulation circuit 59 outputs the demodulated baseband reception packet data, the frame conversion circuit 3 transmits the transmission packet data to the modulation circuit. Thus, transmission and reception are temporarily performed simultaneously in baseband processing, and it is necessary that the frame conversion circuit 3 be configured to be able to perform simultaneous processing.

[0043] Note that from the measured time data T ₁ + T ₂ can not be determined accurately each time data T _1, T _2, since the ratio T ₁ and T ₂ from the configuration of the reception circuit 4 can be estimated , Each value T ₁ , T ₂ can be determined almost accurately. Alternatively, the values (T ₁ + T ₂ ) simply measured may be divided by 2 to obtain the values T ₁ and T ₂ .

In this embodiment, when measuring the group delay, the PLL frequency synthesizer 4 in the transmission / reception circuit 4 is used.
3 is slightly changed from the transmission / reception frequency so that the transmission frequency or the reception frequency is processed at a frequency slightly higher or lower than the transmission frequency or the reception frequency. This is done using By doing so, there is an advantage that even if the group delay is measured, it does not interfere with other communication devices.

As described above, at the time of group delay measurement, processing is performed at a frequency slightly higher or slightly lower than the transmission frequency or the reception frequency. However, when a plurality of channels are prepared as communication channels, Alternatively, the group delay may be measured using a channel on which no communication is being performed. Alternatively, when a plurality of channels are prepared as communication channels and all the channels are in use, a group using the channel with the smallest reception carrier (that is, the channel that is least likely to cause interference) is used. The measurement of the delay may be performed.

Although the random pulse output from the measuring circuit 20 at the time of measuring the group delay is generated by the random pulse generating circuit 23, the random pulse stored in the memory may be output.

Further, the present invention is not limited to the above-described embodiment, but may take various other configurations.

[0048]

According to the present invention, the group delay time in the transmission / reception device in the actual use state can be determined, and the transmission timing of transmission data to the transmission circuit and the reception timing from the reception circuit can always be accurately determined. In addition, it is possible to always accurately communicate at the timing specified by the communication method.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram of a transmission / reception circuit of one embodiment.

FIG. 3 is a configuration diagram of a random pulse generation circuit applied to one embodiment.

FIG. 4 is a configuration diagram of a control unit according to one embodiment.

FIG. 5 is a timing chart for explaining one embodiment;

FIG. 6 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 3 Frame conversion circuit 4 Transmission / reception circuit 10 Control unit 17 Timing control unit 20 Measurement circuit 23 Random pulse generation circuit 25 Counter 26 Data collation circuit 27 Latch circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 5/18 H04B 1/54 H04J 3/00 H04L 27/00

Claims (5)

(57) [Claims] 1. A transmission / reception apparatus which divides one channel into a transmission packet and a reception packet, and performs transmission and reception on the transmission packet and the reception packet of the one channel in a time division manner. A first switch provided on the receiving circuit side for switching between a path from the circuit and a second switch provided on the transmitting circuit side for switching between a path to the antenna and a path to the receiving circuit; A control unit that controls the first and second switches so that the transmission circuit and the reception circuit conduct when measuring the group delay; and a modulation circuit on the transmission circuit side for transmitting a signal of a specific pattern. A transmission / reception apparatus comprising a group delay measuring means for detecting a group delay through the demodulation circuit on the receiving circuit side and performing group delay measurement. 2. The transmission / reception apparatus according to claim 1, wherein said control means includes a guard band time which is a predetermined time between said reception packet and said transmission packet, and an actual reception packet and transmission packet. A transmission / reception apparatus for controlling the measurement of the group delay in relation to the end time and the start time. 3. The transmitting / receiving apparatus according to claim 1, wherein said group delay measuring means measures a transmission frequency when measuring the group delay.
Process using a frequency different from the wave number and reception frequency
A transmission / reception device characterized by the above-mentioned. 4. The transmitting and receiving apparatus according to claim 1, wherein said group delay measuring means is turned on or off by a power supply of said transmitting and receiving apparatus.
A transmitter / receiver that is designed to operate when it is dropped. 5. Transmitting transmission data through a transmission channel.
Transmit and receive data via the receive channel.
In the receiving device, when the power of the transmitting circuit, the receiving circuit, and the transmitting / receiving device is turned on, data is transmitted / received.
Using a frequency different from the transmission and reception frequency at the time of signal, especially
The signal of the fixed pattern is transmitted to the modulation circuit on the transmission circuit side and to the reception circuit.
Group delay measurement by detecting through the demodulation circuit on the communication circuit side.
Performing the group delay measurement means and the group delay measured by the group delay measurement means.
To compensate for the timing in the transmission circuit and the reception circuit.
Timing correction means for correcting
Transceiver.