JPS5930313B2 - Connected pattern extraction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus that sequentially executes pattern cutting processing when performing pattern recognition, and relates to an apparatus that extracts connected patterns such as numbers and alphabets.

In pattern recognition, especially optical character recognition, in order to recognize individual characters, it is necessary to restrict the position and size of the pattern in advance, or to add marks to indicate the boundaries of the pattern. It was difficult to cut out high patterns.

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus for cutting connected patterns from an input pattern free of the above-mentioned constraints.

In the present invention, a quantized pattern storage section, a connected pattern propagation logic network, a connected pattern storage section, and their respective detection mechanisms are configured to sequentially extract connected patterns from a quantized pattern sequence and subsequently send them.

According to the present invention, by combining relatively simple circuits, continuous patterns can be cut out accurately and at high speed, no matter how complex the pattern is, as long as it satisfies the condition that it is connected. I can do it.

Next, a detailed description of embodiments of the present invention will be given.

First, an example of extraction of a connected pattern according to the present invention will be shown, and then a description will be given of a device that implements the extraction. 1 in FIG. 1 is the input pattern. 11 is obtained by quantizing this by the input pattern quantization section. The pattern is scanned in the direction of arrow 1a and sent to the quantization pattern storage unit as signal 11, and the remaining pattern is moved in the direction of arrow lb,
The next row is sent as signal 11 to the quantization pattern storage. iii is a quantization pattern storage unit in which the pattern input as signal 11 is shifted in the direction of arrow ld, and each time the pattern is shifted by one column, the detection signal is changed to arrow 1c in the leftmost column.
Run in the direction of. No concatenation pattern is detected here.
When the pattern repeats the shift and becomes like I, the detection signal detects the first connected pattern at mesh 1e. Here, the first connected pattern is extracted into the connected pattern storage section by the connected pattern propagation logic network.
This is v. Extraction was performed here. This concatenated pattern is sent as a signal 21 to the pattern recognition device. Further, when the extraction is completed, the extracted connected pattern on the quantization pattern storage section is erased and becomes like Vl. Thereafter, the detection signal detects the second connected pattern at the mesh 1f, and cutting is performed in the same manner as before. Next, the configuration of the apparatus according to the present invention will be explained with reference to the drawings.

The overall block diagram of the present invention is shown in FIG. 1
The input pattern quantization unit of Fly Ink scans the input pattern in a two-dimensional array, converts the shading at each quantized pattern position into binary values, and outputs the result. Spot. This is a known OCR scanning mechanism such as a scanner or a vidicon, and its details will be omitted.

Signal 11 is its output. The connected pattern extracting section 2 consists of three layers: a quantization pattern storage section 4 and its detection section 40, a connected pattern propagation logic network 5 and its detection section 50, and a connected pattern storage section 6 and its detection section 60, which will be described later. Reference numeral 21 indicates the extracted pattern and serves as an input to a known pattern recognition device. Further, a signal 32 is a control signal sent from the detection section of each layer to a control section to be described later, and a signal 31 is a control signal from the control section 3, which controls the operations of the input pattern quantization section and the connected pattern extraction section. The configuration of the connected figure extraction unit 2, which is the main part of the present invention, will be explained below using detailed partial diagrams.

FIG. 3 is a block diagram of the quantization pattern storage section 4 (hereinafter abbreviated as storage section 4), and the left end is the detection section 40 thereof.

As shown in the figure, the storage section 4 has shift registers 41 arranged in series in an array corresponding to pattern scanning, and the input pattern 11 is serially shifted in the direction of the arrow by a clock 41i of the shift register. All outputs 4 of the leftmost column of the shift register (i.e., the leftmost column of the processing pattern)
0a, 40b, . . . , 40c are supplied to an 0R gate 401, and its output 40t is an extraction start signal to the control section. Shift register 41 has 1-bit information and its output 41t is determined by clock 411 and clear signal 41c. FIG. 4 is a configuration diagram of the connected pattern propagation logic network 5 (hereinafter abbreviated as logic network 5).
It is equipped with

The processing pattern detection signal 52s is always 0N, 521 is the clock of the detection shift register 501, 52c is also a clear signal, and 50a, 50b, . . . , 50c are the outputs of each detection shift register 501. Signals 40a, 40b, . . . , 40c and 50a, 50b, from the storage unit 4
-50c (DAND is taken and the respective outputs are supplied to the 0R gate 502, and the output 50t is a cutout signal of the connected pattern. In the logic network, the logic cell 51 receives input from adjacent cells 51x, 51y, . . . ,5
Take 1z and send out 51s as output. FIG. 5 shows the relationship between the shift register 41 of the storage section 4, the propagation cell 51 of the logic network 5, and the shift register 61 of the storage section 6, which will be described later.

The shift register 41 receives the aforementioned signals 41, 45, 41.
s. In addition to 41t, the output 61t of the shift 6 register 61 is supplied as a clear gate signal. 41t also serves as an input to the logic cell 51. shift register 6
1 is the input 61s, the clock 611, the load signal 61j,
In addition to the clear signal 61c and the output 61t, the output 51s of the logic cell 51 is taken as a parallel input. Figure 6a shows
FIG. 4 is an explanatory diagram of a shift register 41. FIG.

411 clocks 411, 41c' is a clear signal, 4
It is a 1-bit shift register with 1s as input and 41t as output, 412 is an AND gate, and shift register 4
The clear signal 41c of 1 and the output of the shift register 61 are input.

Therefore, only when both the clear signal 41c and the signal 61t are 0N, the clear signal 41d becomes 0N and clearing is performed. FIG. 6b is a logic circuit diagram of the logic cell 51.

The outputs 51x, 51y..., 51z of adjacent cells are set to 0.
The output 52t and the output signal 41t from the shift register 41 are connected to an AND gate 5'1.
Supply to 2. Its output 51s is sent to the adjacent logic cell. That is, when the output of the shift register 47 corresponding to this logic cell 51 is 0N and the output of at least one of the adjacent logic cells becomes 0N,
41t1)SON and 52t become 0N, and the output of the logic cell 51 becomes 51s/)SON. Therefore, if the output of at least one of the logic cells corresponding to the shift registers in the connected pattern in the storage section 5 is set to 0N, this will be propagated to the other logic cells as well. This allows extraction of connected patterns to be performed accurately and at high speed. FIG. 7 is a configuration diagram of the connected pattern storage section 6 (hereinafter abbreviated as storage section 6) and its connected pattern end detection section 60. The signals 611, 61j, 61s, and 61t are the same as described in FIG. The signal 21 is a signal that is pushed in the direction of the arrow mentioned in FIG. 2 and sends out a connected figure, and the input signal 600 is taken from the ground and is always input as 0FF. The signal 60s is a detection signal from the control unit and becomes 0N when shifted by one column of shift registers, and the output of the 0R gate 611 becomes 0FF only when the output signals of each shift register in the leftmost column are all 0FF. ,
It is changed to 0N by an inverter 613, and the output 60t of the AND gate 613 becomes 0N. If even one of the inputs of the 0R gate 611 is 0N, the output 60t becomes 0FF and becomes a detection signal. The control section 3 in FIG. 2 generates the various control signals described above in order to realize the following operation explanation, and this can be easily accomplished by a person skilled in the art using a sequential circuit. , the explanation thereof will be omitted. Next, the operation of the above device will be explained in detail. Although the configuration of the apparatus shown in FIG. 2 has already been described, the basic flow of operation will be explained first. The input pattern 11 quantized from the input figure quantization unit 1 is temporarily stored in the storage unit 4, and the detection configuration 40 detects a connected pattern to be extracted.
When a pattern is detected, a connected pattern is extracted by the logic network 5 and stored in the storage section 6. When this storage is performed, the extracted connection pattern in the storage unit 4 is deleted. Finally, the connected pattern cut out in the storage section 6 is sent as an output 21 to the pattern recognition device. The specific operation will be explained below.

The pattern sequence 11 quantized by the input pattern quantization section is shifted and stored in the storage section 4 one bit at a time. The control section 3 counts the clock 411 with a counter, and stops the clock 411 when one column of information of the quantized pattern has been stored in one column of the shift register of the storage section 4, thereby stopping the shift. At the same time, the pattern input scanning of the input pattern quantization unit is temporarily interrupted. At this time, if at least one of the outputs of the registers in the leftmost column is 0N, the output 40t of this detection section 40 becomes 0N, which causes the control section 3
It becomes a connected pattern extraction start signal. Conversely, when all the outputs of the registers in the leftmost column are 0FF, 40t becomes 0FF, and the pattern input operation for the next column is restarted until all the information in the leftmost column is sent out again. During pattern input operation, clear signal 41c1I! ．． 0FF
It is. When the connected pattern extraction start signal 40t is generated, the control section 3 stops the clock 411 of the storage section 4, outputs a clear signal 52c to clear the detection shift register array 501, and then generates the clock 521 to clear the detection shift register array 501. Perform a serial shift within column 501. The output of each shift register is logically ANDed with the output of the register in the leftmost column of the storage section 4, and the logical sum of the respective AND outputs is obtained by the 0R gate 502.
The output will be 50t. Here, 50t becomes 0N when the most significant 0N bit of the concatenated pattern to be processed is detected, and this 50t is sent to the control section and becomes an extraction start signal. Also, at this time, one logic cell corresponding to the above-mentioned detected position of the logic network 5 becomes 0N and propagates into the connected pattern one after another. When cutting is started, the storage section 6 is shifted after the propagation of the connected pattern has stabilized. The load signal 61j of the register 61 is input, and the logic cell 51
The output 51s is taken into the shift register 61. As a result, only one connection pattern connected to the detected bit is set in the storage section 6. At this time, the output 61t of the shift register 61 of the cut out portion is 0N, and the AN with the clear signal 41c of the shift register 41 is
When D is taken and the clear signal 41c is set to 0N, the signal 41c' becomes 0N and the shift register 41 is cleared. That is, the cut out connection pattern is stored in the storage unit 4.
will be canceled above. Now, after the connected pattern is cut out on the storage section 6, a clock 611 is generated from the control section 3.
The cut information is sent to a subsequent pattern recognition device.
At this time, the input 60s of the concatenated pattern end detection section 60 is set to 0N every time one column of the shift register is sent out. If the connected pattern remains, the signal 62t becomes 0FF, and therefore the output 60t of the connected pattern end detection section 60 becomes 0FF. At this time, the sending operation is continued again. Conversely, when the leftmost row is the end of the concatenated pattern, all bits are 0FF, so the signal becomes 62tit0N, and therefore the output 60t of the concatenated pattern end detection section 60 becomes 0N. ,, is sent to the control section 3, and the control section 3 uses the clock 6 of the storage section 6.
11 is stopped, the clock 411 of the storage section 4 is generated again, and the operation of inputting the connected pattern is started again. In this way, the connected pattern is extracted. Finally, applications of the present invention will be described.

Here, we used an example in which the direction in which the input pattern is scanned and the direction in which it is shifted in the input pattern quantization section are the same, but the shift register can be shifted in two directions even if the direction in which it is scanned and the direction in which it is shifted are different. If you use , you can perform cutting. In addition, here, the detection part of the cutting pattern is set to the leftmost edge, but if you want to perform cutting from the left 45 detection direction, for example, the detection part is set to the right 45 detection direction.
It can be set according to the purpose, such as arranging them in a 5° direction. Furthermore, information on the cutting position can be stored by counting the number of shifts until the cutting starts.

[Brief explanation of the drawings] Fig. 1 is a diagram showing changes from an input pattern to an output pattern, where 1 is the input pattern, D is a pattern obtained by quantizing the input pattern, and Iiii and i are the quantized pattern stored in the quantized pattern storage unit. The pattern, v, is a pattern extracted to the connected pattern storage section, and Vi is a diagram showing that the pattern cut out to the connected pattern storage section is erased on the quantized pattern storage section. 2 is a block diagram of the entire apparatus of the present invention, FIG. 3 is a block diagram of the quantization pattern storage section 4 and the detection section 40, FIG. 4 is a block diagram of the connected pattern propagation logic network 5 and the detection section 50,
FIG. 5 is a connection relation diagram between the shift register of the quantization pattern storage section 4, the logic cells of the connected pattern propagation logic network 5, and the shift register of the connected pattern storage section 6, and FIG.
The figure is an explanatory diagram of the shift register 41 of the storage unit 4. Figure 6b is a circuit diagram of the logic cell, and Figure 7 is a diagram of the connected pattern storage unit 6.
and a configuration diagram of a detection unit 60.

Claims (1)

[Claims] 1. An input pattern quantization unit that scans and quantizes a plane pattern into a two-dimensional array and into binary values, and a quantization pattern storage unit that is composed of a plurality of storage elements and temporarily stores the quantized input pattern. , a detection mechanism that detects the presence or absence of a concatenated pattern to be extracted based on the output of a specific storage element of the quantization pattern storage section, and generates an extraction start signal; A connected pattern propagation logic network in which the extraction start signal is propagated to the logic cell corresponding to the connected pattern, and a connected pattern propagation logic network that temporarily stores the connected pattern extracted by the connected pattern propagation logic network, and a connected pattern storage section having a means for erasing an extracted connected pattern portion of the input pattern on the converted pattern storage section and a means for sequentially outputting already connected patterns; A connected pattern extraction device comprising: a detection mechanism that detects the end of output of a connected pattern based on the output of a specific storage element of the section; and a control section that generates control signals necessary for each of the sections and mechanisms.