JPS5930070A - Inspection of large scale memory apparatus - Google Patents

Abstract

PURPOSE:To make it possible to rapidly perform memory inspection up to the level of the bit position of a memory unit without adding a special bit for inspection to a large scale memory apparatus. CONSTITUTION:An inspection pattern generating circuit 5, a comparison operation circuit 6 and an error position detecting circuit 8 are added to a large scale memory apparatus to be inspected and the memory part 1 of the above mentioned memory apparatus is divided into a plurality blocks MB1, MB2... each having a same size while the inspection pattern from the inspection pattern generating circuit 5 is written in a plurality of the divided blocks and one of said blocks is used as a reference block while the other blocks are used as the blocks to be inspected to successively read stored contents written in the reference block and the blocks to be inspected in parallel according to the order in the arrangement of a memory unit constituting each block. In the next step, the read-out signals are inputted to the comparison operation circuit 6 to compare the conformity and the inconformity of the read-out signals up to the bit level of the above mentioned memory unit and, if there is an inconformity memory unit, the error place of the blocks to be inspected is detected from the positional information of inconformity and the address information of the memory unit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a memory device, particularly a large-scale memory device such as an image memory device that includes semiconductor memory elements as a component.

It is a large-scale memory device that uses semiconductor memory elements as a component, and is currently used for image data.

In other words, an image memory device is typical, and it is used as a buffer memory when inputting and outputting 0i11 image signals, or as a total of 1I
It is used as external memory for the machine.

In the case of image memory, since the number of information in one image data is large, 1, for example, just storing 1&'&30 frames of 1 frame A312X5121i1i111, that is, 1 second, is 7.5 MIfi elements (1 memory unit consisting of 8 bits) Assuming the pixel representation, 6
A memory device with a large capacity (0M bits) is required.

U when using such a large scale memory device.

It is necessary to perform memory inspection periodically or at any time, check for defective memory elements, and take measures such as replacing the defective memory element or board with a good one.

Conventionally, as a memory inspection means for this glazed memory device, a computer is used to check specific data D by a program.
6 is written to the memory, and the data DI that continues this is D.
A method is known in which a complete judgment is made as to whether or not the data matches o, or a method 1 in which an error is detected by adding a special bit for checking to the data stream bits, such as a parity check method. However, in the former case, there is a problem that memory inspection takes time due to limitations due to computer processing speed and bus speed. On the other hand, the latter requires extra bits other than those for data, and the sparity check cannot identify error locations down to the bit position level.

The present invention takes the above situation into consideration, and enables large-scale memory devices without adding special pins (ff-) for inspection.
It is an object of the present invention to provide a method for testing a large-scale memory device that can quickly perform memory testing down to the bit position level of a memory unit without using a computer.

A method for testing a large-scale memory device according to the present invention has achieved such an object, and a test pattern generation circuit, a comparison calculation circuit, and an error position detection circuit are added to a large-mimum-sized memory device to be tested, and the memory portion of the memory device is Divide into a plurality of blocks of the same size, and write the test pattern from the test pattern generation circuit into all the divided blocks or into a plurality of blocks that can be safely inspected.

Let one of these blocks be fL - the reference block and the other be the tested block, and let the reference block and the tested block be
4. The stored memory contents are sequentially output in parallel according to the arrangement order of the memory units constituting each block, and the successive signals are manually inputted to the above-mentioned comparison circuit to read out the match/mismatch of No. 13. are compared down to the bit-level of the above memory units, and if there is a mismatched memory unit.

Output the position information of the mismatched pit in the memory unit,
The above error position detection circuit detects a mismatched memory unit.
Error locations in the block to be inspected are detected down to the bit position level of the memory unit based on the position information of the mismatched bits and the memory unit address information output from the memory device, and similarly, all blocks to be inspected in IA and RI are detected. This is done using a method that is characterized by a one-order test.

A large-scale memory system f? An embodiment of the inspection method of i will be described with reference to the drawings.

Figure 1 F:J: A row of test circuits implementing the method of testing a large scale memory device fl according to the present invention.

In FIG. 1, l is a memory unit storing 1Ihl image data, MB l , MB 2 . ...is memory section 1
2 is a memory access machine that can access 10 memory blocks, 3 and 4 are memory blocks that are divided into individual memory blocks of the same size, and 4 are connected to the image input/output device and control data input/output operations. input/output controller that performs
l'1. P2 is the content of the memory extracted via the input/output controller 3.4, 5 is the test pattern generation circuit,
6 is the memory gatekeeper P1. Comparison rjI circuit for P2.

7 is a determination circuit, 8 is an error-1 upright detection circuit, 9 is a recording device, Elt is the calculation ζr output in the comparator circuit 6, and E2
is the judgment output in the judgment) circuit 7, E3 is the error position information obtained from the error position detection circuit 8, and 10.11 is t
h image input device, 12.13 is image output (display) device, D
II and DI2 are image input paths, and DDI and DD2 are image output paths.

5WI-8W3 are switches, ■ to ■ are switching terminals of the switches, and A1 and A2 are address information at the time of memory access sent from the input/output controller 3.4 to the error position detection circuit.

ll! Although it does not have any essential meaning in the image input/output devices 10 to 13, the image memory device is generally used in connection with the image input/output device. The memory access control portions of the memory access mechanism 2 and input/output controllers 3 and 4 are not newly prepared only for memory inspection, but are for one image input/output device. This is added to FIG. 1 to clarify that it can also be used for memory testing simply by switching the
57 hY and ql different 4 arrows =,! 1
'#ll il)J](・& etc.) It can be said that this is an extremely effective method.The memory inspection means will be explained step by step below.

(υ First, in the image memory unit 1, the memory location to be inspected (partially τ in the entire memory device) is divided into multiple blocks MB of the same size NxXNy pixels (corresponding to a memory unit consisting of 4!r - 8 bits of water line). 1, MB 2・
Divide into... This division is a software division to increase the unit of access to the memory section, and it is not necessarily necessary to divide the memory section in terms of hardware. Also, the block size NXXNy can be set to any size that can be created by the memory access device ##2.
The size is set to 2×512 pixels).

(2) Connect the switch SWI to the terminal (p), and transmit the test pattern generated by the test pattern generation circuit 5 to the input/output controller 3 and the memory access mechanism 2.
After all, memory (fill each block MB1.MB2
．． ... speed f! Praise for tf+.

The same test pattern is written in each block. As this test pattern, for example, all bits are 1. All bits θ etc. are used, but the pattern of No. 1 may also be used.

(3) Select an arbitrary block MBs from blocks MB l , MB 2 . . . as a reference block.

(Of the 41 reference blocks MBs, 1 is the block to be inspected MBt using the input/output controller 3 (VIBL is M
Bs) is read out using the input/output controller 4 at a speed f2. Contents of the read memory P1. P
2 is sent to the comparator circuit 6 by connecting the switch 5 Number of sheets flock 1VIB1. MB2.・
・Of those divided into ’lI! , the same pattern for 澾ﾆ: is written in the quasi blog 2 ff 2.

It is a diagram showing the states that appear one after another in the 11th order of the entire pixel arrangement of these illusions L6. For convenience of explanation, it is assumed that data is stored in the blocks MBs, Mj3t, and Kt in the form of a two-dimensional array.

Bladder extraction is performed sequentially from the first pixel l8 (1.1) and It (1.1). 911 as shown in Figure 2.

At a certain point in time, the block MBs (11.j+)
th pixel l5(is ajs) * block MB
(r1*j1)th pixel It(11SJI
) is simultaneously outputted and sent to the comparison calculation circuit 6. That is, the contents of blocks MB s and MB t are considered to be a screen, and a memory check is sequentially performed on pixels located at the same position on one screen.

(5) In the comparison calculation circuit 6, the bladder output contents P1. from the reference block MBs. EXOR ( Exclu
sive OR) operation.

Figure 3: By EXOR operation in bit units.

This shows that an output corresponding to the match or mismatch of the indulgence contents PI and P2 can be obtained.

Read content P1. MSB if P2 matches
(Most 51gn1ficant Bit) from the b7th bit, LSB (Least 51gn1
1111 t, content P1. P2 EXO
If all the R calculations are performed, 0 is obtained, and therefore 0 is obtained as the output El of the comparison calculation circuit 6 as shown in FIG. For the mismatched bits, the EXOR operation results 1, and a non-zero value is obtained as the output El, as shown in FIG. If not, the bit position that is l in the output E1 indicates the error position at the bit level of the memory unit of the read content P2 and therefore the marriage check block. If ψj is incorrect, the b2th bit of the pixel start-up content P2 is incorrect, the read content PI.

The EXOR operation result of the b2th bit of P2 becomes 1,
As shown in FIG. 3 (bl), the b2 focus of the calculation output E1 becomes 1.

(6) Calculation output]! ;L is a Koni judgment 1! At J Road 7, all parties decide whether or not it is true. If the calculation output is non-zero, it means that a memory error has been detected, so 1 judgment circuit 7
notifies the error position detection circuit 8 of this fact through the judgment output E2 (however, it is the same as the calculation output El).

+71 The error position detection circuit 8 receives memory access address information @Ax from the input/output controller 3.4.
A2 indicates the address in the memory section of rIiJ where the error was detected, and also determines which focus point in the judgment output E2 is 1. demand. This makes it possible to completely identify error positions down to the bit position level.

(8) The output E31 of the error position detection plane IM8, that is, the address of the error pixel and the position information of the mismatched bit of the error pixel, etc., is sent to the error position recording ferric acid 9. The recording device 9 displays the error position in coordinate format or prints it out.

Processing is performed to record the error position detection results in dC, such as recording H1 on a disk or the like.

(By sequentially switching T test blocks and test blocks for 91 reference blocks MBs and performing test processing according to (41 to (8)), it is possible to perform a memory test on the entire memory location to be tested.

In the case of the above memory test procedure, the write speed f+ of the test pattern in (2) and the read speed f2 in (4) should be set to the M island operating speed fmax of the memory device as the most stable state. tX'OT toothhi,
Furthermore, the processes in (5) to (8) can be performed at fmax simultaneously with reading out the test pattern from the #'f1 memory section using the current digital processing circuit technology. This means that, in the case of the present invention, the memory test can basically be performed in a time similar to that required for loading and reading the test pattern into the memory section.

For example, in the case of a 25-image memory device with a high operating speed fmax of 10 to 14 M! -12! Since it is possible to input and output data at a sampling frequency of s', a value of 10 to 14 M data/second can be obtained. Therefore, according to the present invention, it is possible to realize a memory test that is much faster than a memory test method that uses one calculation at a time.

Of course, the inspection processing speed can be kept at a slower speed, but 1. Considering that the memory dissipation of the memory device is large, the maximum operating speed f of the memory device is
It would be better to do the m a x″'C'C test because it would take less time to spend on the test (this is the J plan).

The above is the basic memory testing procedure for the transverse method for large-scale memory devices according to the present invention, but the following two points must be noted. First of all, it is insufficient to test the memory simply by using -1 different test patterns. That is, for example, when inspecting a pattern of all pits 1, an error such as O'''C which should be 1 cannot be detected.Contrary to this:

It would be better if you could also take measures such as performing an inspection using a pattern with all the focus points at 0.

Next, in the above inspection procedure (5), the reference block MBBF
Is c assumed that there is no error? 2I: Semi-block MB
The point is that even if there is an error in s, it will still be possible. In contrast, since errors are always detected at the same position for each block to be inspected, the reference block MBs
It can be determined if an error occurs. Therefore, by selecting another block as a new reference block and performing inspection processing, gradient usability can be achieved.

Note that the differences in horizontal and vertical curves between the present invention and the memory testing method using the Hi-don machine are as follows. 1 frame 512x5121! It is 1/4 M u
! Let's consider it in terms of each image of the u-line. II! ll
In the case of an image processing device, the image data can be processed at the frame rate of all television images, that is, the speed of 30 frames per frame, so if the present invention is used, both 1 and 1 can be processed. For the frame, it takes 1/30 seconds to write the test pattern, and 1/30 seconds to send it out from the hospital.The inspection process is performed at the same time as reading, so the time spent on inspection processing is within the time spent on reading. You can take it easy and do 4 moxibustion tests for 1 plant and treatment pattern in 2/30 seconds. On the other hand, VX, writing and reading of specific data, '4
Even if we take a little look at the input/output and arithmetic processing of Iso-C, there is a total of things like determining the match/mismatch between read data and read data. It takes about 11 cables and 10 instructions, and the total time is 2.5 seconds (-10 μs x 1/4 M
(pixels) it takes (however.

The processing power of a computer is defined as IMIPS. ).

In addition to this, the main memory of the ITI computer and the
The data transfer time between the memory device and the memory device is speed + z.
Assuming that the iM bytes/second bus was at least 17
2 seconds (-2X (1/4 M) / (], M))
In the end, it takes about 3 seconds in total for the test pattern. In reality, it is thought that it will take even more time if overheads during transfer are taken into account. Therefore, according to the present invention, it is possible to perform a memory test in a short time of about 1/-50 compared to the 4tA& method using the cylindrical method.

Next, regarding the present invention, it is possible to add some features to the basic inspection procedure based on FIG. 1, which will be explained below.

First, in the present invention, it is possible to read the test pattern from the memory section I and simultaneously display the result of the memory test, that is, the output E1 of the comparison calculation circuit 6, as a two-dimensional pattern (in image format). Error locations can be easily checked visually. Fig. 4 shows what changes should be made to the configuration of Fig. 1 in order to realize this.

■; minute surrounded by a broken line corresponds to the changed part. In FIG. 4, 14 is a look-up table or level conversion circuit (hereinafter referred to as look-up table), SW4 is a switch, and ■■ is a switching terminal of switch SW4. Connect switch SWd to terminal ■2. Comparison calculation circuit 6
The output El is sent to the image display device 12 via the lookup table 14. 1IlII If a television monitor is used as the image display device 12, if the block size is set to the screen size that can be displayed on the monitor or smaller, and if all the blocks are output one after another in accordance with the frame rate of the television, the cool summer output You will get a display screen that matches your needs. At the error point, a non-zero output is obtained for the picture, so it is displayed as a bright dot on the monitor.On the other hand, at 615 minutes without an error, a zero output is obtained, so it is displayed as a black level. Is displayed. If you look at the six-line screen, you can easily determine which 1i111 element in the block has an error based on the position of the brightly displayed point.

Note that the lookup table 14 can be used, for example, by transmitting the bit pattern of the calculation output El as it is to the monitor 12 as one image output and extracting it, or if the calculation output E1 is non-zero, It can also be used to transfer values to a display device. In the former case, the calculation output El for the error location on the 6° monitor screen
A dot with a brightness corresponding to the bit pattern is displayed. In other words, the closer the error location is to the MSB side, the brighter the %LS
Closer to the B side d: Displayed darkly. Therefore, the position of the error bit can be estimated from the brightness of the displayed point, but even if there is a call at Vrr, BS, the display may be too dark to make out /(j). In the case of Tawara and Ministry, 1211 on both monitors 101 and 1211 are dot-stitched with a constant brightness.
The number one spot is clearly indicated.

Next, going back to the main departure point 1, a return route is set in which the internal PI read from the memory section 1 or the output E1 of the comparison calculation circuit 6 is re-introduced.

Also, by adding the auxiliary +il''JL and the memory access machine from the computer (・^), you can make memory allocation more flexible.
Use the r body diagram to draw t+h', Yu'. Figure 5 is a modified version of Figure 1, with the parts surrounded by broken lines corresponding to the changes. Note that the changes rt;i=r in FIG. 4 are also added to FIG. In Figure 5, there is an input/output controller for feedback to the 15 digits. I' may be the same as the input/output controller 3.4, but may be of lower power. 16 is a mechanism for controlling memory access from the auxiliary meter.

17 Yusuke Bl'μ, SWS is terminal ■, [Co., Ltd.] It is a switch that does not change all. Switch SWS to terminal [Co., Ltd.]
By connecting the switch SV/2 to the terminal ■, switch SW4' (c to the terminal ■)
11. In this case, the gatekeeper for reading from the memory section is the input/output controller 3. Switch fSW2. Switch SW4, switch SW5. After the input/output controller 15, the data is written to the base memory section.
An arbitrary inspection pattern that is difficult to generate in the pattern generation path 5 is generated by the auxiliary # calculator 17, written to one block of the memory section via the memory access control mechanism 16, and written to another block. It is also possible to import this ITK check pattern to all blocks at high speed through all feedback routes, that is, at the maximum operating speed of the memory device. - million switch SW2.

If SW3 and SW4 are connected to terminals ■, ■, and ■, respectively, the calculation output is 1! 1 is written into memory iB 1, and it exits the memory access machine (h16) and uses the auxiliary d1 calculation W17 to analyze the test results, check the tendency of memory error occurrence, and detect the error again. It becomes possible to perform inspections using an auxiliary computer for the locations.

As explained above, according to the method for testing a large-scale memory device according to the present invention, it is possible to test a large-scale memory device without requiring special bits for testing other than data bits.
Also, without using a computer, at the maximum ψ effort speed of the memory device,
It takes about 1,750 hours to perform the test when processing using a computer, and the results can be plotted and displayed on a monitor screen, or displayed as bright spots on a monitor screen so that they can be identified at a glance. Although the image memory device for top-side one-image data has been described and explained, the present invention can be widely applied to the inspection of general large-scale memory devices regardless of the type of data, using exactly the same method. Is possible.

[Brief explanation of the drawing]

Figure 1 shows the method of testing large-scale memory capacity according to the present invention. FIG. 3 is an explanatory diagram illustrating the principle of calculation for detecting a memory error from the gatekeeper P2 of the reference block contents PL'tl check block using the circuit shown in FIG. 1; Figure 4 is an illustration of the part shown in Figure 1 that has been modified to display the result of the memory error detection calculation in circuit 1'' as a two-dimensional pattern, and Figure 5 is the diagram shown in Figure 1. 2 shows the circuit configuration diagram of the auxiliary device, memory access 4N structure, and input/output controller for feedback. In the drawing, l is the memory section. 2 is the memory access mechanism. 3.4.15 is the input/output controller. 5 is a test pattern generation circuit, 6 is a comparison calculation circuit, 7 is a judgment circuit. 8 is an error position detection circuit. 9 is a recording device. 10.11 is 1 ion input device IM-, 1
2.13 is the 1LiII unit output device. 】4 is lookup table 1 (i is memory access machine 4i6 from auxiliary 11 calculation
゛. x 7 t:i: Auxiliary fft g Irot≧, SW
I to SW5 are switches. Special Edition M Person International Ichiyoichi Episode 9 Co., Ltd. Agent

Claims (1)

[Claims] (II. A test pattern generation circuit, a comparison calculation circuit, and an error position detection circuit are added to a large-scale memory device to be tested, and the memory section of the memory device is divided into a plurality of blocks of the same size. , write the test pattern from the above test pattern generation circuit into all the divided blocks or multiple blocks that require backup testing, set one of these blocks as the entire reference block, set the others as the blocks to be tested, and write the test pattern as the reference block. The memory contents written in the block and the block to be inspected are sequentially read out in parallel according to the arrangement order of the memory units constituting each block, and the read signals are input to the above comparison circuit, so that the read signals match.・Compare up to the bit level of the memory unit that does not match, and if there is a memory unit that does not match, output the position information of the mismatch bit O in the memory unit, and detect the mismatch bit of the memory unit that does not match by the error position detection circuit. The error location in the block to be inspected is detected down to the bit position level of the memory unit based on the position information of the block and the memory unit address information output from the above memory device, and in the same way, all remaining blocks to be inspected are sequentially +inspected. A method for testing a large-scale memory device characterized by If an error is detected in the memory unit at the same address, it is determined that there is an error in the reference block, the reference block is replaced with another block to be inspected, and all other blocks to be inspected are newly inspected sequentially. A method for testing a large-scale memory device according to claim 1, characterized in that: