JPS5929036B2 - semiconductor communication path switch - Google Patents

semiconductor communication path switch

Info

Publication number
JPS5929036B2
JPS5929036B2 JP48072933A JP7293373A JPS5929036B2 JP S5929036 B2 JPS5929036 B2 JP S5929036B2 JP 48072933 A JP48072933 A JP 48072933A JP 7293373 A JP7293373 A JP 7293373A JP S5929036 B2 JPS5929036 B2 JP S5929036B2
Authority
JP
Japan
Prior art keywords
gate
circuit
switch
line
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP48072933A
Other languages
Japanese (ja)
Other versions
JPS5023511A (en
Inventor
充 川波
真治 奥原
卓司 迎町
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP48072933A priority Critical patent/JPS5929036B2/en
Priority to CA203,636A priority patent/CA1038068A/en
Priority to DE19742431164 priority patent/DE2431164C3/en
Publication of JPS5023511A publication Critical patent/JPS5023511A/ja
Priority to US05/707,352 priority patent/US4107472A/en
Publication of JPS5929036B2 publication Critical patent/JPS5929036B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/52Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements
    • H04Q3/521Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements using semiconductors in the switching stages
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/735Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は主に電話交換機等の通話路に用いられる通信路
スイッチ(一般には通話路スイッチあるいはチャネルス
イッチと呼ばれる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a communication path switch (generally referred to as a communication path switch or a channel switch) used mainly for a communication path in a telephone exchange or the like.

以下の説明は通話路スイッチとする。)の半導体化に関
するものである。〔発明の背景〕 交換機の通話路スイッチを半導体化しようとする試みは
従来よりあるが、その大部分はPNPNスイッチ(サイ
リスタ、SCR等と呼ばれる)を用いる方法である。
The following description will refer to a communication path switch. ) is related to semiconductorization. [Background of the Invention] There have been attempts to use semiconductor communication path switches in exchanges, but most of these have been methods using PNPN switches (called thyristors, SCRs, etc.).

PNPNスイッチは導通時のインピーダンスが比較的小
さく、且つ、遮断時には大きな絶縁抵抗が得られ、しか
も、小さなゲート信号で一旦ターンオンすると、外部で
電流を切断しない限り、導通状態を保ち続けるという自
己保持作用をもち、交換機の電子通話路化に有用な素子
である。しかし乍ら、電話交換機においては、電話機の
呼出信号(ベル信号)が高電圧の交流であるため、正負
いずれの方向にも電流を流さなければならず、また、ダ
イヤリング、フッキング等によつて、回路電流を断続す
ることが一般に行なわれており、この時も通話路スイツ
チは閉成し続ける必要がある。このため、この種の用途
にはPNPNスイツチの自己保持作用は充分に生かしき
れず、従来、ダイヤリング、呼出信号等は別に処理し、
PNPNスイツチでは直流電流に重畳した通話信号(小
信号)だけを取抜つている。〔発明の目的〕本発明はこ
のような欠点を改善したもので、複数の回路要素を組合
せることにより、ダイヤリング、フツキング、呼出信号
等を直接処理することの可能な半導体スイツチを提供す
ることを目的とする。
A PNPN switch has a relatively low impedance when conducting, and a large insulation resistance when cutting off. Moreover, once turned on by a small gate signal, it has a self-holding action that continues to conduct unless the current is cut off externally. It is a useful element for implementing electronic communication channels in switching equipment. However, in telephone exchanges, the ringing signal (bell signal) of the telephone is a high-voltage alternating current, so current must flow in both positive and negative directions. It is common practice to turn on and off the circuit current, and the communication path switch must remain closed at this time as well. For this reason, the self-maintaining effect of the PNPN switch cannot be fully utilized for this type of application, and conventionally, dialing, ringing signals, etc. are processed separately.
A PNPN switch extracts only the call signal (small signal) superimposed on the DC current. [Object of the Invention] The present invention improves these drawbacks and provides a semiconductor switch that can directly process dialing, hooking, calling signals, etc. by combining a plurality of circuit elements. With the goal.

〔発明の概要〕[Summary of the invention]

本発明は、通信路に接続された1対の主端子及びゲート
端子を有するゲート制御形双方向導通性半導体スイツチ
素子と、このスイツチ素子のゲート端子に接続された高
インピーダンスの0N,0FF制御可能な、逆流防止手
段を有する定電流回路よりなるゲート電流回路と、この
ゲート電流回路を0N,0FF状態に保つメモリ回路と
、このメモリ回路を制御する制御回路とから構成したこ
とを特徴とする。
The present invention provides a gate-controlled bidirectional conductive semiconductor switch device having a pair of main terminals and a gate terminal connected to a communication path, and a high impedance 0N, 0FF controllable device connected to the gate terminal of this switch device. The present invention is characterized in that it is composed of a gate current circuit consisting of a constant current circuit having a backflow prevention means, a memory circuit that maintains this gate current circuit in an ON/OFF state, and a control circuit that controls this memory circuit.

〔発明の実施例〕[Embodiments of the invention]

以下第1図ないし第3図を用いて本発明に係る半導体ス
イツチの一実施例を詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor switch according to the present invention will be described in detail below with reference to FIGS. 1 to 3.

第1図は本発明に係る半導体スイツチの第1の実施例で
、構成の基本単位を表わしたものである。ゲート制御形
双方向性PNPNスイツチ1は、主端子T1を通話路X
1に、主端子T2を通話路Yjに接続し、図示しない他
の双方向性PNPNスイツチと行列の格子に配置してあ
る。スイツチ1のゲート端子Gは逆流防止ダイオード2
を経て、交流的に高インピーダンスのゲート電流回路3
に接続されている。尚、ゲート電流回路3自身に逆電流
が流れない構成があれば、ダイオード2はなくてもよい
。ゲート電流回路3はメモリ4によつて制御され、メモ
リ4は交差点選択回路5によつてセツト・りセツトされ
るように構成する。この第1図図示の実施例においては
、メモリ4にはフリツプフロツプを用い、選択回路5は
選択路Xi,yj又はXi,yjの論理積によりメモリ
4をセツト・りセツトする方法が用いられている。そし
て、選択路Xi,yjに同時に信号が到来すると、メモ
リ4がセツトされ、これによつて、ゲート電流回路3か
らゲート電流が連続して流れ出し、スイツチ1がターン
オンする。選択路Xi,yjの論理積でメモリ4がりセ
ツトされれば、ゲート電流回路3はゲート電流の供給を
停止するか、スイツチ1に自己保持作用があるため、ス
イツチ1の遮断は外部で行なう必要がある。ただし、一
般には、通話が終了すると、電話機のフツクスイツチで
通話電流が切断されるため、特別の制御は必要としない
。これらの構成は一般に通話路の双方向2線路を平衡形
伝送路とし、MXn格子に組立てられる。このMXn格
子の実施例を第3図に示しており、詳細は第3図におい
て説明する。さて、第1図の構成の個々の要素につき、
更に説明を加える。
FIG. 1 shows a first embodiment of a semiconductor switch according to the present invention, and shows the basic unit of the structure. The gate-controlled bidirectional PNPN switch 1 connects the main terminal T1 to the communication path
1, the main terminal T2 is connected to the communication path Yj, and is arranged in a matrix grid with other bidirectional PNPN switches (not shown). Gate terminal G of switch 1 is reverse current prevention diode 2
After that, the AC high impedance gate current circuit 3
It is connected to the. Note that the diode 2 may be omitted if the gate current circuit 3 itself has a configuration in which no reverse current flows. The gate current circuit 3 is controlled by a memory 4, and the memory 4 is configured to be set and reset by an intersection selection circuit 5. In the embodiment shown in FIG. 1, a flip-flop is used for the memory 4, and the selection circuit 5 uses a method of setting and resetting the memory 4 by logical product of selection paths Xi, yj or Xi, yj. . Then, when signals arrive at the selection paths Xi and yj simultaneously, the memory 4 is set, whereby the gate current continuously flows from the gate current circuit 3 and the switch 1 is turned on. If the memory 4 is reset by the AND of the selection paths Xi and yj, the gate current circuit 3 will stop supplying gate current, or the switch 1 will have a self-holding function, so it is necessary to shut off the switch 1 externally. There is. However, in general, when a call ends, the call current is cut off by the telephone's switch, so no special control is required. These configurations generally use two bidirectional communication lines as balanced transmission lines and are assembled into an MXn lattice. An example of this MXn grating is shown in FIG. 3, and details will be explained in FIG. Now, regarding the individual elements of the configuration shown in Figure 1,
Add further explanation.

ゲート制御形双方向性PNPNスイツチとは、制御ゲー
ト端子をもち、正負いずれの方向にも電流を流せるPN
PNスイツチを意味し、たとえばトライアツクと呼ばれ
るスイツチが該当する。
A gate-controlled bidirectional PNPN switch is a PN switch that has a control gate terminal and allows current to flow in either the positive or negative direction.
This refers to a PN switch, such as a switch called a triack.

但し、後述の如く、一般のPNPNスイツチを逆並列に
接続したものも同様な機能が得られる。PNPNスイツ
チとした理由は、先きに述べたように、低い導通インピ
ーダンス、高い絶縁抵抗が得られる長所のほか、交流を
も取扱う本発明の回路に用いるとき、正負いずれの方向
にも高耐圧であることなど、トランジスタ他その他の素
子に勝る性能が得られるからであり、また、後述のよう
に、通話路の電位分布によつてはその自己保持作用も利
用できるからである。スイツチに自己保持作用を与えな
がら重複してメモリ4を設けた理由は、交流を通したり
、フツキング・ダイヤリング等で通話路電流が一時零と
なつて、スイツチ1がターンオフしても、再び通話路に
電圧が加われば、直ちに通話路に電流が流れるよう、常
時ゲート電流回路3を作動させておくためである。
However, as will be described later, a similar function can be obtained by connecting ordinary PNPN switches in antiparallel. The reason for choosing a PNPN switch is that, as mentioned earlier, in addition to the advantages of low conduction impedance and high insulation resistance, when used in the circuit of the present invention that also handles alternating current, it has a high withstand voltage in both positive and negative directions. This is because performance superior to transistors and other elements can be obtained, and, as will be described later, its self-holding effect can also be utilized depending on the potential distribution of the communication path. The reason why memory 4 is provided redundantly while providing a self-holding function to the switch is that even if the communication path current temporarily becomes zero due to passing AC or hooking dialing, etc., and switch 1 is turned off, the communication can be resumed. This is to keep the gate current circuit 3 in operation at all times so that current flows through the communication path immediately when voltage is applied to the communication path.

ゲート電流回路3を、高インピーダンスとした理由は、
スイツチと制御系の間の電位が変動しても一定したゲー
ト制御電流が供給できることから両者の電位差に関係な
く安定な制御が可能となり、更に消費電力も少くてすみ
、又通話中にはこの回路が生きているため、通話信号が
ゲート端子Gを通つて流失したり、他の回路に漏話した
りしないようにする目的であり、その電流値の大小又は
変動は、スイツチが感動するのに充分であれば、問題と
しない。
The reason why the gate current circuit 3 is made high impedance is as follows.
Since a constant gate control current can be supplied even if the potential between the switch and the control system fluctuates, stable control is possible regardless of the potential difference between the two, and power consumption is also low. The purpose is to prevent the call signal from flowing through the gate terminal G and from crosstalking to other circuits, and the magnitude or fluctuation of the current value is sufficient to impress the switch. If so, it's not a problem.

選択回路5はこの実施例に示すごとく、セツト・りセツ
トを別の選択回路で行なう方法とか後述の実施例のごと
く、他の交差点を選択するときに、自然にりセツトする
方法など、通話路スイツチの目的に合わせて適宣設計す
る。
As shown in this embodiment, the selection circuit 5 can be used to select a communication route, such as a method in which setting and resetting are performed using separate selection circuits, or a method in which resetting is performed naturally when selecting another intersection, as in the embodiment described later. Design appropriately according to the purpose of the switch.

ゲート電流回路3、メモリ4は各交差点対応に設けるが
、この選択回路5の一部は通話路スイツチ1台に共通に
設けるだけでも良い。商用交流回路では、双方向性PN
PNスイツチに交流に同期したパルス状のゲート電流を
加える方法が一般的である。
Although the gate current circuit 3 and the memory 4 are provided for each intersection, a part of the selection circuit 5 may be provided in common to one communication path switch. In commercial AC circuits, bidirectional PN
A common method is to apply a pulsed gate current synchronized with alternating current to a PN switch.

しかし、ベル信号、ダイヤリング、フツキング等は同期
が異るか又はいつ生ずるか予測できない情報であり、こ
れを連続的に監視してゲートパルス制御をする方法は制
御回路自体が複雑となり、効果的でない。メモリ4がセ
ツトされて、PNPNスイツチ1が導通した場合、電位
関係によつては端子Xi,yjの電位が共にゲート電流
回路3の供給可能限界電位より大きくなる場合がある。
However, bell signals, dialing, hooking, etc. are information that cannot be predicted whether or when synchronization will occur, and the method of continuously monitoring this and controlling gate pulses requires the control circuit itself to be complicated and is not effective. Not. When the memory 4 is set and the PNPN switch 1 is turned on, the potentials of the terminals Xi and yj may both become higher than the limit potential that the gate current circuit 3 can supply depending on the potential relationship.

(この状態は第1図の端子Xiに高い正の電源、端子Y
jに負荷抵抗を接続した場合を想定すればよい。)この
場合、端子Xi,yj間の導通状態はスイツチ1の自己
保持作用によつて保たれているだけで、ゲート電流回路
3は供給しようとしているにもかかわらず、実質的には
ゲート電流は零となり、むしろダイオード2がなければ
逆流することも考えられる。しかし、何らかの原因でP
NPNスイツチ1がターンオフすれば直ちにゲート電流
が流れ得る。従つて、本発明で連続的にゲート電流を流
すという意味は、実質的には流れないが流そうと作用し
ている状態をも含むものとする。第2図は、本発明に係
る半導体スイツチの第2の実施例で、その基本単位を表
わしたものであり、第1図の説明と同様に、通話路スイ
ツチの1交差点の一部を表わしている。
(In this state, a high positive power supply is applied to terminal Xi in Fig. 1, and terminal Y
It is sufficient to assume that a load resistance is connected to j. ) In this case, the conduction state between terminals Xi and yj is maintained only by the self-holding action of switch 1, and even though the gate current circuit 3 is trying to supply it, the gate current is actually It is conceivable that the current would be zero, and that if the diode 2 were not present, the current would flow backwards. However, for some reason P
As soon as the NPN switch 1 is turned off, the gate current can flow. Therefore, in the present invention, the meaning of continuously flowing a gate current includes a state in which the gate current does not substantially flow but is acting to flow. FIG. 2 shows a second embodiment of the semiconductor switch according to the present invention, and shows its basic unit, and similarly to the explanation of FIG. 1, it shows a part of one intersection of the communication path switch. There is.

第2図においては、通常のゲート制御形PNPNスイツ
チ11,12を逆並列に接続して、双方向性PNPNス
ィッチを得ている。そして、逆流防止ダイオード21,
22を各々のPNPNスイツチ11,12のゲート端子
に設けてある。ゲート電流回路3は第1図と同様である
が、第1図のメモリ4と選択回路5をセツト優先フリツ
プフロツプ回路6として一体にしている。このような構
成において、選択路Xi,xjに同時に信号が加わると
セツト状態になり、他の交差点を制御しようとして選択
路Yjに信号が加わると、りセツトされる。
In FIG. 2, ordinary gate-controlled PNPN switches 11 and 12 are connected in antiparallel to obtain a bidirectional PNPN switch. And a backflow prevention diode 21,
22 is provided at the gate terminal of each PNPN switch 11,12. The gate current circuit 3 is similar to that shown in FIG. 1, but the memory 4 and selection circuit 5 of FIG. 1 are integrated as a set priority flip-flop circuit 6. In such a configuration, when signals are applied to the selected roads Xi and xj at the same time, the set state is reached, and when a signal is applied to the selected road Yj to control another intersection, the selected road is reset.

この構成は選択路が増えないことであり、電子交換機の
半導体通話路スイツチには有効な手段である。これらが
格子に組立てられる。第3図は本発明の半導体スイツチ
を用いて通話路スイツチが平衡形2X2格子に構成され
た場合の概要を表わした図であり、図の煩雑さをさける
ため、交差点選択回路等を除いて示した。
This configuration does not increase the number of selection paths, and is an effective means for semiconductor communication path switches in electronic exchanges. These are assembled into a grid. FIG. 3 is a diagram showing an outline of a communication path switch configured in a balanced 2×2 grid using the semiconductor switch of the present invention. In order to avoid complication of the diagram, the intersection selection circuit etc. are not shown. Ta.

この図に例示するように、通話路スイツチは一般にm×
n格子として作られ、又、双方向2線路(A線,B線、
)を平衡形伝送路として作ることが多い。なお平衡形伝
送路とは、大地との間のインピーダンスが平衡している
回路で、2線路をアースから浮かせた形で信号を伝送す
る回路である。さて、第3図の実施例において、メモリ
Mは交差点に1個でよいが、A線とB線で電位が異なる
ために、ゲート電流回路はA線用、B線用と独立して設
けることが望ましい。
As illustrated in this figure, the call path switch is generally m×
It is made as an n-lattice, and has two bidirectional lines (A line, B line,
) is often constructed as a balanced transmission line. Note that a balanced transmission line is a circuit whose impedance to the ground is balanced, and is a circuit that transmits signals with two lines floating above the ground. Now, in the embodiment shown in FIG. 3, one memory M may be provided at the intersection, but since the potentials of the A line and B line are different, gate current circuits must be provided independently for the A line and the B line. is desirable.

なお、以上の説明ではPNPNスイツチがゲートに電流
を流し込むことによつてターンオンするものとして回路
図を表わして来たが、ゲートから電流を引き出してター
ンオンさせることが好都合の場合には、ゲート電流回路
、ダイオード等の向きを逆にすればよい。
In the above explanation, the circuit diagram has been shown assuming that the PNPN switch is turned on by flowing current into the gate, but if it is convenient to turn on by drawing current from the gate, the gate current circuit , the direction of the diode, etc. may be reversed.

また、これらの回路要素が全て一体の部品として組立て
られていなくても、布線などでで接続されて実質的に全
体が完成する場合も含まれることはいうまでもない。〔
発明の効果〕 以上詳しく説明したように、本発明に係る半導体スイツ
チは、交換機の通話路スイツチに用いれば、呼出信号、
ダイヤリング、フツキング等の処理を、従来の機械系通
話路スイツチと同様に取扱うことができ、交換機等の半
導体化に著しく寄与するものである。
Furthermore, it goes without saying that even if these circuit elements are not all assembled as an integral part, the circuit elements may be connected by wires or the like to substantially complete the whole. [
[Effects of the Invention] As explained above in detail, the semiconductor switch according to the present invention, when used as a call path switch of an exchange, can generate ringing signals,
Processing such as dialing and hooking can be handled in the same manner as a conventional mechanical communication path switch, and it will significantly contribute to the use of semiconductor switching equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る半導体スイツチの第1の実施例の
基本単位構成図、第2図は本発明の第2の実施例の基本
単位構成図、第3図は本発明に係る半導体スイツチを用
いて通話路スイツチを2X2の平衡形スイツチに構成し
た概要図を示す。 1・・・・・・ゲート制御形双方向性PNPNスイツチ
、2゜゜゜゜゜゜逆流防止ダイオード、3・・・・・・
ゲート電流回路、4・・・・・・メモリ、5・・・・・
・交差点選択回路、6・・・・・・交差点選択・メモリ
回路、11,12・・・・・・ゲート制御形PNPNス
イツチ、21,22・・・・・・逆流防止ダイオード。
FIG. 1 is a basic unit configuration diagram of a first embodiment of a semiconductor switch according to the present invention, FIG. 2 is a basic unit configuration diagram of a second embodiment of the present invention, and FIG. 3 is a basic unit configuration diagram of a semiconductor switch according to the present invention. A schematic diagram of a communication path switch configured as a 2×2 balanced type switch using the following is shown. 1...Gate-controlled bidirectional PNPN switch, 2゜゜゜゜゜゜゜backflow prevention diode, 3...
Gate current circuit, 4... Memory, 5...
- Intersection selection circuit, 6... Intersection selection/memory circuit, 11, 12... Gate control type PNPN switch, 21, 22... Backflow prevention diode.

Claims (1)

【特許請求の範囲】 1 通信路に接続された1対の主端子及びゲート端子を
有するゲート制御形双方向導通性半導体スイッチ素子と
、このスイッチ素子のゲート端子に接続された高インピ
ーダンスのON、OFF制御可能な、逆流防止手段を有
する定電流回路よりなるゲート電流回路と、このゲート
電流回路をON、OFF状態に保つメモリ回路と、この
メモリ回路を制御する制御回路とから構成されたことを
特徴とする半導体スイッチ。 2 通信路の双方向2線路(A線、B線)を平衡形伝送
路として縦列、横列格子に組立て、各格子交差点の縦列
A線と横列A線間、縦列B線と横列B線間に各1個づつ
ゲート端子を有するゲート制御形双方向導通性半導体ス
イッチ素子を配置し、この各スイッチ素子のゲート端子
に高インピーダンスON、OFF制御可能な、逆流防止
手段を有する定電流回路よりなるゲート電流回路を各1
個づつ接続し、この各格子交差点に配置された一対のス
イッチ素子に接続された2個のゲート電流回路に共通に
、このゲート電流回路をON、OFF状態に保つメモリ
回路を各1個づつ接続し、このメモリ回路をON、OF
F制御することにより、上記各格子交差点の通信路の開
閉を行なわしめることを特徴とする半導体スイッチ。
[Scope of Claims] 1. A gate-controlled bidirectional conductive semiconductor switching element having a pair of main terminals and a gate terminal connected to a communication path, a high impedance ON connected to the gate terminal of this switching element, It is composed of a gate current circuit consisting of a constant current circuit that can be turned off and has a backflow prevention means, a memory circuit that keeps this gate current circuit in an ON/OFF state, and a control circuit that controls this memory circuit. Characteristic semiconductor switch. 2. Assemble two bidirectional communication lines (A line and B line) into a column and row lattice as a balanced transmission line, and connect between the column A line and the horizontal line A, and between the column B line and the horizontal line B at each grid intersection. Gate-controlled bidirectional conductive semiconductor switching elements each having one gate terminal are arranged, and the gate terminal of each switching element is a constant current circuit that can perform high impedance ON/OFF control and has backflow prevention means. One current circuit each
One memory circuit is connected in common to each of the two gate current circuits connected to a pair of switch elements placed at each grid intersection, and one memory circuit is connected to each of the gate current circuits to keep the gate current circuits in the ON and OFF states. and turns this memory circuit ON and OFF.
A semiconductor switch characterized in that communication channels at each of the grid intersections are opened and closed by F control.
JP48072933A 1973-06-29 1973-06-29 semiconductor communication path switch Expired JPS5929036B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP48072933A JPS5929036B2 (en) 1973-06-29 1973-06-29 semiconductor communication path switch
CA203,636A CA1038068A (en) 1973-06-29 1974-06-28 Semiconductor channel switch
DE19742431164 DE2431164C3 (en) 1973-06-29 1974-06-28 Semiconductor way switch
US05/707,352 US4107472A (en) 1973-06-29 1976-07-21 Semiconductor channel switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP48072933A JPS5929036B2 (en) 1973-06-29 1973-06-29 semiconductor communication path switch

Publications (2)

Publication Number Publication Date
JPS5023511A JPS5023511A (en) 1975-03-13
JPS5929036B2 true JPS5929036B2 (en) 1984-07-17

Family

ID=13503647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48072933A Expired JPS5929036B2 (en) 1973-06-29 1973-06-29 semiconductor communication path switch

Country Status (3)

Country Link
JP (1) JPS5929036B2 (en)
CA (1) CA1038068A (en)
DE (1) DE2431164C3 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02110349U (en) * 1989-02-21 1990-09-04

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51144115U (en) * 1975-05-14 1976-11-19
ATE59520T1 (en) * 1985-09-23 1991-01-15 Siemens Ag BROADBAND SIGNAL SPACE COUPLER.

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4977566A (en) * 1972-11-28 1974-07-26

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1185907A (en) * 1957-11-08 1959-08-10 Cie Ind Des Telephones Connection point device, in particular for electronic switching
NL253766A (en) * 1959-07-13
DE1122568B (en) * 1959-09-15
US3543051A (en) * 1966-12-28 1970-11-24 Stromberg Carlson Corp Electrical switching arrangements including triggerable avalanche devices
DE1589681A1 (en) * 1967-03-07 1970-04-30 Philips Patentverwaltung Electronic crosspoint
FR1555813A (en) * 1967-12-12 1969-01-31
NL6908332A (en) * 1969-05-30 1970-12-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4977566A (en) * 1972-11-28 1974-07-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02110349U (en) * 1989-02-21 1990-09-04

Also Published As

Publication number Publication date
JPS5023511A (en) 1975-03-13
CA1038068A (en) 1978-09-05
DE2431164C3 (en) 1983-01-13
DE2431164A1 (en) 1975-01-23
DE2431164B2 (en) 1976-05-20

Similar Documents

Publication Publication Date Title
US3154695A (en) Gating control apparatus wherein static switches in the respective phase lines of a polyphase system are phase-sequence gated by a controlled gating signal
GB1564011A (en) Integrated circuits
US3883696A (en) Solid state crosspoint switch
JPS5929036B2 (en) semiconductor communication path switch
US3135874A (en) Control circuits for electronic switches
US4437096A (en) Concentrator circuit incorporating solid state bilateral bridge arrangement
US4107472A (en) Semiconductor channel switch
US4057691A (en) Switching network with crosstalk elimination capability
US4821315A (en) Electronic contacts and associated devices
US4060699A (en) Line connection reversing circuits
US3694812A (en) Switching circuit having a controllable semiconductor switching element and a switching matrix employing the switching circuit
US3601547A (en) Cross-point switching arrangements including triggerable avalanche devices
US4082923A (en) Semiconductor speech path switch
USRE27680E (en) Polarity sensitive voltage inserttion circuit for long subscriber loops
US3621147A (en) Electronically controlled crossbar switch
USRE26313E (en) Matrix switch utilizing magnetic structures as crosspoints
US3483516A (en) Controls for a glass crosspoint arrangement
US3086083A (en) Switching circuit
US3626208A (en) Double-pole double-throw diode switch
US3499116A (en) Circuit arrangements for remotely controlled dictating installations having multiple subscriber and dictating machine stations to prevent engagement of a previously engaged dictating machine station
US3417292A (en) Transistorized electronic relay
US3956590A (en) Switching arrangement for switching between different current values by means of mechanical or electronic switches
US3920906A (en) Wired broadcasting systems
GB1602304A (en) Bipolar switching networks
US3111558A (en) Relay circuit