JPS5927932B2 - Key input method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key input method for inputting only specific key inputs according to a predetermined priority order for simultaneous operation of a plurality of keys.

In general, in small electronic calculators such as desktop and palm-top calculators, cash registers, typewriters, etc., various keys such as a large number keys and function keys are placed close to each other. A plurality of keys may be operated at the same time, and in order to prevent this inconvenience, various so-called multi-key prevention means have been devised.

These conventional methods for preventing multiple presses include means for locking keys when multiple presses are made and prohibiting subsequent key inputs, and means for inputting key input information for one of the keys pressed at the same time. However, if the above-mentioned key lock is used to prohibit further key input, an inexperienced operator may mistakenly think that there is a malfunction, and the key lock must be released each time. In addition, in the case of using a method of manually inputting information from one of the keys, it is necessary to check each time the operator presses a key to see if the desired input information has been input. However, there were problems such as an extremely burdensome key operation for the operator and a lack of reliability. The present invention has been made in view of the above circumstances, and provides key operation signals output from a plurality of output lines of a matrix-like keyboard having a plurality of keys arranged on each intersection of a plurality of input/output lines. are weighted for each output line, and a priority is set in advance between each output line, so that when multiple keys belonging to the same human power line are operated simultaneously, only one key is assigned a weight according to the above priority. It is an object of the present invention to provide a key input method that allows only key input and improves the reliability of key operation. An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, reference numeral 11 denotes a key input section, which generates key input data coded into numerical information by key operation.

That is, this key input section 11 includes a keyboard 12, a buffer register 13, and a parallel/serial conversion circuit 1, as shown in FIG.
Consists of 4. The keyboard 12 includes, for example, 20 key switch mechanisms arranged in a matrix of 5 rows (Lo-L0) x 4 columns (P1 to P4) as shown in the figure, and a timing pulse line L in each row. -L4 is a key input timing pulse X having different phase timing for row sampling from a decoder 15, which will be described later. -X4 are sequentially supplied and the keys are scanned. Therefore, when a key is operated on the keyboard 12, the key input timing pulse of the row to which the operated key belongs is derived as a key operation signal from the key operation signal line of the column to which the key belongs. Key operation signal lines P1 to P of each column of this keyboard 12
4 is led as a parallel input of the buffer register 13 having a 4-bit capacity corresponding to this number of columns. Number keys O to 4 are arranged in the P4 column of the keyboard 12, and P
Number keys 5 to 9 are arranged in the 3rd column, and various calculation command keys etc. are arranged in the P2 column and the P, column. The parallel data output from the buffer register 13 is then transferred to a parallel-to-serial conversion circuit 14.
The data is encoded into 4-bit numerical information, which is further converted into serial data and output.

Locks t1 to T4 are necessary for encoding this numerical information.
are sequentially supplied from a timing counter (not shown in FIG. 2), and one cycle of the clocks T, -T4 is provided in synchronization with each of the key input timing pulses. That is, if a key belonging to P1 of each column P1 to P4 of the keyboard 12 is operated, the output of the parallel-to-serial conversion circuit 14 becomes 2".
1000] (decimal 1), and in P2 it becomes “010
0" (decimal 2), P3 outputs "0010" (decimal 4), and P4 outputs "0001j (decimal 8).

Therefore, the number of data output from the key input section 11 is 1.
When only one key is operated, data representing numeric information 1, 2, 4, or 8 given to the column to which this key belongs is output, but if two or more keys on the same row are operated by mistake, When these keys are operated at the same time, the numerical information obtained by adding the three numerical information given to the column to which each key belongs is output. For example, when the keys in columns P3 and P4 are operated at the same time, the information ``001U (12 in decimal)'' is output, and when the keys in columns P2 and P3 are operated simultaneously, the information ``011U'' is output.
0” (decimal number 6) is outputted, P2,
When the keys in the P3 and P4 rows are operated at the same time, “011
1" (decimal number 14) is output. The output data of the key input section 11 is input to the gate circuit 17 of the calculation section 16.

This calculation section 16 is constructed as shown in the figure: gate circuit 17 → adder circuit 18 → gate circuit 19 → X register 20 → loop of gate circuit 17 and gate circuit 17 → adder circuit 18 →
It has a loop of gate circuit 21 → Y register 22 → gate circuit 17, and the gate circuits 17, 19, 21 are connected to the control unit 24.
By controlling the opening and closing at predetermined timings from the key input section 11, digits and various calculation commands can be input based on the numerical information of the coded key common signal from the key input section 11. Further, the gate circuit 17 receives a code signal “1” from a code generator (not shown) of the control unit 24.
is input according to a predetermined command and timing. The carrier output and output data of the adder circuit 18 are led to a judgment circuit 23.

This judgment circuit 23 judges the magnitude of numerical information of input data. A command for this judgment operation is given from the arithmetic control unit 24, for example, a read-only memory (ROM). This judgment operation is performed by adding the relevant numerical value in the register and the numerical value generated by the code generation section of the control section 24 to the gate circuit 17, and adding the value to the adder circuit 17 to which the control section 24 has given a subtraction instruction.
8, the above two numbers are subtracted, and the result is sent to the judgment circuit 2.
3, and the magnitude of the above two numerical values is determined. The judgment output of the judgment circuit 23 is led to an address control section 25 for specifying the address of the control section 24.

Further, the control unit 24 has built-in programs for various calculations, and also has a built-in program for determining the priority order of key inputs according to a flowchart as described later. Generates control signals.

In this embodiment, the priority of key input is set to P on the keyboard 12.
The 4th column is given top priority, and the following columns are set in the order of P3 column, P2 column, P, column. By the way, the X register 20 has a digit Xc where timing data is stored, a digit XB where output data of the key input section 11 is input, and a digit XF where numeric flag data is stored. Data is stored.

Then, the output data of the X register 20 is led to a gate circuit 26, and this gate circuit 26 receives the
It is opened at the timing of output from the register 20. The output data of this gate circuit 26 is guided to the decoder 15 and decoded to generate the timing pulses XO-X4. That is, when Xc=O, the timing pulse
. Similarly, Xc21, Xc=2, Xc=3, Xc
= 4, the timing pulses Xl, X2, X3,
Generate X4. Next, the circuit operation of one embodiment of the present invention will be described with reference to the circuit configuration diagrams of FIGS. 1 and 2 and the flowcharts shown in FIGS. 3 to 5. As shown in the flowchart of FIG. 3, first, the XO digit of the X register 20 is
0'', that is, cleared.

The value "O" in the Xc digit is the timing signal X shown in FIG. 2 via the gate circuit 26 and decoder 15. occurs. Next, the contents of the buffer register 13 are encoded into numerical information by a parallel-to-serial conversion circuit 14 and input as serial data to the XB digit of the X register 20 via a gate circuit 17, an adder circuit 18, and a gate circuit 19. Next, a judgment command as to whether or not the XB digit is "O" is output from the control unit 24 to the judgment circuit 23, and as a result, the numerical information of the XB digit is input to the judgment circuit 23 via the gate circuit 17 and the adder circuit 18. The presence or absence of numerical information is determined, and the determination output of the determination circuit 23 is sent to the control unit 24.
The command is input to the address control unit 25 for instructing the next command. If no key is operated on the keyboard 12, the XB digit is "0" as described above, and the judgment circuit 2
3, the address control unit 25 instructs the next instruction, that is, the instruction to count up the XO digit of the X register 20 by 1. Therefore, a code signal “1” is input from the Xc digit of the X again
X in register 20. input into the digit. At this time, the value in the XO digit becomes "1", and a timing signal X1 shown in FIG. Judgment circuit 23
The numerical value of the Xc digit is passed through the gate circuit 17 and the adder circuit 18, and the judgment circuit makes the above judgment, and then inputted again to the Xc digit of the X register 20 via the gate circuit 19. The judgment output of the above judgment result is given to the address control unit 25, and if the value of the XO digit is smaller than "4", the contents of the buffer register 13 are encoded into numerical information as described above and input into the digit.

If the value of the XO digit is [4], then the Xc digit is set to ``0''.
” and repeat the above operation. Here, if the numeric key 3 in the P4 column and the operation key ÷ in the P2 column of the keyboard 12 are operated at the same time, the key common signal in the P4 column and P2 column at this time is when the timing signal X3 is input, that is, the value of the Xc digit. is input to the buffer register 13 when it is "3".

The parallel-to-serial conversion circuit 14 receives the contents of the buffer register 13 and encodes it into numerical information using timing signals Tl, t2, t3, and t4, and converts it into numerical information [0101'' (10
This information is output in series as a base 10), and this information is input to the XB digit of the X register 20 via the gate circuit 17, adder circuit 18, and gate circuit 19. Next, the XB digit is “0”
The determination as to whether or not the A judgment command as to whether or not is 8 or more is issued.
Therefore, the numerical information of the XB digit of the X register 20 is "10".
is input to the gate circuit 17, and a numerical code "8" is input to the gate circuit 17 from the code generating section of the control section 24. On the other hand, at this time, the adder circuit 18 is given a subtraction command from the control section 24. Therefore, the adder circuit 18 subtracts the numerical information "10" of the XB digit and the numerical code "8", and as a result "2" is inputted to the XF digit via the gate circuit 19. At this time, the output of the adder circuit 18 is also input to the control circuit, and a judgment result is output based on the subtraction result (depending on whether the subtraction result is positive, zero, or negative), and the next command of the control section 24 is executed. be instructed. Now, the subtraction result is “2”
(Correct), that is, it is determined that
4 is indicated. In the numeric flow 1, as shown in FIG. 4, it is first determined whether there is numeric flag data, such as "1", in the XF digit of the X register 20, and if there is numeric flag data, the Y register 22 is Carry up by one digit, and if there is none, input the numeric flag data to the XF digit. That is,
If the input number is the first value, the Y register 22 is not carried forward, but is carried every time the next value is input.
For example, when entering "250", "2", "5", "0"
", but the Y register 22 is not carried up with the first number "2", but is carried up each time the next number "5" and "0" are input. After the above operations have been performed, as shown in numeric flow 1, Xc of the X register 20 is
The digit number “3” is the first digit Y of the Y register 22. is input. As described above, even though the numeric key 3 and the arithmetic key ÷ are operated at the same time, only the key whose priority is determined in advance, in the above example, the numeric key 3 is input. Furthermore, although the above example shows a case where the keys in the P4 column and the P2 column of the keyboard 12 are operated at the same time, there is also a case where one or more keys including the keys in the P4 column are operated singly or simultaneously. The operation of numeric flow 1 is performed in the same manner as above. Next, a case will be described in which the numeric key 6 in the P3 column of the keyboard 12 and the calculation key + in the P2 column are operated at the same time.

At this time, the key common signals of columns P3 and P2 are input to the buffer register 13 when the timing signal X is input, that is, when the value of the Xc digit is "1". Parallel-to-serial conversion circuit 1
4 receives the contents of the buffer register 13 and stores the numerical information "
0110'' (decimal 6), output in series, and input to the XB digit of the X register 20 in the same manner as described above. Next, it is determined whether the XB digit is "0" or not,
In this case, since it is "6", the next judgment is XB/8. Here, the judgment of XB(=6)×8 is made and the process moves to the next judgment, which is XB/3. Here, the judgment that XB(=6)>3 is made and the flow moves to number flow 2. Note that the above judgment operation is performed through the same operations as described above. In the numeric flow 2, as shown in FIG. 5, after the Y register 22 is carried or the numeric flag data is input, the
5 is added to the digit value "1". That is, the numerical value "1" of the XO digit and the numerical code "5" generated from the code generating section of the control section 24 are sent to the adder circuit 18 via the gate circuit 17.
The addition result "6" is input to the Xc digit via the gate circuit 19. Next, the value of this Xc digit is “6”
is input to the first digit Y4 of the Y register 22. As described above, even though the numeric key 6 and the arithmetic key + are operated at the same time, only the numeric key 6 in the above sequence, which is a key whose priority is determined in advance, is input.

Further, in the above example, the keys in the P4 column and the P2 column of the keyboard 12 are operated simultaneously, but in addition to the P4 column, one or more keys including the keys in the P3 column may be operated alone or Even when they are operated at the same time, the operation of number setting flow 2 is performed in the same manner as described above. Also, the XB=
In the judgment step of 3, XB>3, XB<3, XB=
3, that is, when keys in the P column and keys in the P2 column are operated at the same time, the flow shifts to the calculation flow for performing calculation control corresponding to the fantasy key assigned to the P2 column.

That is, in this case, it is assumed that only the keys in the P2 column have been operated and are handled preferentially. Also, in the above judgment step,
When B is 3, it is further determined whether or not XB=2.

Then, when it is determined that XB=2, that is, only the keys in column P2 are being operated, the process moves to the calculation flow described above. On the other hand, X
8\"2", that is, when it is determined that only the keys in the P1 column are being operated, the process moves to a calculation flow for performing calculation control corresponding to the function key assigned to the P1 column. According to the key input method as described above, the keyboard 12
gives numerical information of a predetermined weight to each column output (key common signal) of the keys arranged in a matrix, that is, encodes the key common signal, and
Move it to register 20.

Then, the control unit 24 controls the judgment circuit 23 to judge the magnitude of the numerical information of the key input data,
In addition, if the numerical information is the sum of a plurality of key common signals, the control section 24 controls the calculation section 16 so that it is treated as one key common signal according to a predetermined priority order. Therefore, even if keys in a plurality of columns are being operated at the same time, it can be handled as if keys in one column are being operated preferentially. In this case, it is safer to prioritize the keys in multiple rows to keys that are less affected by incorrect keystrokes; for example, input data from numeric keys should be given priority over data input from function keys. For example, since this can be confirmed on the display, it becomes clear which keys have been input when keys are pressed simultaneously. Incidentally, in the embodiment of the present invention, priority is given to the input of the number keys when keys are pressed simultaneously, but the priority order is not limited to the embodiment and can be set as appropriate.

Further, the key layout can be appropriately set so that, for example, keys having different key common signals are adjacent to each other. Furthermore, in the above embodiment, there are four key operation output lines.
Although the case where the book is a book has been described, the book is not limited to this, and any number of books may be used as long as it can be encoded into numerical information.

Other circuit configurations can also be modified in various ways without departing from the gist of the present invention. As described above, the present invention
Key operation signals output from multiple output lines of a matrix-like keyboard having multiple keys arranged on each intersection of multiple input/output lines are weighted for each output line, and the key operation signals are weighted for each output line. By setting priorities in advance, even if multiple keys belonging to the same human power line are operated simultaneously, only one key can be input according to the predetermined priority order, improving the reliability of key operation. It is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the key input section of FIG. 1 in detail, and FIGS. 3 to 5 are diagrams showing the operation of FIG. 1. This is a flowchart shown to explain. 11...Key input section, 12...Keyboard, 13...Buffer register, 14...
. . . Parallel-serial conversion circuit, 16 . . . Arithmetic unit, 23
. . . Judgment circuit, 24 . . . Control unit.

Claims (1)

[Claims] 1. A matrix-like keyboard having a plurality of keys arranged on each intersection of a plurality of input/output lines, and a key scanning device for supplying timing pulses with different phases to the plurality of input lines of the keyboard to scan keys. means, encoding means for weighting key operation signals outputted from the plurality of output lines for each output line when a key is operated and encoding them into binary numerical information; An input for inputting information of a key belonging to an output line of a predetermined priority among the plurality of operated keys based on binary numerical information outputted from the encoding means when operated. A key input method characterized by comprising a control means.