JPS592471A - Base band transmission system - Google Patents

Abstract

PURPOSE:To attain high speed re-locking of a PLL circuit of a device A, by transmitting a lock state of the PLL circuit of the device A to a device B in R- bit and transmitting a signal of a prescribed period from the device B when an R-bit represents out of lock. CONSTITUTION:A transmission signal consists of a timing detecting bit F, a transmission timing ST, a transmission data SD and a remote bit R, an F-bit repeats sequentially (1), (0) at each frame and when the R-bit has the same logic as that of the F-bit, it represents the locking of the PLL circuit of the own station, and when the logic is always zero, it represents out of lock. The device A transmits the transmission signal to the device B, and when the PLL circuit is unlocked at the demodulation section 52 of the device A, the R-bit is zero and in other cases, a signal having a logic equal to that of the F-bit is transmitted to request the transmission of a signal of re-lock of the PLL circuit to the device B. The modulation section 63 of the device B transmits a signal where all bits of one frame are equal to the logic of the F-bit to the device A, the PLL circuit of the demodulation section 52 of the device A is re-locked and the logic of each signal is returned to (1).

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a baseband transmission system, and particularly to a case where a PLL circuit is used to extract a modulation timing clock from a digital signal and reproduce transmission data and transmission timing. The present invention relates to a baseband transmission method that enables high-speed automatic locking of a PLL circuit.

(2) Background of the technology Baseband transmission transmits a digital signal, such as an NRZ signal, as it is without any modulation, and on the receiving side extracts a timing clock from the received signal using a PLL circuit etc. It performs demodulation. Therefore, if the PLL circuit becomes unlocked, the timing clock cannot be extracted and it becomes impossible to properly demodulate the signal. Therefore, if the PLL circuit becomes unlocked, it is necessary to quickly relock it. It is said that

(3) Prior art and problems The inventors of the present invention have previously developed a system as shown in FIG. 2 in order to realize baseband transmission of serial digital data at high speed and with a simple circuit configuration, as shown in FIG. We have proposed a baseband demodulation method that extracts the demodulation timing using a PLL circuit 20 such as a phase comparator 1, a low-pass filter 2, and a voltage-controlled oscillator 3 as shown (Japanese Patent Application No. 1986-
13022 and 57-13023). In this demodulation method, a voltage controlled oscillator (hereinafter simply referred to as VCO) 3
The output pulse is divided into 91/N by the counter 4 (N is an integer), and the rising edge or falling edge of this frequency-divided pulse is less than or equal to twice the minimum width or pulse width of the transmitted pulse. Create an r-)-phantom reply with a pulse width, input this dart pulse to the AND/DART 9, and apply a dart to the transmitted signal.

This ant 9 gate 9 output rough needs comparator 1
a baseband demodulation circuit configured to input the f-) pulse to one of the input terminals of the phase comparator 1, and to delay the f-) pulse by an amount equal to or less than the minimum pulse time width of the transmission signal to the delay circuit 8, and input the pulse to the other input of the phase comparator 1; using the configuration.

In this case, as shown in Figure 3, the structure of the transmission signal is a serial frame structure of n bits wrapped in a frame detection bit (F) and a frame end bit (g), and the frame detection bit That is, the F♂ bit sequentially repeats logic ``'1'' and °゛0'' in units of one frame, and the frame end bit, that is, n bit, always becomes logic ``0'' when the F bit is logical MO#. In addition, in this method, the transmission black.

Since the PLL circuit 20 locks directly to the frame rather than to the frame, the frame detection and frame synchronization circuits required in conventional LC resonant circuits are no longer necessary, and miniaturization is possible. Furthermore, by inputting a lock signal to the multiplexer 16 until the PLL circuit 20 locks,
A signal that bypasses the AND date 9 and makes all bits of one frame the same as the logic of the F bit as shown in FIG. 4(,), or a signal as shown in FIG. 4(b)
High-speed locking of the PLL circuit is possible by receiving a signal in which all bits other than the bit are set to logic "0".

However, with this configuration, when the PLL circuit loses its lock, information to the effect that the lock has been lost is transmitted to the transmitting side due to high-speed locking, and a fixed period signal consisting of frame bits is transmitted from the data transmission. Switching to transmission was difficult.

Therefore, there are disadvantages in that it takes a long time to relock the PLL circuit, or it is necessary to forcefully reset all the circuits manually.

(4) Purpose of the Invention The purpose of the present invention is to:
In a baseband transmission method in a data transmission line using a plurality of sending devices A, B, etc. using a baseband demodulation method, a signal indicating that the PLL circuit of device A is unlocked is transmitted to device B, and device B The purpose is to enable high-speed relocking of the PLL circuit of device A based on the concept of transmitting a signal for locking the PLL circuit from the device A.

(5) Structure of the Invention The base-domain demodulation method proposed earlier automatically switches the transmission signal from data transmission to a fixed-period signal made up of frame bits when the PLL circuit is unlocked. Since there is no means to change the PLL circuit, there is a drawback that it takes time for the PLL circuit to lock again.

The present invention transmits the state of the PLL circuit of device A to device B using R bits through a data transmission line, so that device B selects the transmission signal, and if R bits indicate an out-of-lock state. At times, device B sends a signal at a constant period to cause devices Aa and ptL circuits to relock at high speed.

(6) Examples of the invention The present invention will be explained in detail below with reference to the drawings.

FIG. 5 shows an example of a frame structure of a transmission signal used in a system according to an embodiment of the present invention. One frame consists of 4 bits, the 1st bit is the frame bit for timing detection (F), and the 2nd bit is the transmission timing (ST).
, the third bit is the transmission data (SD), and the fourth bit is the remote bit (R). The F bit sequentially repeats the logic ``1'' and 0# every frame.The R♂ shift logic is
When the bit is the same, it indicates that the PLL circuit of the own station is locked,
If the logic is always 0#, it indicates that it is not locked.

For high-speed synchronization of other station PLL circuits? As shown in Figure 6, as an example, until the PLL circuit of the local station is locked, the R pit is set to 0'' and a constant cycle pulse with a duty ratio of 37.5% is transmitted, and the PLL circuit of the local station is locked. After that, the R pit is set to '1' and a constant period/4' pulse with a 7' knee ratio of 50 chi is transmitted. In the embodiment, each bit is 31.25 nls and the i-frame is 125 nm.

FIG. 7 shows the configuration of a baseband demodulator used in a system according to an embodiment of the present invention. The baseband demodulator in the figure includes an optical-to-electrical conversion module 22 connected to an optical fiber cable 21, a PLL circuit 23, and a shift register 2.
4, D type free lug frog 2f, 32, 33.36
．． 37 and exclusive orderer F34.38.

In the configuration shown in FIG. 7, the digital transmission signal sent from the optical fiber cable 21 is converted into an electrical signal by the optical-to-electrical conversion module 22, and is input to the PLIJ1 path 23 and the upper 23 foot register 24. In synchronization with this signal, the PLL circuit 23 outputs a clock signal 25 (for example, 32
) and a halt value of 9 pulses 26 (for example, 8■h) are output. The shift register 24 shifts the input signal using a black signal 25. D type 7 to reproduce the signal
The reset flag 27 temporarily stores (latches) this shifted signal in a hold/receiver 26. For this,
Transmission data (SD) 28, transmission timing (ST) 29
, remote signal (R) 30. A frame signal (F) 31 is obtained. Note that the remote signal 30 and frame signal 31 respectively include remote bit R and frame bit F.
The pulse width is 1 frame (125ni)'
t'6ru. To obtain the ready signal, the remote signal 30 is latched in the D-Tino flipflop f32. The output is input to a D-type free lag frog 33 and an exclusion ore (e-) 34. The exclusive-jib-or-dirt 34 performs an exclusive OR of the outputs of the D-type flip-frogs 32 and 33, and when the remote signal 30 sequentially repeats the logic "1" l, @0#, the logic "1" is output.
A signal (RDY) 35 is output. At this time,
The PLL circuit of the other station is locked. When the logic of the remote signal is other than the above, the logic of the RDY signal 35 is 0''.Similarly, the D-tie 767 rig 70g 36.
37 and exclusive-or-dirt 38, when the frame signal 31 sequentially repeats the logic "l #, n Q #", the logic of the received carrier detection signal (CD) 39 is set to "1", and when the logic of the frame signal is other than the above, , CD
The logic of signal 39 is set to par 0#.

When the logic of the CD signal 39 is 1#, the PLL circuit of the local station is locked.

FIG. 8 shows the configuration of a pace and frequency modulator used in a system according to an embodiment of the present invention. The baseband modulator in the figure includes a crystal oscillator 40 that oscillates a reference signal (for example, 32 MHz), a counter 41, a multi-breather 45,
Electrical-optical conversion module 5 connected to AND dart 47, shift register 50, and optical fiber cable 21
1.

In the configuration of FIG. 8, the counter 41 is a crystal oscillator 40.
Frame signal (F) 42 (for example, 4MFIz bass sampling) for creating a transmission signal by dividing the reference signal from
A clock signal 44 (eg, 32 MHz) is generated. Multibrefusa (MPX)
45 is supposed to be the transmission timing (ST) when the logic of the set signal (SET) 46 is "1".

The transmission data (8D) is selected, and the frame signal 42 is selected at logic "0". The AND dart 47 generates a remote signal (fE) 49 with the same logic as the frame signal when the remote transmission request (RT) 48 is at logic "1#", and generates a remote signal (fE) 49 with the same logic as the frame signal.
”, the logic of the remote signal 49 is set to 0. A shift register (SR) 50 samples four signals ST, SD, R, and F using a sampling pulse 43 and sequentially outputs the sampled signals to an electro-technical conversion module 51 according to a clock signal 44 to generate a transmission signal. . Electrical-optical conversion module 51
converts this into an optical signal and transmits it through the optical fiber 21.

FIG. 9 shows a high speed automatic locking mechanism implementing the scheme according to one embodiment of the present invention. In the figure, device A
and B are data transmission modulators having the same configurations as those in FIGS. 8 and 7, respectively, and 64.65 is an and dart.

In FIG. 9, it is assumed that the PLL circuit is unlocked in the demodulator 52 of the intervening device (fA).At this time, the CD signal 53, RT
The logic of the signal 54, RDY signal 55, and SET signal 56 is 0.
#, and the modulation section 57 becomes Rpi.

It sends a signal whose bit is logic "'0" and which is otherwise equal to the logic of the F bit, requesting device B to send a signal for relocking the PLL circuit. Demodulator 580PLL of device B
Since the circuit is in a locked state, the logic of the CD signal 59 and RT signal 60 is 1#.

Further, the R bit sent from the modulation section 57 is a logic °IO#
Therefore, the logic of the RDY signal 61 and the SET signal 62 is "O", and the modulator 63 of device B transmits to device A a signal in which all bits of one frame are equal to the logic of F bits. This signal relocks the PLL circuit of the demodulator 52 of device A, and the logic of the CD signal 53 and RT signal 54 becomes 1".
Return to At this time, R of the transmission signal sent from the modulation section 63
The bit logic is the same as the F bit logic, and the demodulator 5
This indicates that the PLL circuit of 8 is locked, and as a result, the logic of the RDY signal 55 returns to 1''.Then, the logic of the SET signal 56 also becomes 1'', and the modulation section 57
The R bit, which has the same logic as the bit, and the transmission timing (S
T), return to transmission of transmission date/(SD). Therefore, the RDY signal 61 obtained by the demodulator 58 becomes logic "1#", and the logic of the SET signal 62 also returns to "1". As a result, the modulation section 63 also transmits the transmission timing (ST) and the transmission data (SD).
), the demodulator 520 PLL circuit relock and line recovery are completed.

FIG. 10 shows a time chart when the PLL circuit of the demodulator 52 relocks. Before time T1, both devices iA and B operate normally and the PLL circuits are locked. Now, assume that the PLL circuit of device A becomes unlocked at time T1. At this time, the CD signal, RDY signal, and RT double signal SET signal of device A all become logic "0".

This state reaches device B after a transmission delay TDI,
At time T2, device B sets the logic of the RDY signal and SET signal to 0.
# and starts transmitting a signal to lock the PLL circuit.

At time T3, the PLL circuit of device A relocks, and the logic of the CD signal, RDY signal, and RT double signal SgT signal is returned to 1''.After transmission delay TD2, device B detects the return of device A at time T4. The logic of RDY signal and SET signal is
Set to 1# and return to data transmission. This completes line recovery.

In addition, in the above description, regarding devices A and B that perform r-transmission, an example was explained in which the PLI and circuit of device A are relocked at high speed when the lock is released, but this transmission method is as follows. Needless to say, this is similarly effective for relocking the PLLs of both devices A and B when they are unlocked, and for connecting the transmission line when power is turned on for device A6 or device B.

(7) Effects of the Invention According to the present invention, in a baseband transmission system, when the gate of the PLL circuit on the receiving side is disconnected, the transmission signal from the transmitting side changes from data transmission to a constant period consisting of frames. The PL
High-speed automatic locking of the L circuit is possible.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing an example of a baseband modulated transmission signal, FIG. 2 is a waveform diagram showing the configuration of a transmission signal used in a conventional demodulator's multi-path spant demodulator, and FIG. A waveform diagram showing an example of a transmission signal that is transmitted until the PLL circuit locks in a conventional demodulator, FIG. 5 is a waveform diagram showing an example of a transmission signal used in the embodiment of the present invention, and FIG. A waveform diagram showing an example of a transmission signal for a PLL circuit used in an embodiment of the present invention, FIG. 7 is a block circuit diagram showing a demodulation circuit used in a method according to an embodiment of the present invention, FIG. 8 is a block circuit diagram showing a modulation circuit used in a method according to an embodiment of the present invention, FIG. 9 is an explanatory diagram of a high-speed automatic locking mechanism in a method according to an embodiment of the present invention, and FIG. 9 is a time chart for explaining the operation of the mechanism shown in FIG. 9. FIG. ■... Phase converter or rater, 2... Ronos filter, 3... Voltage controlled oscillator, 4.10... Counter, 5.8.11... Delay circuit, 6... Inverter, 7゜9... Antodart, 12... Optical fiber cable, 13... Optical-electrical conversion module, 14.
...Shift register, 15...D type flip f70
Horn, 16... Multiplexer, 20... PLL circuit, 21... Optical fiber 9 cable, 22... Optical -
Electrical conversion module, 23... PLL circuit, 24...
・Shift register, 27° 32.33, 36.37...
・D type flip 70zz, 34.38...exclusive or dart, 40...crystal oscillator, 41.
...Counter, 45...Multiplexer, 50...
Shift register, 51... electrical-optical conversion module,
64.65...and dirt. Patent applicant Fujitsu Ltd. Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akira Yamaguchi Figure 1 Figure 10 Modulation and demodulation device A Modulation and demodulation device ■ 3

Claims (1)

[Claims] 1. An output pulse from a voltage controlled oscillator is frequency-divided using a PLL circuit equipped with a phase comparator, a low-pass filter, and a voltage-controlled oscillator, and the rising edge or falling edge of this frequency-divided pulse is Create a pulse (f-)/# with a pulse width less than twice the minimum pulse width of the transmitted pulse, multiply the transmitted signal by f-) by this r-) pulse,
This output is input to one side of the phase comparator, and the demodulation timing is extracted by delaying the r-to pulse by an amount less than the time width of the minimum pulse of the transmission signal and inputting it to one side of the phase comparator. In the baseband transmission method, the transmission signal is configured as a serial frame consisting of n bits of data wrapped in a frame detection beep (F) and a frame end beep (R), and the first P bit is one frame. Sequentially logic "'1#" for each program unit. "O# is repeated, and the F bit is logic for the last n bits."
When it is 0#, the logic is always "O", and until the PLL circuit is in the lock state, all pits other than the n bit of one frame are set to the same logic as the F bit, and the F bit is logic "1".
A paced transmission system characterized by setting the logic of n bits to MO# or 1# when . 2. When the PLL circuit operates and the demodulated F bit sequentially repeats the logic ``1'' and 0# for each frame, the received carrier detection signal (CD
), and when the F bit is not set, the logic of the CD signal is inverted, and when the PLL circuit is locked,
The demodulated n bits are sequentially converted into logic II l #, @Q
Claim 1 uses a demodulator which outputs a ready signal (RDY) of logic "1" or "0" when repeating II, and inverts the logic of the RDY signal when n bits are not in that state. The baseband transmission method described in 3.3.1 frame has all bits other than the n bit set to the same logic as the F bit, and all bits other than the F bit of the 17th frame are set to logic "o" or 1. A baseband transmission method according to claim 1 using a transmitter having a function of switching between a transmission signal and a transmission signal; , a transmission signal in which all bits other than the n bit of one frame are made the same as the logic of the F bit, and an F bit of one frame,
The baseband transmission system according to claim 2 or 3, wherein the transmission signal in which all bits other than 0 and 1 are set to logic parts 0# or 1# is switched by the logic of the RDY signal.