JPS5924395B2 - Pulse width measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width measuring device, and is particularly suitable for use as an adjusting device for adjusting circuit constants of a circuit to be adjusted so as to obtain a specific value.

When adjusting the circuit constants of a circuit to be adjusted to obtain a specific value, for example, a pulse width, when measuring the pulse width with a conventional pulse width measuring device, the detection sensitivity of the pulse width measuring device is constant. Detection sensitivity is insufficient near an important specific pulse width, and sensitivity becomes unnecessarily high in areas away from the specific pulse width, resulting in poor efficiency of adjustment work.

The present invention was invented in view of the above points, and includes a clock pulse generator, a gate circuit that gates the clock pulse signal from the clock pulse generator in accordance with the pulse width of the signal under test, and a frequency divider that divides the output signal of the gate circuit; and a detector that includes a logic circuit and detects the frequency division state of the frequency divider and outputs a plurality of pulse signals according to the pulse width of the signal under test. and a D/A converter for D/A converting the output of the detector,
The plurality of pulse signals are configured such that their rising positions and pulse widths are different from each other according to desired characteristics,
The pulse signal is configured to be converted into a nonlinear and continuously changing analog signal in the D/A converter.

With this configuration, even though the circuit configuration is simple, it is possible to perform accurate counting with high detection sensitivity when counting and detecting an important specific pulse number or its vicinity, and When counting and detecting parts far from the number, the efficiency of measurement work can be increased with low detection sensitivity. Further, the change in the analog signal can be made smooth, and by changing the rising positions of the plurality of pulse signals, etc., the curve itself representing the nonlinear characteristics of the analog signal can be changed into a desired shape. The present invention will be explained below with reference to examples and drawings.

FIG. 1 is a block diagram showing the entire measurement system when adjusting the circuit constants of the circuit to be adjusted 2 using the pulse width measuring device 1 to which the present invention is applied. The adjustment described above is performed by the adjuster adjusting the constants of the circuit to be adjusted 2 while looking at the display on the display section 3. Adjustment of the constant is performed by rotating and adjusting electrical variable means such as a variable resistor. During such adjustment work, the value measured by the measuring system (in this case the pulse width) is generally a value far from a specific value, i.e. a value larger or smaller than the specific value, but ,
Through the above adjustment, the value gradually approaches a specific value.

This embodiment is most suitable for use not only when measuring absolute values, but also when adjusting the circuit to be adjusted so as to obtain a specific value as described above.

The parts of the pulse width measuring device 1 in FIG. 1 excluding the display section 3 are configured as shown in FIG. A signal a as shown in FIG. , and when the contact 21b is closed, the output signal c (FIG. 3) of the flip-flop 8 can be selected.

This flip-flop 8 is for obtaining a signal B having a phase difference supplied to input terminals 5 and 6, and a signal c having a pulse width corresponding to the phase difference from B2, and converting the phase difference into a pulse width. . The flip-flop 8 may be set to the set state by the fall of the signal b1, and may be set to the set state by the fall of the signal B2. Signal a or signal c supplied to gate circuit 12 acts as a gate signal for the clock pulse signals from clock pulse generators 9, 10, 11.

The gate circuit 12 is also supplied with an output signal En from a detector 15, which will be described later. When this signal En is supplied, the gate circuit 12 is closed. This is to prevent erroneous counting in which the frequency divider 14 makes one round and performs the second or subsequent counting rounds when a signal with an abnormally large pulse width is supplied. The clock pulse generators 9, 10, and 11 are used to obtain different clock pulse frequencies for reasons to be described later, and their respective outputs are selected by a switch 22 and supplied to a gate circuit 12. Signal a or signal c supplied to differentiation circuit 13 is differentiated here and supplied to frequency divider 14 and gate circuit 16, respectively.

This rising differential signal serves as a clear signal for the frequency divider 14, and this falling differential signal serves as a gate signal for the gate circuit 16. When the clock pulse signal, which is the output of the clock pulse generators 9, 10, 11, is gated with the signal a or the signal c, the signal d shown in FIG. 3 is obtained.

This signal d is supplied to a frequency divider 14 where it is counted,
The state counted by the frequency divider 14 is detected by the detector 15. As a result, one of the signals e1 to EO shown in FIG. 3 (E, in the case of FIG. 3) is obtained from the detector according to the count value. Note that the signal e1
The levels of ~En are all the same. This signal e1~En
The combination of the frequency divider 14 and the detector 15 for obtaining the above is configured as shown in FIG. 4, for example. In FIG. 4, the frequency divider 14 includes flip-flops 25, 26, 27, 2
These flip-flops 25
, 26, 27, and 28 are supplied to the detector 15 as outputs Ql, Q2, Q3, and Q4 of the frequency divider 14, respectively.

The detector 15 is composed of NAND circuits 30, 31, etc., and detects the states of the outputs Q1 to Qn. For example, when the outputs Q1 to Q4 are expressed as shown in FIG.
By NANDing the outputs Q2, Q3, and Q4 in the NAND circuit 30, the signal g1 (FIG. 5) is obtained, and by NANDing the outputs Q3 and Q4 in the NAND circuit 31, the signal G2 (Fig. Figure 5) is obtained.

In this case, the signals g1 and G2 are directly transmitted to the detector 15.
The outputs e1 to En may be obtained by combining the signals g1, G2, etc., or the outputs e1 to En may be obtained by combining the signals g1, G2, etc. In order to obtain the outputs E, ~En shown in FIG. 3 from the detector 15, the detector 15 not only uses the NAND circuits 30 and 31 shown in FIG. It may be a combination of other logic circuits. The output signals E, ~EO of the detector 15 are connected to semi-fixed resistors 181~18n and diodes 191~19n.
are supplied to the gate circuit 16 through the respective channels. The combination of these resistors 181 to 18n and diodes 191 to 19n constitutes a D/A converter, and D/A conversion of signals e1 to En is performed in this D/A converter. There is. During this D/A conversion, signals e1 to En
The level of the analog signal obtained from each signal e
Semi-fixed resistance 18 to vary depending on 1 to En
The resistance value of 1 to 18n is adjusted. To give a specific example, the resistors 181 to 181 are connected so that the voltage value of the analog signal obtained during the 8H1 level period of the signal e1 is 2V, and the voltage value of the analog signal obtained during the 11H8 level period of the signal E2 is 3V. The resistance value of 18n is adjusted. As shown in FIG. 3, each output signal e1~ of the detector 15
En has different rising positions and pulse widths.

In addition, semi-fixed resistors 181 to 18 are connected so that the levels of the analog signals obtained by D/A converting these signals e1 to En are different depending on the signals e1 to EO.
The resistance value of n is adjusted. By doing this, the characteristics shown in FIG. 6 are obtained between the number of clock pulses supplied to the frequency divider 14 and the analog signal h. The characteristics shown in FIG. 6 indicate that the detection sensitivity of the number of clock pulses supplied to the frequency divider 14 is
When a clock pulse of a specific value A or a numerical value close to it is being supplied to the frequency divider 14, the change in the analog output of the D/A converter in response to a change in the number of clock pulses is large, so the clock pulse is high. When clock pulses of different values are being supplied to the frequency divider 14, the D/A for a change in the number of clock pulses is
This means that the change in the analog output of the converter is small, so it is low. As shown in FIG. 7, the output signals E, -En of the detector 15 are obtained as signals e1-En, which differ only in rising positions but have a common falling position, and the resistors 181-18n are adjusted in accordance with these signals. The resistance value may also be adjusted. In the case shown in FIG. 7, the analog signal h is obtained as a signal in which the analog conversion values of the signals e1 to EO are sequentially added.
It is possible to make the resistance values of 8n almost the same. The analog signal h obtained in this manner is supplied to a hold circuit 17 via a gate circuit 16. This gate circuit 16 supplies an analog signal h to a hold circuit 17 when the gate signal obtained by the differentiating circuit 13 is applied. Further, the hold circuit 17 holds the analog signal h supplied as described above, and sends this hold value from the output terminal 7 to the display section 3 shown in FIG. 1, etc. When the pulse width measurement circuit 1 described above measures the pulse width of the signal a obtained from the circuit to be adjusted 2 and adjusts the circuit to be adjusted 2, the clock pulse generators 9, 10, and 11 are activated by the switch 22. Therefore, it is selectively switched.

In this case, the pulse width of the signal a or c to be measured obtained from the adjusted circuit 2 is set appropriately so that the pulse width of the signal a or c to be measured obtained from the adjusted circuit 2 is supplied to the frequency divider 14 with a specific number of pulses shown in FIG. The clock pulse generators 9 to 11 that generate clock pulses of various frequencies are switched and selected. Display section 3 is the eighth
It is configured as shown in the figure. This display section 3 displays the signal f
It is used when detecting the peak of The input terminal 41 is supplied with the signal f obtained as described above. This signal f is supplied to a meter 49 as well as to the ten terminal of an amplifier 46 which acts as a comparator.
Further, the hold value of the signal f obtained from the peak hold circuit 45 to which the signal f is supplied is supplied to one terminal of the amplifier 46 . The amplifier 46 outputs l! when the signal f is less than the peak value m! L1, and when the signal f is equal to or greater than the peak value m, the output n is ! 1H8. The output n of the comparison amplifier 46 is supplied to an AND circuit 47 and a counter 48.

When the counter 48 has counted the number determined by the control signals supplied to the input terminals 42 and 43,
The output is 11H11. counter 48
The output 0 is supplied to the AND circuit 47. AND circuit 4
7 is for taking the AND of the signal n of the amplifier 46 and the output signal 0 of the counter 48, so that both the signal n and the signal 0 are 1.
When the voltage becomes 1H1, the output p becomes 1H1. Next, the operation of the configuration described above will be explained.

Now, suppose that the signal f shown in FIG. 9 is obtained by rotating and adjusting the electrical variable means such as a variable resistor in the circuit to be adjusted 2 in positive and negative directions while looking at the meter 49. In other words, when trying to adjust the rotation of an electrical variable means such as a variable resistor so that the signal f becomes the peak voltage EV, the user first rotates it in the negative direction, then realizes that the rotation direction is reversed and rotates it in the positive direction. When it passes the peak, it rotates in the negative direction to return to the peak point, and as a result, the signal f shown in FIG.
Suppose that we obtain Peak hold circuit 45 at this time
The output of the amplifier 46 becomes a signal m shown in FIG. 9, and the output of the amplifier 46 becomes a signal n shown in FIG. Conventionally, the peak was detected based on the rise of the output signal n of the amplifier 46.

Therefore, when the level of the input signal f shown in FIG. 9 once decreases and then increases again by adjusting the rotation of an electrical variable means such as a variable resistor, the signal n will be It stands up as shown in Figure 9. However, even if the level of the input signal once drops, then rises again, and then reaches the original level, this level is not necessarily the peak point, as in the case of signal f shown in Figure 9, so in this case will result in false detection of the peak point. However, in this embodiment, the counter 48 is set to output 1H1 when it counts the rising edge of the signal n twice by the signals supplied from the terminals 42 and 43. The output 0 of is as shown in FIG. Note that since the output n of the amplifier 46 and the output 0 of the counter 48 are supplied to the AND circuit 47, the signal f is equal to the peak value m held by the peak hold circuit 45, as shown in FIG. Or, the output p of the AND circuit 47 becomes ゛1H only when it becomes larger than this peak value m twice or more.
It becomes 8. Therefore, if the peak point is detected when the signal p becomes FlH, there is no possibility of erroneous detection as described above in the conventional art. As mentioned above,
According to the present invention, the detector includes a logic circuit and detects the frequency division state of the frequency divider and outputs a plurality of pulse signals according to the pulse width of the signal under test, and the plurality of pulse signals are The pulse signal is configured such that its rising position and pulse width are different from each other depending on the desired characteristics, and the pulse signal is
Since it is configured to be converted into an analog signal that changes non-linearly and continuously in the /A converter, the detection sensitivity of the number of clock pulses supplied to the frequency divider is high enough to detect clock pulses of a specific value or a value in the vicinity. is being supplied to the frequency divider, the change in the analog output of the D/A converter in response to a change in the number of clock pulses is large and therefore high, and clock pulses with a numerical value far from the specified value are supplied to the frequency divider. When the number of clock pulses is increasing, the change in the analog output of the D/A converter with respect to the change in the number of clock pulses is small, so it is low.

Therefore, even though the circuit configuration is simple, it is possible to perform accurate counting with high detection sensitivity when counting and detecting the important specific pulse number or its vicinity, and it is possible to count and detect the important specific pulse number or its vicinity. When detecting, the efficiency of measurement work can be increased with low detection sensitivity. In addition, it is possible to smooth the changes in the analog signal, and
By changing the rising positions of the plurality of pulse signals, etc., the curve itself representing the nonlinear characteristics of the analog signal can be changed into a desired shape.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram showing the entire measurement system when adjusting the circuit constant of the circuit to be adjusted 2 using a pulse width measuring device to which the present invention is applied. 2 is a block diagram showing the pulse width measuring device 1 shown in FIG. 1 with the display section 3 omitted, FIG. 3 is a waveform diagram for explaining the pulse width measuring device 1 shown in FIG. 2, and FIG.
The figure is a circuit diagram showing the frequency divider 14 and detector 15 shown in Fig. 2, Fig. 5 is a waveform diagram for explaining the circuit shown in Fig. 4, and Fig. 6 is a pulse width measurement shown in Fig. 2. 7 is a waveform diagram for explaining the pulse width measuring device shown in FIG. 2, FIG. 8 is a circuit diagram showing the display section 3 shown in FIG. 1, and FIG. 9 is a characteristic diagram for explaining the device 1. This figure is a waveform diagram for explaining the circuit shown in FIG. 8. In addition, in the symbols used in the drawings, 9, 10, 1
1 is an oscillator, 14 is a frequency divider, 15 is a detector, 181 to 1
8n is a resistor, 191 to 19n are diodes, 45 is a peak hold circuit, 46 is an amplifier, 47 is an AND circuit, 4
8 is a counter.

Claims (1)

[Claims] 1. A clock pulse generator, a gate circuit that gates the clock pulse signal from this clock pulse generator in accordance with the pulse width of the signal under test, a frequency divider that divides the output signal of this gate circuit, and a logic a detector consisting of a circuit that detects the frequency division state of the frequency divider and outputs a plurality of pulse signals according to the pulse width of the signal under test; and a D/A that converts the output of the detector into a D/A. A converter, the plurality of pulse signals are configured such that their rising positions and pulse widths are different from each other according to desired characteristics, and the pulse signals are nonlinear and continuous in the D/A converter. 1. A pulse width measurement device characterized in that the pulse width measurement device is configured to convert the pulse width into an analog signal that changes over time.