JPS5923665B2 - Subscriber line test circuit - Google Patents

Subscriber line test circuit

Info

Publication number
JPS5923665B2
JPS5923665B2 JP53165809A JP16580978A JPS5923665B2 JP S5923665 B2 JPS5923665 B2 JP S5923665B2 JP 53165809 A JP53165809 A JP 53165809A JP 16580978 A JP16580978 A JP 16580978A JP S5923665 B2 JPS5923665 B2 JP S5923665B2
Authority
JP
Japan
Prior art keywords
line
insulation resistance
subscriber line
circuit
test circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53165809A
Other languages
Japanese (ja)
Other versions
JPS5592065A (en
Inventor
健 坂井
栄治 猪西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53165809A priority Critical patent/JPS5923665B2/en
Publication of JPS5592065A publication Critical patent/JPS5592065A/en
Publication of JPS5923665B2 publication Critical patent/JPS5923665B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/26Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
    • H04M3/28Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
    • H04M3/30Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Description

【発明の詳細な説明】 本発明は加入者線における線間絶縁抵抗を正確に測定す
ることができる加入者線試験回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a subscriber line test circuit that can accurately measure line-to-line insulation resistance in subscriber lines.

電話交換システムにおいて、交換機から端末装置を介し
て電話加入者が接続される加入者線にお 。
In a telephone switching system, the line from the exchange to the subscriber line where telephone subscribers are connected via terminal equipment.

ける異常の有無を知るため、加入者線試験が行われる。
加入者線試験は通常、加入者線のAB両線、間の線間絶
縁抵抗ZAB、A線またはB線と対接地間の絶縁抵抗Z
A、ZBおよび容量CA、CBを対象として行われる。
第1図は加入者線およびその試験状態を示す図である。
Subscriber line tests are conducted to determine whether there are any abnormalities in the network.
Subscriber line tests usually test the subscriber line's AB wires, the inter-line insulation resistance ZAB, and the insulation resistance Z between the A wire or B wire and grounding.
This is done targeting A, ZB and capacitances CA, CB.
FIG. 1 is a diagram showing a subscriber line and its test status.

同図において1は試験回路、2は電話機、ZAB、ZA
、ZBは絶縁抵抗、Coは線間容量である。このような
加入者線試験のうち、線間絶縁抵抗ZABの測定には従
来第2図に示すごとき方法がとられていた。
In the figure, 1 is a test circuit, 2 is a telephone, ZAB, ZA
, ZB is insulation resistance, and Co is line capacitance. Among such subscriber line tests, the method shown in FIG. 2 has conventionally been used to measure the line-to-line insulation resistance ZAB.

同図に示すごとく、直列抵抗Zoを介して電源+Vin
を一方のライン、例えばA線に接続し、他方のラインB
線を接地して、A線と接地間の電圧Voutを測定する
ことによつてZABを測定していた。しカルながら第2
図から明らかなように、このような接続方法によつて測
定されるのは線間絶縁抵抗ZABと、A線と接地間の絶
縁抵抗ZAの並列絶縁抵抗である。すなわち第2図にお
いて V0ut=Vin× (1) ZA+ZAB の関係が成立するからである。
As shown in the figure, the power supply +Vin is connected through the series resistor Zo.
to one line, e.g. A line, and the other line B
ZAB was measured by grounding the line and measuring the voltage Vout between the A line and ground. second
As is clear from the figure, what is measured by this connection method is the parallel insulation resistance of the line-to-line insulation resistance ZAB and the insulation resistance ZA between the A line and the ground. That is, in FIG. 2, the following relationship holds: V0ut=Vin×(1) ZA+ZAB.

従つて第2図の測定法によつては、正しく線間絶縁抵抗
ZABを測定できない欠点があつた。
Therefore, the measuring method shown in FIG. 2 has the disadvantage that the line-to-line insulation resistance ZAB cannot be measured correctly.

本発明はこのような従来技術の欠点を除去しようとする
ものであつて、その目的は、バランス回路を用いて測定
することにより1線接地間絶縁抵抗の影響を受けること
が少く、正確に線間絶縁抵抗の測定ができる加入者線試
験回路を提供することにある。この目的を達成するため
本発明の加入者線試験回路においては、2線からなる加
入者線をそれぞれ直列抵抗を経て正電源と負電源に接続
したとき生じる前記2線の電位をそれぞれ入力とする一
個のエミッタフォロアからなる回路と、該回路の両出力
をそれぞれ入力とする差動増幅器とを具え、該差動増幅
器の出力電圧によつて前記加入者線の線間絶縁抵抗を測
定し得ることを特徴としている。以下、実施例について
説明する。
The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to reduce the influence of the insulation resistance between one wire and ground by using a balance circuit, and to accurately measure the wire and ground. An object of the present invention is to provide a subscriber line test circuit capable of measuring insulation resistance between cables. In order to achieve this object, the subscriber line test circuit of the present invention inputs the potentials of the two wires that are generated when the subscriber lines each consisting of two wires are connected to a positive power source and a negative power source through series resistors. It comprises a circuit consisting of one emitter follower and a differential amplifier which receives both outputs of the circuit as inputs, and the line-to-line insulation resistance of the subscriber line can be measured by the output voltage of the differential amplifier. It is characterized by Examples will be described below.

第3図は本発明の加入者線試験回路の一実施例の構成を
示す回路図である。
FIG. 3 is a circuit diagram showing the configuration of an embodiment of the subscriber line test circuit of the present invention.

同図において、Q1、Q2,Q3,Q4はトランジスタ
、ZDはツエナーダイオード〜 R1?R2?R3,R
4,R5,R6,R7,R8は抵抗、Zl,Z2は直列
抵抗である。今、第2図に示すごとく、直列抵抗Zl,
Z2を通じてそれぞれ正電源+1、および負電源−V2
をA線およびB線に接続する。両線の電圧をエミツタフ
オロアを構成するトランジスタQl,Q2のベースにそ
れぞれ入力し、それぞれのエミツタに得られた出力を差
動増幅器Q3,Q4によつてさらに増幅して出力電圧0
utを生じる。両トランジスタQ,,Q2はコレクタ接
地形に接続されているから、その入力インピーダンスは
十分高く、従つて絶縁抵抗ZAB,ZA,ZBに影響を
及ぼすことがない。
In the figure, Q1, Q2, Q3, and Q4 are transistors, and ZD is a Zener diode ~ R1? R2? R3,R
4, R5, R6, R7, and R8 are resistors, and Zl and Z2 are series resistors. Now, as shown in Figure 2, the series resistance Zl,
positive power supply +1 and negative power supply −V2 respectively through Z2
Connect to A and B wires. The voltages on both lines are input to the bases of transistors Ql and Q2 that constitute the emitter follower, and the outputs obtained at the respective emitters are further amplified by differential amplifiers Q3 and Q4, resulting in an output voltage of 0.
produce ut. Since both transistors Q, , Q2 are connected to the collector ground plane, their input impedance is sufficiently high and therefore does not affect the insulation resistances ZAB, ZA, ZB.

線間絶縁抵抗ZABが大きいときは両トランジスタQl
,Q2のベース間に加えられる電位差が大きく、従つて
トランジスタQ3の電流が大きくトランジスタQ4の電
流は小さい。従つてトランジスタQ3のコレクタから取
り出される出力電圧VOutは小さくなる。逆に線間絶
縁抵抗ZABが小さいときは出力電圧VOutは大きく
なる。直列抵抗Z,,Z2の値およびトランジスタQ,
,Q4の利得は一定なので出力電圧VOutと線間絶縁
抵抗ZABとは一定の関係があり、出力電圧0utの測
定によつて線間絶縁抵抗を知ることができる。このよう
にして、バランス形の回路で測定することによつて線間
絶縁抵抗ZABをより正確に測定することができる。
When line insulation resistance ZAB is large, both transistors Ql
, Q2 is large, and therefore the current of transistor Q3 is large and the current of transistor Q4 is small. Therefore, the output voltage VOut taken out from the collector of transistor Q3 becomes smaller. Conversely, when the line insulation resistance ZAB is small, the output voltage VOut becomes large. The value of series resistance Z, , Z2 and transistor Q,
, Q4 are constant, there is a constant relationship between the output voltage VOut and the line insulation resistance ZAB, and the line insulation resistance can be determined by measuring the output voltage 0ut. In this way, by measuring with a balanced circuit, the line-to-line insulation resistance ZAB can be measured more accurately.

ただしこの場合も、測定される線間絶縁抵抗ZABは、
1線接地間絶縁抵抗ZAZBの直列回路が並列に接続さ
れたものとツなることは言うまでもない。
However, in this case as well, the measured line insulation resistance ZAB is
It goes without saying that the series circuit of the one-line-to-ground insulation resistance ZAZB is connected in parallel.

なお第3図において、ツエナーダイオードZdは、トラ
ンジスタQ3,Q4のエミツタバイアスを一定にするた
めに用いられている。このように、本発明の加入者線試
験回路においては、線間絶縁抵抗の測定にバランス回路
を使用したため、1線接地間絶縁抵抗ZA,ZBの影響
が少く、従来の加入者線試験回路に比べ、線間絶縁抵抗
ZABをより正確に測定できる利点がある。
In FIG. 3, the Zener diode Zd is used to keep the emitter bias of the transistors Q3 and Q4 constant. As described above, in the subscriber line test circuit of the present invention, since a balance circuit is used to measure the line-to-line insulation resistance, the influence of the 1-wire-to-ground insulation resistance ZA, ZB is small, and the subscriber line test circuit of the present invention is different from the conventional subscriber line test circuit. Compared to this, there is an advantage that the line-to-line insulation resistance ZAB can be measured more accurately.

なお第4図は本発明が適用される、端末3−,ラ3−2
,・・・3−。
Note that FIG. 4 shows terminals 3- and 3-2 to which the present invention is applied.
,...3-.

、端末装置4、親装置5、交換機6からなる電話交換シ
ステムを示したものである。以上説明したように本発明
の加入者線試験回路によれば、2線からなる加入者線を
それぞれ直列抵抗を経て正電源と負電源に接続したとき
生じる2線の電位をそれぞれ入力とする2個のエミツタ
フオロアからなる回路と、この回路の両出力をそれぞれ
入力とする差動増幅器とを具え、この差動増幅器の出力
電圧によつて加入者線の線間絶縁抵抗を測定するように
したので、1線接地間絶縁抵抗の影響を受けることが少
なく、加入者線の線間絶縁抵抗の値をより正確に測定す
ることができる。
, a telephone switching system consisting of a terminal device 4, a master device 5, and a switch 6. As explained above, according to the subscriber line test circuit of the present invention, the potentials of the two lines that are generated when the subscriber lines each consisting of two wires are connected to the positive power supply and the negative power supply through the series resistors are respectively input. The system is equipped with a circuit consisting of two emitter followers and a differential amplifier which receives both outputs of this circuit as inputs, and the line-to-line insulation resistance of the subscriber line is measured by the output voltage of this differential amplifier. , it is less affected by the insulation resistance between one line and ground, and the value of the insulation resistance between the subscriber lines can be measured more accurately.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は加入者線とその試験状態を示す図、第2図は従
来の線間絶縁抵抗測定回路を示す図、第3図は本発明の
加入者線試験回路の一実施例の構成を示す回路図、第4
図は本発明が適用される電話交換システムを示すプロツ
ク図である。 1・・・・・・試験回路、2・・・・・・電話機、3−
,,3−2,・・・3−。
Fig. 1 shows a subscriber line and its test status, Fig. 2 shows a conventional line-to-line insulation resistance measuring circuit, and Fig. 3 shows the configuration of an embodiment of the subscriber line test circuit of the present invention. Circuit diagram shown, 4th
The figure is a block diagram showing a telephone switching system to which the present invention is applied. 1...Test circuit, 2...Telephone, 3-
,,3-2,...3-.

Claims (1)

【特許請求の範囲】[Claims] 1 2線からなる加入者線をそれぞれ直列抵抗を経て正
電源と負電源に接続したとき生じる前記2線の電位をそ
れぞれ入力とする2個のエミツタフオロアからなる回路
と、該回路の両出力をそれぞれ入力とする差動増幅器と
を具え、該差動増幅器の出力電圧によつて前記加入者線
の線間絶縁抵抗を測定し得ることを特徴とする加入者線
試験回路。
1. A circuit consisting of two emitter followers each receiving the potential of the two wires generated when the subscriber line consisting of two wires is connected to a positive power source and a negative power source through series resistors, and both outputs of the circuit, respectively. A subscriber line test circuit comprising a differential amplifier as an input, and capable of measuring line-to-line insulation resistance of the subscriber line based on the output voltage of the differential amplifier.
JP53165809A 1978-12-30 1978-12-30 Subscriber line test circuit Expired JPS5923665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53165809A JPS5923665B2 (en) 1978-12-30 1978-12-30 Subscriber line test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53165809A JPS5923665B2 (en) 1978-12-30 1978-12-30 Subscriber line test circuit

Publications (2)

Publication Number Publication Date
JPS5592065A JPS5592065A (en) 1980-07-12
JPS5923665B2 true JPS5923665B2 (en) 1984-06-04

Family

ID=15819400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53165809A Expired JPS5923665B2 (en) 1978-12-30 1978-12-30 Subscriber line test circuit

Country Status (1)

Country Link
JP (1) JPS5923665B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443639Y2 (en) * 1988-05-27 1992-10-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0443639Y2 (en) * 1988-05-27 1992-10-15

Also Published As

Publication number Publication date
JPS5592065A (en) 1980-07-12

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