JPS5923523A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate occurring of abnormal discharge even when reverse sputter etching is performed to secure the connection, by a method wherein when an insulation film and a conductive layer are laminated on a semiconductor substrate with diffusion region formation, the conductive layer is connected directly to the substrate utilizing a scribed line bored on the insulation film. CONSTITUTION:N<+> type diffusion region is formed on P type Si substrate 25, and whole surface including these is coated with a gate insulation film 26. An opening is bored corresponding to the diffusion region, and a scribe line S is also bored and surface of the substrate 25 is exposed to the scribe line S. When a first conductive layer 23 comprising polycrystalline Si layer is applied to the film 26, the conductive layer 23 is contacted with the diffusion region and at the same time separated therefore and overhung and contacted to the substrate 25. When a second conductive layer 24 comprising Al layer is applied onto the layer 23 through PSG film 27, the layer 24 is overhung in the line S and the overhung 23a on the layer 23 and the overhung 24a on the layer 24 are contacted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to semiconductor devices, and specifically to semiconductor wafers after a UniHaf zero process.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, even in devices with a multilayer wiring structure, higher precision and more stable electrical characteristics are required. When electrically touching, the underlying conductive single layer may generate abnormal discharge and melt. As a result, the conductor may be re-attached to the entire surface of the wafer. This results in defective products and reduced reliability.

That is, an element with a multilayer wiring structure is constructed by depositing a first insulating film, such as a first SIO□ film (2), on a semiconductor substrate, such as a P-type silicon substrate (1), as shown in FIG. A first conductor layer, for example a polysilicon layer (3), is selectively formed. A second insulating film, for example, a second 5102 film (4) is deposited on this polysilicon layer (3), and this 8102
A second conductor layer, for example an aluminum layer (5), is placed on top of the membrane (4).
) to form. An insulating film, such as a 5IO2 film (6), is formed on this aluminum layer (5).

In such a structure, when depositing the second conductive layer, for example, the aluminum layer (4), the polysilicon layer (3) is reverse sputter etched immediately before depositing the second conductive layer, for example, to ensure electrical connection. It is. And after this, Snow! The aluminum layer (5) described above is deposited by ivy deposition. Nao (7
) is a diffusion layer forming the drain and source.

On the other hand, in recent years, exposure has been increasingly performed using the Stellar 0-and-repeat method even in devices having the above-mentioned multilayer wiring structure. This is because in recent years, devices have been required to be more precise and denser, and in such cases, the aberrations of the exposure lens pose a problem in resolution at the periphery, resulting in variations in device characteristics between the middle heat section and the periphery. This is also due to the increasing number of devices with large chip sizes such as VL8 I.

Moreover, in order to achieve high resolution, positive photoresist 1 is required, and in the step-and-repeat exposure method described above, the part of wafer 0→ shown in FIG. Exposure is not performed on the 1-related area 0 indicated by a dot, and therefore the insulating film and conductor layer remain as they are on the peripheral area 0).

As shown in an enlarged view in FIG. 3, the scribe line 0→ has a width of, for example, 100μ+11, and no insulating film or conductive film is formed on this scribe line a+ due to the subsequent scribing process. For this reason, the conductor layer left on the peripheral edge α force becomes a floating electrode with respect to the silicon substrate.

As described above, when reverse sputter etching is performed as a pretreatment for vapor deposition of a conductor layer, a strong electric field is formed, which tends to cause abnormal discharge in the floating electrode region. This abnormal discharge causes the sifting electrode to melt and re-deposit on the entire surface. Such abnormal discharge occurs particularly at the periphery of the unit, that is, the periphery α shown as scattered dots in Fig. He was inviting the people.

Of course, the floating electrode on the peripheral edge part α can be removed later by performing a mask alignment process or an etching process. However, doing so will increase the number of steps. Moreover, the yield rate also deteriorates.

Purpose of the Invention The present invention has been made in consideration of the above circumstances, and an object of the present invention is to eliminate the 70-ting at the peripheral edge without increasing the number of steps.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention connects the conductive layer left at the peripheral edge directly to the semiconductor substrate. Such a semiconductor device eliminates abnormal discharge during reverse sputter etching, improving reliability and yield. Moreover, there is no need to increase the number of processes.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 shows a part of the semiconductor device of this example, and in this figure, a plurality of chip devices Q are formed on a wafer Q. In this semiconductor device, the mask for selectively depositing (selectively removing) the conductor layer, that is, the silicon layer (1) and the first aluminum layer (C) to be described later, shall cover the area indicated by the dashed-dotted line. . That is, assume that the square chip device (a) is slightly protruded. Then, the polysilicon layer (g) and the polysilicon layer (g) are formed. That is, this area is prevented from being exposed to light.

FIG. 5 shows a cross section taken along the line 1--2 in FIG. (c) is deposited, and a first conductor layer, such as a polysilicon layer (c), is formed thereon.

A second insulating layer, such as a phosphor glass layer (b), is deposited on the terisilicon layer (c).
A second conductive layer such as a first aluminum layer (2
G is selectively deposited. And this first aluminum J
For example, a 5I02 film (c) is formed on the @(c), and a second aluminum layer (not shown) is formed thereon.

As is clear from the figure, the polysilicon layer (c) and the first aluminum layer (c) hang downward in the scribe line region S, and are directly bonded to the silicon substrate (c). It has become.

Let these hanging parts be (23n) and (24u).

Note that (c) indicates the diffusion region.

In such a configuration, the first aluminum layer Q→
There are no disadvantages when depositing the second aluminum layer (as shown) by sputtering. That is, when selectively depositing the first aluminum layer (c), the polysilicon layer (g) is reversely etched just before depositing the first aluminum layer (c). However, the polysilicon layer is exposed to the non-ringing part (23a).
) Since it is directly connected to the silicon substrate, it is no longer in a floating state, and therefore, this 1q
Abnormal discharge does not occur in the IJ silicon layer, and therefore the phenomenon of re-silicon deposits on the polysilicon layer does not occur.

Similarly, the first aluminum layer is selectively deposited immediately before the second aluminum layer is selectively deposited.
Even if the aluminum layer (c) is reversely etched, the first aluminum layer (c) is connected to the silicon substrate (c) through the grooved portion (24a), so the first aluminum layer (c) is also connected to the silicon substrate (c). Is the aluminum layer (c) redided71? jitter is avoided.

In addition, the 71 ringing part (23a) on the chip device (A) side
(24a) prevents the edge of the chip device e4 from receiving the scribe damage. Therefore, a level is not formed on the scribe line side, and the electrical characteristics of the chip device are not adversely affected.

The semiconductor device configured as described above is later transferred to an assembly process such as scrubbing and manufactured as a semiconductor device.

Effects of the Invention As described above, according to the present invention, the single conductive layer at the periphery of the wafer is connected to the semiconductor substrate. No discharge occurs, and therefore it is possible to avoid an increase in the number of defective products and a decrease in reliability due to redepositing of the conductor layer.

Moreover, there is no increase in the number of processes.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing a conventional example, Fig. 2 is a similar plan view,
3 is a similar enlarged plan view, FIG. 4 is a plan view showing a part of the invention, and FIG. 5 is a sectional view taken along the line V-Vi in FIG. 4. Q is a sea urchin, the ridge is a chip, (b) is a polysilicon layer, (c) is a first aluminum layer, and (c) is a silicon substrate.

Claims (1)

[Claims] A first pattern of a conductor layer is periodically formed on one main surface of the semiconductor substrate with an insulating layer interposed therebetween, and a second pattern different from the first pattern is formed on the peripheral edge of the semiconductor substrate. of! 1. A semiconductor device in which a turn conductor layer is formed, wherein the second pattern is electrically pressure-connected to the semiconductor substrate near an edge of the first pattern.