JPS5923187B2 - Seifdengen Ogbisultashutsuriyoku - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-output switching regulator equipped with positive and negative power supplies.

Conventionally, in single-input, multi-output switching regulators equipped with positive and negative power supplies, it has been difficult to share an auxiliary power supply circuit, an oscillation circuit, etc. due to mutual interference caused by noise.

For this reason, each circuit had an independent configuration. auxiliary power supply,
If the oscillation circuit etc. are shared, the number of components in the output side control circuit system will be reduced, and the characteristics for each output will be uniform, improving stability. However, on the other hand, common control for positive and negative input signals There is a drawback that the interface conditions for matching such as polarity mismatch with the signal are complicated.

In addition, if the alarm signal circuit that sends out an alarm signal when a protection circuit for overvoltage, overcurrent, etc. is activated, or any output protection circuit is activated, it would be possible to minimize the component composition and make it common for multiple output switching regulators. The advantages mentioned above are further enhanced. The present invention has been made in consideration of the above-mentioned points, and is a multi-output switching device that is equipped with positive and negative power supplies that share an auxiliary power circuit, an oscillation circuit, etc. for a control circuit system without causing mutual interference due to noise, etc. It provides a regulator. Embodiments of the present invention will be described in detail below with reference to the drawings.

1 to 3 are circuit configuration diagrams showing common circuit parts of a multi-output switching regulator equipped with positive and negative power supplies according to the present invention, and FIG. 1 shows a power supply circuit.

AC line input 10 is connected to AC line input 10 through filter circuit 101.
It is directly rectified by the rectifier 12 of the line direct rectification and smoothing circuit 11, smoothed by the smoothing circuit 13 using a capacitor, and converted into a DC voltage. The smoothing circuit 13 is the rectifier 1
Smoothing capacitor 13 connected between output terminals P and N of 2
1 and a capacitor 132, which divides the voltage between the output terminals into two.
33, and a terminal C is provided between the two divided capacitors. Terminals P, C, and N are connected to the same terminals P, C, and N of the converter circuit 14 shown in FIG. 4, respectively, and supply a DC voltage. The auxiliary power supply circuit 27 has a transformer 28 having three windings on the secondary side, and the primary winding is connected to the output side of the filter circuit 101.

Each bridge type double-wave rectifier 291, 29 is installed in the secondary winding.
2,293 are connected.

A smoothing capacitor 301 and a regulator 31 are connected in parallel to the output terminal of the rectifier 291.
, outputs +15V DC voltage to the output terminal. Further, a smoothing capacitor 302 and a regulator 312 are connected in parallel to the output terminal of the rectifier 292, and a DC voltage with a reference voltage of 0V1, that is, -15V, is output to the output terminal of the regulator. Furthermore, a smoothing capacitor 30 is connected to both ends of the rectifier 293.
3 is connected to obtain +15V DC voltage. FIG. 2 shows the oscillation circuit.

Oscillator circuit 15 generates three clock pulses CP1, CP2 and CP3. two nand gates 151,1
52 constitutes an astable multivibrator 15N, and its output is supplied to the T terminal of the T flip-flop 15F0) and is used as a first signal inverted by a NAND gate 153. This signal is delayed by a delay circuit De and then inverted by a NAND gate 154. The second signal is generated by inputting the first and second signals to the NUN gate 15, which generates a clock pulse CP1 at the terminal CP1.

On the other hand, the outputs of the T flip-flop F(7)Q and Q are input to individual NAND gates 156 and 157, and are multiplied by the output of the astable multivibrator 15N to output terminals CP2 and CP2, respectively.
Clock pulses CP2 and CP3 are output to CP3. The pulses supplied from the clock pulse terminals CPl, CP2, and CP3 have the phase characteristics shown in FIG.
is supplied to the pulse width conversion circuit shown in FIG. 12, and pulses CP2 and CP3 are supplied to the primary side drive circuit 16 shown in FIG.
supplied to FIG. 4 is a circuit connection diagram mainly on the secondary side, that is, the output side, of the multi-output switching regulator according to the present invention, in which blocks 251 and 25 are the drive circuits shown in FIG. 12, 23, 232 are the error voltage amplifiers shown in FIG. 13, and 261, 262 are the overcurrent detection amplifiers shown in FIG. 14, respectively.

The converter circuit 14 in FIG. 4 includes two diodes 14,
, 142 and power transistors Trl and Tr2. The collector of the transistor Tr2 is connected to the terminal P, its emitter is connected to the collector of the transistor Trl, and the primary winding 1 of the converter transformer 17
Connected to terminal C via 7P. The emitter of power transistor Trl is connected to terminal N. Diodes 141, 142 are connected in parallel between the emitters and collectors of power transistors Trl, Tr, respectively, and two outputs of the primary side drive circuit 16 are input individually to the bases of transistors Tr, Tr2. clock pulse CP2 supplied from the oscillation circuit 15 shown in FIG.
, CP3. That is, the primary side drive circuit 16 includes two transformers 16A, 16B and 2.
The collectors of the transistors 16, 162 are connected to the power supply via the primary windings 16A1, 16B1 of the transformers 16A, 16B.

In this configuration, when clock pulse CP2 is input to the base of transistor 161 and clock pulse CP3 is input to the base of transistor 162, the primary winding 1
6A,, 16B, and the secondary winding 1 of the transformer.
A boosted clock pulse appears at 6A2, 16B, and turns on the power transistors Tr, Tr2 alternately. The output of the converter circuit 14 is the converter transformer 17
is supplied to the primary winding 11P of.

As described above, since the clock pulses CP2 and CP3 alternately drive the respective transistors Trl and Tr2, the voltage waveform VTR between the terminals of the primary winding 1rP of the transformer 17 has the operating waveform shown in FIG. 6c. In the waveform of FIG. 6c, the period Toff is the storage time of the power transistors Trl and Tr2 for the input signal. As shown in the figure, CP2'CP3 has an operating configuration that has a rest period long enough to turn off the power transistor. Therefore, both transistors have a characteristic that they are never conductive at the same time under any condition. In FIG. 4, the power circuit system will be described first.

The converter transformer 17 has two windings with different numbers of windings on the secondary side.
Two windings 17S1 and 17S2 are provided, and each valley winding is provided with a center tap. Diodes Dl, D2, D3, and D4 are connected to both ends of the secondary winding, respectively, to form double-wave rectifier circuits 181 and 182, and the output of the converter circuit 14, which has been stepped down by the converter transformer 17, is connected to +15V and - Converts to two 5V DC outputs.

The anodes of the diodes Dl and D2 of the rectifier circuit 181 are connected to the emitter of a PNP switching transistor Tr3 constituting the switching control circuit 19, and the collectors are connected to the smoothing circuit 201. Center tap is 0
It is drawn out as a V line. On the other hand, the rectifier circuit 182 draws out the anodes of the diodes D3 and D4 as a 0V line, has a center tap connected to the collector of a PNP switching transistor Tr4 constituting the switching control circuit 192, and has an emitter connected to the smoothing circuit 202.
The smoothing circuits 201 and 202 are composed of diodes D5 and D6, choke coils L, L2, and smoothing capacitors Cl and C2. The smoothing circuit 201 outputs a DC voltage of +15V, and the smoothing circuit 202 outputs a DC voltage of -5V. Current detection circuits 21, 212 consisting of valley resistors are inserted into the two 0V lines on the output side, and overvoltage detection circuits 221, 222 are connected between the +15V line and the 0V line, and between the -5V line and the 0V line. Ru.

Next, we will discuss the control circuit system. Error voltage amplifier 231
The input terminal D is connected to the +15V line of the power circuit system,
The output end is connected to the input end A of the pulse width conversion circuit 241. In addition, the input terminal F of the overcurrent detection amplifier 261 is connected to the current detection circuit 211, and its output is connected to the pulse width conversion circuit 2.
It is connected to the input terminal A1 of 41. Pulse width conversion circuit 24
1 is connected to the input terminal C1 of the drive circuit 251, and the secondary winding 25T2 of the transformer 25T in the drive circuit 251 has one end connected to the emitter of the transistor Tr3 of the switching control circuit 191 and the other end connected to the base. It is connected. On the other hand, the error voltage amplifier 232 has an input terminal E connected to the -5V line of the power circuit system, and an output terminal connected to the input terminal A2 of the pulse width conversion circuit 242.

In addition, the input terminal G of the overcurrent detection amplifier 262 is connected to the current detection circuit 2.
12, its output is connected to the input terminal A2, and the reference voltage is input from the auxiliary power supply circuit 21 to its positive input terminal,
Moreover, this voltage is stabilized by a Zener diode ZD. The +15V line shown in FIG. 4 is connected to the negative input terminal, a comparison is made with a reference voltage, and a differential voltage is output and input to the pulse width conversion circuit 241 shown in FIG. 12. Further, the amplifier 23 receives a reference voltage (-15V) from the auxiliary power supply circuit 2T to the negative input terminal of the differential amplifier 0A2, and is stabilized by the Zener diode ZD. The voltage of the -5V line in FIG. 4 is input to the positive input terminal and compared with the reference voltage. The differential voltage at this time is input as an amplifier output to the input terminal A2 of the pulse width conversion circuit 242 shown in FIG. In FIG. 9, a shows the operating characteristics of the input side of the error voltage amplifier, and b shows the operating characteristics of the output end. As shown in FIG. 12, the pulse width conversion circuits 241 and 242 are equipped with a differential amplifier 0A, and have an error voltage amplification 231 or 232 and an overcurrent detection amplifier 26 at their negative input terminals A, A2.
1 or 262 analog outputs are input, and the positive input terminal is connected to the reference power supply E.

Input terminals Al and A2 are grounded via a capacitor 24C and connected to the collector of a transistor Tr via a resistor 24R. The emitter is connected to the +15V terminal of the auxiliary power supply circuit 27, and the clock pulse CPl of the oscillation circuit 15 is input to the base. The transistor Tr3 turns ON at the falling edge of the clock pulse, photoelectrically connecting the capacitor 24C. transistor T
When r, is 0FF at the rising edge of a pulse, capacitor 24C begins discharging and continues until the falling edge of the next pulse, thereby forming a triangular voltage. The output terminal of the differential amplifier 0A is connected to the NAND gate 2 via the inverter 241.
Connected to the 4N input terminal. A clock pulse CP1 is input to the other input terminal of the NAND gate 24N. The output terminal of the NAND gate 24N is connected to the drive circuits 25, 25.
2 input terminals Cl and C2. FIG. 11 shows the drive circuit. The input of the input terminals Cl, C, is applied to the base of the switching transistor Tr6 via the inverter 251, the emitter of the transistor is grounded, and the collector is connected to the primary winding 25T1 of the transformer 25T.
A current is supplied from the auxiliary power supply circuit 27 to the winding 25T1 in response to inputs from the terminals C, , C2. The secondary winding 25T2 of the transformer 25T is connected to transistors Tr, Tr4 of switching control circuits 191, 192, respectively. Pulse width conversion circuit 2 using Fig. 10
The operation of 41 and 242 will be explained.

a is clock pulse CPl, b is Al during steady operation, A
Operating waveforms at two points, C is the operating waveform at points Al, A, when the input to the error voltage amplifier is small, d is the operating waveform at two points A, A and A when the input to the error voltage amplifier is large, and e is the steady operation. , f indicates the operating waveform at point B during normal operation, and f indicates the operating waveform at points C, , and C2 during steady operation, respectively. Illustrated, Al, A
The triangular waves at two points are shifted by the output voltage of the error voltage amplifier and compared with a set threshold level, and the comparison output is output to point B. Here, if the input of the error voltage amplification is small and the output of the error voltage amplifier is therefore large, the output voltage of the triangular wave will also be greater than the threshold level, and the comparison output will be fixed at "H" (high voltage). . When the drive circuits 251, 252 shown in FIG. 11 are operated with this voltage signal, the transistors Tr, Tr4 of the switching control circuits 191, 192 remain conductive, and the transistor
All the burden is added to r,, Tr2, and it has disadvantageous loss characteristics in multi-output operation, which will be described later. Therefore, by obtaining the AND output with clock pulse CPl,
It is possible to always take out an output signal that causes the switching transistor Tr to operate with a rest period, and the maximum value of the signal does not exceed the conduction period of CP1. This pulse output causes the next stage drive circuit 2 to
After power amplification, 51 and 252 are connected to the switching control circuit 1 through the windings 25T1 and 25T2 of the transformer 25T.
The transistors Tr, Tr4 of 91, 192 are controlled to be turned on or off. The above-mentioned operation shows that when converter outputs become multiple outputs, each output can always be stabilized by providing each with a circuit configuration after the secondary side.

Next, we will discuss the case where this device has a multi-output configuration with positive and negative power supplies.

In the case of a negative power supply configuration, by inverting the input of the error voltage amplifier 232 and configuring the reference voltage by the Zener diode ZD2 etc. on the negative voltage side, the output of the error voltage amplifier 23, as described above, is output when the input voltage is zero or When it is smaller than the predetermined value, the voltage is close to +15V, and when the input voltage becomes larger in absolute value than the predetermined output value, the output voltage of the amplifier becomes smaller, and therefore the operation of the next stage and subsequent stages is the same as the above-mentioned operation. FIG. 14 shows an overcurrent detection amplifier.

As shown in the figure, overcurrent detection amplifiers 261 and 262 connect shunt resistors 26R individually to points F and G provided on the 0V line of the valley DC output, and the voltage drop is applied to the amplifier 0A3.
,0A4. That is, amplifier 0A3 inputs the signal from the 0v line to the negative input terminal, and amplifier 0A4
inputs the signal from the 0V line to the positive input terminal. The positive terminal of amplifier 0A3 and the negative input terminal of amplifier 0A4 are connected to the terminal close to the power supply of resistor 26R, so that the output of differential amplifiers 0A3 and 0A4 is always proportional to the load current from 0V to +15V. It is composed of The output voltage of this differential amplifier is detected by Zener diodes ZD3 and ZD4 as shown in the figure, and the next stage differential amplifiers 0A5 and 0A6 are driven, and the triangular wave voltage of the pulse width conversion circuits 241 and 242 is reduced by the output. It is something.
That is, when the load current exceeds a certain value (when the Zener voltage exceeds one voltage), the next stage differential amplifiers 0A5 and 0A6 operate,
The output operates in the direction of lowering the triangular wave voltage. Therefore, the pulse width conversion circuit operates in such a direction that its output pulse width decreases, thereby shortening the conduction time of the transistors Tr3 and Tr4 of the switching control circuits 191 and 192. Therefore, the output voltage and output current become small, and this current is again detected by the shunt resistor 26R, and the above operation is repeated to perform constant current operation. Overcurrent detection amplifier 261, 2
The output of 62 is supplied to pulse width conversion circuits 241 and 242, and is also applied to a protection circuit 32 for alarm signal and AC cutoff shown in FIG. Since the output of the overcurrent detection amplifier is connected to the two points Al and A of the pulse width conversion circuits 241 and 242, the current at the two points Al and A is biased by the output stages of the overcurrent detection amplifiers 26 and 262. The triangular wave becomes lower in proportion to the load current. For example, the first
It becomes low from the state shown in FIG. 0B to the state shown in FIG. 10D.
FIG. 3 shows the protection circuit of the switching regulator.

The protection circuit 32 is for alarm signals and AC cutoff, and the output of the overcurrent detection amplifiers 26, 262 is +15V.
The output circuits 22, 222 control the output voltage when the output voltage decreases from the reference value to 0V, but as a means to further improve this operation function, when each output voltage increases from the reference value, the oscillation circuit 15 and the primary By controlling the side drive circuit 16, it becomes possible to prevent excessive voltage from being applied to the load even momentarily. That is, the error voltage amplifiers 231, 232
When the output of
It is also possible to protect the switching regulator of the present invention by operating the circuit for interrupting the clock pulses CP2 and CP3 of No. 5 to interrupt the clock pulses before the overvoltage detection circuit is activated. As described above, according to the present invention, in a multi-output switching regulator equipped with positive and negative power supplies, all the circuit configurations can be configured with the same components by simply inverting the input terminals of the error voltage amplifier and overcurrent detection amplifier. Furthermore, the oscillation circuit, alarm circuit, and protection circuit can be used in common, and therefore a multi-output switching regulator with uniform characteristics for each output, stability, and productivity can be provided.

It should be noted that the above embodiments are merely illustrative of the present invention, and it goes without saying that various changes can be made as necessary.

Scarcity

[Brief explanation of drawings]

1 to 3 are circuit configuration diagrams showing common circuit parts of a multi-output switching regulator equipped with positive and negative power supplies according to the present invention, and FIG. 4 is a circuit diagram showing a multi-output switching regulator equipped with positive and negative power supplies according to the present invention. A connection diagram showing the remaining circuit parts of the regulator, FIGS. 5 to 10 are waveform diagrams for explaining the operating characteristics of the multi-output switching regulator equipped with positive and negative power supplies according to the present invention, and FIG. 11 12 is a circuit diagram showing an example of connection of a drive circuit, FIG. 12 is a circuit diagram showing an example of connection of a pulse width conversion circuit, FIG. 13 A and B is a circuit diagram showing an example of connection of an error voltage amplifier, and FIG. Figures A and B are circuit diagrams showing examples of wiring of an overpower detection amplifier. 11: AC line direct rectification smoothing circuit, 14: converter circuit, 15: oscillation circuit, 16: primary side drive circuit, 18: converter transformer, 181, 182: double wave rectifier circuit, 19, 192: switching control circuit ,
201, 202: Smoothing circuit, 211, 212: Current detection circuit, 221: 222: Overvoltage detection circuit, 231, 23
2: Error voltage amplifier, 241, 242: Pulse width conversion circuit, 251, 252: Drive circuit, 261, 262:
Overcurrent detection amplifier, 27: Auxiliary power supply circuit, 32: Protection circuit for alarm signal and AC cutoff.

Claims (1)

[Claims] 1. A switching converter circuit, a converter transformer that boosts or steps down the output of the converter circuit and has multiple windings on the secondary side, and rectifies the output of the secondary winding of the transformer to convert positive and negative a rectifier circuit that obtains electric power, a switching control circuit that stabilizes the electric power supplied from the rectifier circuit, and a smoothing circuit that smoothes the output of the control circuit;
a current detection circuit that detects the output current of the smoothing circuit; and a power circuit system that drives the converter circuit.
a next-side drive circuit; an error voltage amplifier that compares the positive and negative DC outputs of the smoothing circuit with a reference voltage to generate a differential voltage output; and a current detection circuit that detects the current value of each DC output. an overcurrent detection amplifier that generates an overcurrent output when the current value is larger than a predetermined set value; and an overcurrent detection amplifier that receives the outputs of the amplifier and the error voltage amplifier and controls the switching according to the magnitude of the input voltage. A control circuit system includes a pulse width conversion circuit that controls the conduction period of the switching element of the circuit, and the error voltage amplifier and overcurrent detection amplifier are configured using differential amplifiers, and the primary side drive circuit and a multi-output switching device comprising positive and negative power supplies, characterized in that the clock pulse is supplied from a common oscillation circuit to the pulse width conversion circuit, and the positive and negative DC power is supplied from a common auxiliary power supply circuit to the control circuit system. regulator.