JPS59231841A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59231841A
JPS59231841A JP10815483A JP10815483A JPS59231841A JP S59231841 A JPS59231841 A JP S59231841A JP 10815483 A JP10815483 A JP 10815483A JP 10815483 A JP10815483 A JP 10815483A JP S59231841 A JPS59231841 A JP S59231841A
Authority
JP
Japan
Prior art keywords
cap
heat
chips
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10815483A
Other languages
Japanese (ja)
Inventor
Shin Nakao
中尾 伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10815483A priority Critical patent/JPS59231841A/en
Publication of JPS59231841A publication Critical patent/JPS59231841A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To unify the heat dissipating quantities of chips according to the mounting positions on a substrate by a method wherein walls for conduction paths of heat to a radiator are provided protruding between the mutual semiconductor chips of the whole from the upper inside face of a cap. CONSTITUTION:A radiator 9 is adhered 10 on a cap 7A to seal airtightly semiconductor chips 2 of the plural number of pieces equipped on a substrate 1, walls 12 to protrude between the mutual chips 2 of the whole from the upper inside face of the cap 7A are provided, and adhered 8, 13 to the substrate 1 to seal airtightly. At this time, because heat flows flowed out from the surfaces of the chips 2 are transmitted through the adhesives 8, 13, the differences of the heat transmitting distances and the heat transmitting sectional areas according to the mounting places (a), (b), (c) are reduced, heat resistances between the chips are unified, and heat resistance as the whole is also reduced. Moreover because the walls 12 are formed in one body structure with the cap, no bad influence is applied to sealing work.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は複数個の半導体テップが基板に実装され、こ
れらの半導体チップを気密封止するキャップを有する構
造の半導体装置において、各半導体チップの上記基板上
の実装位置の如何による熱放散量の不均一を小さくする
改良に関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device having a structure in which a plurality of semiconductor chips are mounted on a substrate and has a cap for hermetically sealing these semiconductor chips. This invention relates to an improvement that reduces non-uniformity in the amount of heat dissipation depending on the mounting position on the board.

〔従来技術〕[Prior art]

第1図は従来のこの種装置の一例を示す縦断面図、第2
図は第1図のロー■線での断面図である。
Figure 1 is a vertical cross-sectional view showing an example of a conventional device of this type;
The figure is a sectional view taken along the line 2 in FIG. 1.

なお、第1図は沈2図のI−I線での断面図に相当する
Note that FIG. 1 corresponds to a cross-sectional view taken along line I--I in FIG. 2.

図において、(1)は基板、(2)は基板i11の上に
装着されたフリップチップ方式の半導体チップ、(3)
はエンジニアリングチェンジのためのノ(ラド、(4)
は外部接続用ビン、(5)は熱伝導性のよい金属板、(
6)は金属板(5)を半導体チップ(2)の上面に接着
する熱伝導性の良好な接着剤、(7)は気密封止のため
のキャップ、(8)はキャップ(7)を基板filに接
着する熱伝導性のよい接着剤、(9)はヒートシンク、
Qo+はヒートシンク(9)をキャップ(7)の上面に
接着する熱伝導性のよい接着剤、(Illはキャップ(
7)内の空隙部に充填された熱伝導性のよい気体である
In the figure, (1) is a substrate, (2) is a flip-chip semiconductor chip mounted on the substrate i11, and (3)
is for engineering change (rad, (4)
is a bottle for external connection, (5) is a metal plate with good thermal conductivity, (
6) is an adhesive with good thermal conductivity that bonds the metal plate (5) to the top surface of the semiconductor chip (2), (7) is a cap for airtight sealing, and (8) is a cap that connects the cap (7) to the substrate. Adhesive with good thermal conductivity that adheres to fil, (9) is a heat sink,
Qo+ is an adhesive with good thermal conductivity that adheres the heat sink (9) to the top surface of the cap (7), (Ill is the cap (
7) is a gas with good thermal conductivity that fills the voids within.

このように構成された半導体装置では、半導体チップ(
2)で発生した熱にはテップ裏面から接着剤(6)、金
属板(5)を通り、気体(u) +キャップ(7)、接
着剤(10+ 、およびヒートシンク(9)に伝わって
外部空気中へ放散されるものと、チップ表面から基板(
1)。
In a semiconductor device configured in this way, a semiconductor chip (
The heat generated in step 2) passes through the adhesive (6) and metal plate (5) from the back of the tap, and is transmitted to the gas (U) + cap (7), adhesive (10+), and heat sink (9), and is released into the external air. What is emitted into the inside and what is emitted from the chip surface to the substrate (
1).

接着剤(8)、キャップ(7)、接着剤(10)、およ
びヒートシンク(9)を介して外部空気中へ放散される
ものとがある。半導体チップ(2゛1の裏面から逃げる
伝熱経路において接着剤(6)および金属板(5)は熱
伝導性のよい材料を用いていて接触熱抵抗もほとんど7
ぽい。
Some is dissipated into the outside air via the adhesive (8), the cap (7), the adhesive (10), and the heat sink (9). The adhesive (6) and metal plate (5) in the heat transfer path escaping from the back surface of the semiconductor chip (2゛1) are made of materials with good thermal conductivity, and the contact thermal resistance is almost 7.
Poi.

また、金属板(5)とキャップ(7)との間隙は極めて
小さくこの間は熱伝導性のよい気体囲が封入されている
ので、熱抵抗は十分小さい。さらに、キャップ(7)、
接着剤(101およびヒートシンク(9)にはいずれも
熱伝導性のよい材料を用いており、接着剤(lO)とキ
ャップ(7)およびヒートシンク(9)との接触は極め
て良好であるからこの間の熱抵抗も極めて小さい。
Further, since the gap between the metal plate (5) and the cap (7) is extremely small and a gas surrounding with good thermal conductivity is filled in this gap, the thermal resistance is sufficiently small. Furthermore, a cap (7),
The adhesive (101) and the heat sink (9) are both made of materials with good thermal conductivity, and the contact between the adhesive (101) and the cap (7) and the heat sink (9) is extremely good. Thermal resistance is also extremely low.

以上のように、半導体ナツプ(21の長面からの熱伝導
は極めて効果的に行なわれるがチップ(2)の表面から
の熱伝導に関してはチップの実装場n[によって熱抵抗
に走か生じる欠点があった。即ち例えば、半導体チップ
(21が第2図のように実装されていた場合、第2図の
半導体チップ(2iのa、bおよびCの位置に実装され
たものはそれぞれナツプ(2)で発生した熱か基&(1
jを通ってキャップ(7)と基板(liとの接滝部分に
到達する筐での伝熱距岬および伝熱断面積かAなる。従
って8の位置Gこ実装されたチッソとbの位置に実装さ
れたテップ甘たけCの位置に誤装されたチップとの間に
熱抵抗の差が生じ特にCの位置に実装されたチップの熱
抵抗が大きくなりチップ間の熱抵抗にばらつきが生じる
欠点かあった。
As mentioned above, heat conduction from the long surface of the semiconductor napkin (21) is extremely effective; For example, if the semiconductor chip (21) is mounted as shown in Fig. 2, the semiconductor chips (2i) in Fig. ) The heat generated at &(1
The heat transfer distance cape and heat transfer cross-sectional area of the casing that passes through j and reaches the contact area between the cap (7) and the board (li) is A.Therefore, the position G of 8 is the position of the mounted Nisso and b. There is a difference in thermal resistance between the chip mounted in the Amatake position and the chip incorrectly installed in the C position, and the thermal resistance of the chip mounted in the C position becomes particularly large, causing variations in thermal resistance between chips. There were some drawbacks.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するた
めになされたもので実装された半導体チップの間にも基
板の周辺と同様にキャップと基板とを接合し、新たな伝
熱経路を設けることによって、それぞれのチップに対す
る均一な熱伝導を可能にし、チップ間の熱抵抗のばらつ
きをなくすような半導体装置を提供するものである。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and a new heat transfer path is provided between the mounted semiconductor chips by bonding the cap and the substrate in the same way as the periphery of the substrate. This provides a semiconductor device that enables uniform heat conduction to each chip and eliminates variations in thermal resistance between chips.

〔発明の実施例〕[Embodiments of the invention]

第3図はこの発明の一実施例を示す縦断面図、第4図は
>g 3図の1シ−lv株での断面図である。なお、第
3図は第4図のIII −III線での断面図に相当す
る。図において、薦1図、第2図の従来例と同一符号は
同等部分を示す。(7A)は半導体チップ(2)を気密
封止するンこめのキャップ、(12)はチップ間で均一
な熱伝;Jを得るためにぜ一1ソゲ(7人)に設りた壁
であり、この壁(121は基鈑(11と熱伝導性のよい
接着剤(13)で接脇されている。接着剤(13)はプ
ロセスを容易にするために接着剤(Sjと同じものを用
いるのが望ましい。
FIG. 3 is a longitudinal cross-sectional view showing an embodiment of the present invention, and FIG. 4 is a cross-sectional view of the 1S-LV strain of FIG. Note that FIG. 3 corresponds to a cross-sectional view taken along the line III--III in FIG. 4. In the figure, the same reference numerals as in the conventional example shown in Figures 1 and 2 indicate equivalent parts. (7A) is a cap that airtightly seals the semiconductor chip (2), and (12) is a wall that was installed in the first place (7 people) in order to obtain uniform heat transfer between the chips. This wall (121) is attached to the base plate (11) with an adhesive (13) with good thermal conductivity.The adhesive (13) is the same as the adhesive (Sj) to facilitate the process. It is desirable to use

第4図において、α4)はエンジニアリングチェンジし
た導線である。
In FIG. 4, α4) is a conducting wire that has undergone engineering changes.

この実施例のような構造にした場合、半導体チップ(2
)の表面から伝えられる熱流は接着剤(8)を介してキ
ャップ(′7A)に伝導するだけでなく、接着剤Oal
を介しても伝熱する。この結果、第4図に示した半導体
チップ(2)の実装場所a、bおよびCによる伝熱距離
および伝熱断面積の差が小さくなり、チップ間の熱抵抗
の均一性が得られるだけでなく、全体としての熱抵抗の
低下にもなる。
If the structure is as shown in this example, the semiconductor chip (2
) is not only conducted to the cap ('7A) through the adhesive (8), but also through the adhesive Oal
Heat is also transferred through As a result, the differences in heat transfer distance and heat transfer cross section between the mounting locations a, b, and C of the semiconductor chip (2) shown in FIG. This also reduces the overall thermal resistance.

また、第4図に示すように、伝熱のための壁(電りはキ
ャップ(7A)の周辺部分とつながっておらず、壁(I
2)同士も接続されていないのでエンジニアリングチェ
ンジをする場合にも何ら問題はない。
In addition, as shown in Figure 4, the wall (electricity) for heat transfer is not connected to the peripheral part of the cap (7A), and the wall (I
2) Since they are not connected to each other, there is no problem when making engineering changes.

さらに、壁(12)はキャップ(7A)と一体になって
いるのでチップ数が増加しても封止の工程数が増すこと
なく、一度に封止できる。
Furthermore, since the wall (12) is integrated with the cap (7A), even if the number of chips increases, the number of sealing steps does not increase, and the chips can be sealed all at once.

なお、上記実施例ではチップを9個塔載した場合につい
て示したが、このチップ数に制限はなく、何個塔載され
ていても同様の効果が得られる。また、第4図のチップ
間に対する均一な熱伝導を得るために設けた種口は第5
図に平面断面図を示す他の実施例における壁(12A)
のようにチップ周辺を囲む形で設けても同じ効果が得ら
れる。
In the above embodiment, the case where nine chips are mounted is shown, but there is no limit to the number of chips, and the same effect can be obtained no matter how many chips are mounted. In addition, the seed opening provided to obtain uniform heat conduction between the chips in Fig. 4 is the 5th one.
Wall (12A) in another embodiment whose plan sectional view is shown in the figure
The same effect can be obtained even if it is provided to surround the periphery of the chip.

さらに、エンジニアリングチェンジを必要としく必要は
なく第6図に平面断面図を示す更に他の実施例における
壁(12B)のようにすべて接続させることも可能であ
る。
Further, it is also possible to connect all the walls (12B) in still another embodiment, which does not require engineering changes and is shown in a cross-sectional plan view in FIG.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明になる半導体装置では基
板上に装着された複数個の半導体チップを気密封止する
キャップの上に放熱装置を設けるとともに、そのキャッ
プの上向面からすべての半導体チップの相互間に突出す
る壁を設けたので半導体チップの装着部位の如何に拘ら
ず一様な放熱が可能となる。しかも壁はキャップと一体
構造であるので封止作業に何等悪影響を及ぼさない。
As explained above, in the semiconductor device of the present invention, a heat dissipation device is provided on the cap that hermetically seals a plurality of semiconductor chips mounted on a substrate, and all the semiconductor chips are disposed from the upper surface of the cap. Since a protruding wall is provided between the two, uniform heat dissipation is possible regardless of where the semiconductor chip is mounted. Furthermore, since the wall is integrally constructed with the cap, it does not have any adverse effect on the sealing operation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来装置の一例を示す縦断面図、第2図は第1
図の■−■線での平面断面図、第3図はこの発明の一実
施例を示す縦断面図、第4図は第3図のIV−IV線で
の平面断面図、第5図はこの発明の他の実施例の平面断
面図、第6図はこの発明の更に他の実施例の平面断面図
である。 図において、(1)は基板、(2)は半導体チップ、(
”A)+ (7B)、 (′70)はキャップ、(8)
は接着剤、(9)はヒートシンク(放熱装置)、(10
)は接着剤、(121、(12A) + (12B)は
壁である。 なお、図中同一符号は同一または相当部分を示す。 代理人 大岩増雄 第1図 第2図 第31′A 第4図
Fig. 1 is a vertical sectional view showing an example of a conventional device, and Fig. 2 is a longitudinal sectional view showing an example of a conventional device.
3 is a longitudinal sectional view showing an embodiment of the present invention, FIG. 4 is a sectional plan view taken along line IV-IV in FIG. 3, and FIG. FIG. 6 is a plan sectional view of still another embodiment of the present invention. In the figure, (1) is a substrate, (2) is a semiconductor chip, (
"A) + (7B), ('70) is the cap, (8)
is adhesive, (9) is a heat sink (heat dissipation device), (10
) is the adhesive, and (121, (12A) + (12B) is the wall. The same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 31'A 4 figure

Claims (3)

【特許請求の範囲】[Claims] (1)複数個の半導体チップが装着された基扱上に、上
記半導体チップを気密に封止するように取りつけられた
キャップと、このキャップの上(こ設けられ上記半導体
チップから発生ずる熱を外部に放散させる放熱装置とを
有するものにおいて、−上記キャップの上向面から」二
記すべての半導体チップの相互間に突出し上記熱の上記
放熱装置への←伝導路を構成する壁を備えたことを特徴
とする半導体装fn。
(1) A cap attached to a substrate on which a plurality of semiconductor chips are mounted so as to hermetically seal the semiconductor chips; and a heat dissipation device for dissipating the heat to the outside, - a wall protruding from the upper surface of the cap between all the semiconductor chips and forming a conduction path for the heat to the heat dissipation device; A semiconductor device fn characterized by the following.
(2)  壁はキャップ内側面にはつながることなく各
半導体チップの西側面を囲むように形成されたことを特
徴とする特1r請求の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the wall is formed so as to surround the west side of each semiconductor chip without being connected to the inner side of the cap.
(3)壁はキャップ内側面につながり上記キャップ内を
格子状に区切るように構成され、これらの各格子内4こ
各半導体チップが収容されるようにしたことを特徴とす
る特許請求の範囲第1項記載の半導体装置。
(3) The wall is connected to the inner surface of the cap and is configured to divide the inside of the cap into a grid, and each of the grids accommodates four semiconductor chips. The semiconductor device according to item 1.
JP10815483A 1983-06-14 1983-06-14 Semiconductor device Pending JPS59231841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10815483A JPS59231841A (en) 1983-06-14 1983-06-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10815483A JPS59231841A (en) 1983-06-14 1983-06-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59231841A true JPS59231841A (en) 1984-12-26

Family

ID=14477314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10815483A Pending JPS59231841A (en) 1983-06-14 1983-06-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59231841A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572053A (en) * 1987-11-25 1996-11-05 Fujitsu Limited Dynamic random access memory cell having a stacked capacitor
US5705850A (en) * 1993-09-20 1998-01-06 Hitachi, Ltd. Semiconductor module
JP2013080742A (en) * 2011-09-30 2013-05-02 Fujitsu Ltd Semiconductor package, wiring board unit, and electronic apparatus
JP2016146427A (en) * 2015-02-09 2016-08-12 株式会社ジェイデバイス Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572053A (en) * 1987-11-25 1996-11-05 Fujitsu Limited Dynamic random access memory cell having a stacked capacitor
US6046468A (en) * 1987-11-25 2000-04-04 Fujitsu Limited Dynamic random access memory device and method for producing the same
US6114721A (en) * 1987-11-25 2000-09-05 Fujitsu Limited Dynamic random access memory device and method for producing the same
US5705850A (en) * 1993-09-20 1998-01-06 Hitachi, Ltd. Semiconductor module
JP2013080742A (en) * 2011-09-30 2013-05-02 Fujitsu Ltd Semiconductor package, wiring board unit, and electronic apparatus
JP2016146427A (en) * 2015-02-09 2016-08-12 株式会社ジェイデバイス Semiconductor device
CN111446217A (en) * 2015-02-09 2020-07-24 株式会社吉帝伟士 Semiconductor device with a plurality of semiconductor chips
US11488886B2 (en) 2015-02-09 2022-11-01 Amkor Technology Japan, Inc. Semiconductor device
CN111446217B (en) * 2015-02-09 2024-02-09 安靠科技日本公司 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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