JPS59230389A - Bus connecting circuit - Google Patents

Abstract

PURPOSE:To attain ease of large scale circuit integration by adding a data transmission/reception function in the circuit so as to transmit and receive data with a multiplex line and also forming the required operation timing from an externally designated condition and a basic clock. CONSTITUTION:The data is received in the timing LTO from a multiplex data on a signal line 7A-1 by a register 11. Speed converting circuits 12-1-12-4 fetch the data in the register 11 in the timings of LT1-LT4 and circulate the fetched data in the transfer speed of a bus 4a. Tri-state elements 13-1-13-4 switch a gate in the timings of OP1-OP4 respectively and transmit the data to a specific time slot location on the bus 4a. A line state detecting circuti 14 forms a status signal by taking the data in the register 11 as a reference and transmits the data onto a bus 4b via a speed converting circuit 15-i and a tri-state element 16-i. The timing forming circuit 21 forms the timings LT1-LT4 and an OP5 according to information PHN, BRT designated externally, OP1-OP4 by BRT and TSN and forms LT5 from the three sets of information.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to the configuration of a bus connection circuit within a digital exchange.

BACKGROUND OF THE INVENTION One of the conventional switch configuration methods is a so-called function distribution configuration in which many of the functions required of the switch are distributed to line support units provided for the lines to be accommodated. An example of a functionally distributed switch is shown in FIG.

In FIG. 1, 1 is an exchange, 2 is a line correspondence section that accommodates a line, and 4a is a bus that transfers data from the line correspondence section.
4b is a bus for transferring signals from the line corresponding section (a signal representing the state of the line and is called a status signal), 4C is a bus for transferring data to the line corresponding section, and 4d is for controlling signals sent to the line. A bus 5 for transferring signals (line control signals) to a line corresponding section is a line for transmitting and receiving data to and from a terminal, and is composed of an up line 5m and a down line 5b. In FIG. 1, communication between a terminal connected to line 5 and a terminal connected to line 5-1 is performed as follows. The line handling unit 2 receives data from the line 5a, creates a signal (status signal) representing the line status (communication status such as call origination, disconnection, etc.) based on the received data, and then sends the data and status signal to the respective buses. It is sent to the designated time slot on 4m and 4b. Common part 3 is data on buses 4m and 4b.

Based on the status signal, the time slot on the path 4C to which the other line to be connected is assigned is determined, and the time slot on the bus 4a is determined.
The data received from the line 5a is sent to the other line time slot on the bus 4C. The line corresponding section 2-1 selects the line 5 from the time slot allocated on the path 4C.
The data from a is extracted and sent to the downlink 5b-1. Conversely, data from uplink 5a-1 is also sent to partner downlink 5b in the same way, and communication is thus performed between the terminals on line 5 and the terminals on line 5-1.

As shown in FIG.
A signal processing circuit 7 that processes data corresponding to the line and data and status signals from the line are transferred to buses 4a and 4, respectively.
A circuit (hereinafter referred to as a bus connection circuit) 8 and a bus connection circuit that transmits data and line control signals to specified time slots on buses 4c and 4d and receives data and line control signals from specified time slots on buses 4c and 4d. 8A. The line support section 2 in FIG. 2 accommodates a so-called non-multiplex line that transmits data for only one terminal.

In FIG. 2, data from the line 5a is converted by a code conversion circuit 6 from the code format on the line to the code format processed within the switching device. The code-converted data is input to the bus connection circuit 8 after so-called bit synchronization and envelope synchronization is established by the synchronization circuit 7. The bus connection circuit 8 creates a status signal based on the input data, and then transfers the data and status signal to the buses 4a and 4, respectively.
It is sent to the time slot above b. The bus connection circuit 8 also receives data and line control signals from the buses 4c and 4d, respectively, and selects and synchronizes the received data from the bus 4c or a specific signal (for example, a line blockage signal) according to the instructions of the line control signals. The signal is sent to circuit 7. The synchronization circuit 7 adds synchronization bits to the received signal from the bus connection circuit 8 and sends it to the code conversion circuit 6, and the code conversion circuit 6 converts the sign of the signal to the code on the line and sends it to the line 5b. .

The clock supply circuit 8A supplies the bus connection circuit 8 with a necessary lock depending on the data transmission speed on the lines 5a and 5b and the time slot on the bus through which the bus connection circuit 8 transfers data, status signals 9 and line control signals. do. The bus connection circuit 8 operates according to the clock supplied from the clock supply circuit 8A.

On the other hand, a multiplex line 5 that multiplex transmits data from multiple terminals
Conventionally, the two line support sections accommodating A and 5B are code conversion circuits 6. A synchronization circuit 7A synchronizes multiplexed data, and a demultiplexing circuit φ demultiplexes received data from the synchronization circuit 7A.

It is composed of a bus connection circuit 8 and a clock supply circuit 8B. In FIG. 3, the received signal from line 5A is transmitted to code conversion circuit 6. After passing through the synchronization circuit 7A and the signal line 7A-1, the data is separated into multiplexed terminal data by the demultiplexing circuit 9. The separated data is input to a bus connection circuit 8 installed corresponding to the terminal.

The bus connection circuit 8 sends input data and status signals onto the buses 4m and 4b, respectively, as in FIG. 2, and conversely sends data from the buses 4c and 4d.

It receives the line control signal, creates output information to the line side, and sends it to the demultiplexer circuit 9. The demultiplexing circuit 9 multiplexes the information received from each bus connection circuit 8, and the multiplexed information is sent to the signal line 7A-2 and the synchronization circuit 7A.

After passing through the code conversion circuit 6, it is sent out onto the line 5B.

Each bus connection circuit 8 operates according to the clock supplied from the clock supply circuit 8B.

Prior Art and Problems In the conventional bus connection circuit 8, when accommodating multiple lines, a demultiplexing circuit 9 and a number of bus connection circuits corresponding to the number of terminals multiplexed on the multiple lines are required, which is uneconomical. In addition, the bus connection circuit is made into an LSI in order to receive the data transmission/reception speed between the lines and the number of clocks depending on the time slots on each bus 4a to 4d from the clock supply circuit. In some cases, a so-called pin neck occurs.

Purpose of the Invention The present invention adds a function for transmitting and receiving data to and from multiple lines to the bus connection circuit in the exchange line correspondence section, thereby increasing the economic efficiency of accommodating multiple lines, and also improving the efficiency of the externally specified conditions and conditions. By creating the necessary operation timing from the basic clock, pin bottlenecks during LSI integration can be eliminated, and a highly versatile bus connection circuit that can be used under various conditions is provided.

Examples of the invention FIG. 4 shows the configuration of a bus connection circuit according to an embodiment of the present invention.

In FIG. 4, 10 is a bus connection circuit, and 11 is a signal line 7.
Registers 12-1 to 12-4 receive the multiplexed data from A-1 at timing LTO and temporarily store it, and registers 12-1 to 12-4 receive the multiplexed data from A-1 at timing LTO.
T1 to LT4) receive the data in register 11,
Speed conversion circuit that increases the speed up to the transfer speed of bus 4a, 1
1 to 13-4 are tri-state elements that open and close at the timings (OP1 to 0P4) given by the timing generation circuit 21, and 14 is a tri-state element that determines the line status (communication status such as call origination, disconnection, etc.) based on the data in the register 11. ) representing the signal (
For example, a level detection circuit that detects a signal level is applied. 15-1 to 15-4 indicate timings (LT1 to LT1 to
LT4) and increases the speed to the transfer speed on the bus 4b; 16-1 to 16-4 are tri-state elements that open and close at the timings given to each (OP1 to 0P4); 17 is a timing generation circuit 21 A register 18 receives the line control signal from the bus 4d and temporarily stores it at a timing given by the timing generation circuit 21. A register 19 receives data from the register 17. A signal to be sent to the line is created using the data and the line control signal from the register 18.

For example, a selection circuit is applied to the data transmission control circuit for transmission. 20 is a tri-state element that opens and closes at a given timing OP5; 21 is information given from the outside, such as BRT (pair rate), PHN (information representing the phase on multiplexed data), TSN (information representing the time slot on the bus); ) is a timing generation circuit that generates the necessary timing within the bus connection circuit according to each information. In FIG. 4, the register 11 is connected to the signal line 7A-
Data is received from the multiplexed data on 1 at timing LTO. The speed conversion circuits 12-1 to 12-4 are constituted by shift registers, and each takes in the data in the register 11 at timings LT1 to LT4, and circulates the taken data at the transfer speed of the bus 4a. Tri-state elements 13-1 to 13-4 have timings OP1 to OP4, respectively.
The gate is opened and closed at , and data is sent to a specific time slot position on the bus 4a. The line state detection circuit 14 creates a status signal based on the data in the register 11.

The speed conversion circuits 15-1 to 15-4 take in the status signals from the line state detection circuit 14 at timings LT1 to LT4, respectively, and circulate them at the transfer speed of the bus 4b. Tri-state elements 16-1 to 16-4
sends a status signal to a specific time slot position on the bus 4b by opening and closing the gates at timings OP1 to OP4, respectively.

For example, the signal lines 7A-1, 7A-2 have a multi-frame format multiplexed signal consisting of 20 time slots, and the transfer rate on the buses 4a to 4d is the signal lines 7A-1, 7A-2.
If the transfer rate is m times the transfer rate on A-2, the link created by the timing creation circuit 21 will be as follows. The timing generation circuit 21 generates timings LT1 to LT4 and OF2 according to externally specified information PHN and BRT, and timings OP1 to OF2 according to BRT and TSN, as well as PHN.

Create LT5 according to BRT, TSN. Here, PHN specifies time slots within the multiframe on signal lines 7A-1 and 7A-2 (when PHN is -0, time slots 0, 5, 10, and 15 are designated as PHN).
When N = 1, time slots 1, 6, 11.1
6, time slots 2 and 7 when PHN = 2
, 12, 17, when PHN -5, time slots 6, 8, 1, 1B, when PHN = 4, specify time slots) 4, 9, 14, 19) information, B
RT specifies how to use time slots in response to PHN (for example, time slots when BRT = 00 for PHN = O) 0, 5, 10, and 15 are used for data transmission of different terminals, and when BRT = 1 Time slots 0, 10 are used for data transmission of one terminal, time slots 5, 15 are used for data transmission of another terminal, and when BRT = 2, time slots 0, 5 . io, 15 are all used for data transmission of one terminal, and when BRT = 5, 20 time slots from 0 to 19 are used for data transmission of one terminal. ) information, TSN is bus 4
Data between h, 4b, 4e, and 4d.

This is information that specifies the transmission/reception timing of status signals or line control signals.

FIGS. 5 to 8 show timing relationships when BRT is changed from 0 to 3 when PHN -0 and TSN = n.

In this embodiment, a case will be exemplified in which the timings of the buses 4a to 4d are the same. An analogy can be easily made for cases where the timing is different. FIG. 5 shows the timing relationship when BRT=0, and the circuit of FIG. 10 operates as follows using the timing of FIG. 5. Speed conversion circuits 12-1 to 12-4 each take in data from time slots 0, 5, 10, and 15 on signal line 7A-1, and circulate the taken data at the transfer rate on bus 4a. Tri-state elements 13-1 to 13-4 are located at time slot positions n, n+1 . . . on bus 4a, respectively. n+2
．． The gate is opened at a timing corresponding to n+3, and data is sent onto the bus 4a. The line state detection circuit 14 monitors the data of each time slot 0.5, 10, and 15, creates a status signal, and speed conversion circuit 15-1.
, 15-2, 15-3° and 15-4. Speed conversion circuits 15-1 to 15-4 are speed conversion circuits 12-1
〜Similar to 12-4, time slot n on bus 4b
, n+1. n+2. Sends a status signal to n+3.

The register 17 sets timing LT5 (time slot on bus 4c within time slot 00 hours on signal line 7A-1) n, time slot on bus 4C within time slot 50 time on signal line 7A-1) n+1, Signal line 7A
time slot on path 4C) n+2 within the time of time slot 10 on signal line 7A-1, and time slot on path 4C) n+3 within the time of time slot 15 on signal line 7A-1.
The data is extracted from the path 4C using the timing specified by each of them.

The register 18 takes out the line control signal from the bus 4d using timing LT5. The data transmission control circuit 19 is
According to the instructions of the line control signal in the register 18, information (for example, the data in the register 17 during communication, a signal indicating it when communication is possible during non-communication, a signal indicating it when communication is disabled) is transferred to the signal line. 7A-2 data transmission rate. The sending information from the data sending control circuit 19 is
Through the gate 20 opened at timing OP5, time slots 0, 5, 10, 15 on the signal line 7A-2
will be sent to.

FIG. 6 shows the timing relationship when BRT=1, and the rebus connection circuit operates as follows.

Speed conversion circuits 12-1 and 12-2 are connected to time slots 0 and 10 . on signal line 7A-1. , and 5 and 10, and circulate the captured data at the transfer speed on the bus 4a. Tri-state element 13-1, 1
3-2 open their gates at timings corresponding to time slots n and n+1 on the bus 4a, respectively, and the data is transferred to the bus 4 &
sent upwards. The line state detection circuit 14 creates status signals for each of the data in time slot 0.10 and the data in time slot 5.10, and supplies them to speed conversion circuits 15-1 and 15-2. Speed conversion circuit 1
5-1, 15-2 and tristate element 16-1
, 16-2 send status signals to time slots n and n+1, respectively, on bus 4b. The tri-state elements 15-3, 13-4, 16-3, 16-4 include
Speed conversion circuits 12-3, 12-4, and 15-3 because the timing to open the gates is not given.

Data and status signals from 15-4 are on buses 4m and 4b.
Not sent up.

Register 17 is timing LT5 ('M line 7 A
-1 within the time slots 0 and 100 hours on the bus 4c) n, and the time slots on the bus 4o within the time slots 5 and 15 on the signal line 7A-1 (timings to specify respectively) The data is taken in from the bus 4c using. The register 18 takes in the line control signal from the bus 4d using timing LT5. The operation of the data transmission control circuit 19 and the gate 20 is as follows.
The operation is similar to that in the case of FIG.

FIG. 7 shows the timing relationship when BRT=2, and the bus connection circuit operates as follows.

The speed conversion circuit 12-1 takes in data from time slots 0, 5, 10, and 15 on the signal line 7-1,
It is sent via tri-state element 13-1 to time slot (n) on bus 4. The line state detection circuit 14 detects time slots 0, 5, 10, 1 on the signal line 7A-1.
Create a status signal for the received data from 5,
It is supplied to the speed conversion circuit 15-1. The status signal is transmitted through the speed conversion circuit 15-1 and the tri-state element 16-1.
to time slot n on bus 4b.

In this case, the tristate elements 13-2 to 16-4 and 16-2 to 16-4 are not given timing to open their gates, so the speed conversion circuits 12-2, 12-3
, 12-4, 15-2, 15-3. Data and status signals from 15-4 are not sent onto buses 4m and 4b.

The register 17 takes in data from the bus 4C using timing LT5 (timing for specifying time slot n on the bus 4C within each time slot 0, 5, 10, and 15 on the signal line 7A-1). .

The register takes in the line control signal from the bus 4d using timing LT5. The operations of data sending control circuit 19 and gate 20 are similar to those in the case of FIG.

FIG. 8 shows the timing relationship when BRT=5, and the bus connection circuit operates as follows.

The speed conversion circuit 12-1 converts signals from 0 to 19 on the signal line 7A-1.
The data is taken in from all time slots up to and sent to the time slot n on the bus 4 & via the tri-state element 16-1. The line state detection circuit 14 monitors the data of all time slots as data from one terminal, creates a status signal, and supplies it to the speed conversion circuit 15-1. The status signal is sent to the time slot ()n on the bus 4b via the speed conversion circuit 15-1 and the current state element 16-1. In this case, tristate element 1
Since gate opening timing is not given to 3-2 to 16-4 and 16-2 to 16-4, data and No status signals are sent on buses 4a, 4b.

FIG. 9 shows an example in which an in-exchange line support section for accommodating multiplexed lines is configured using the bus connection circuit 10 shown in FIG. 4. In FIG. 9, five bus connection circuits 10 are connected to each P
The data on the signal line 7A-1 specified by HN is received, and the data received from the bus 4a is sent to the signal line 7A-2.
Send to. The configuration of the line support section shown in FIG.
This is a general-purpose configuration that does not depend on how the time slots on the signal line specified by the information are used.

Further, the multiplexing/demultiplexing circuit required in the conventional configuration shown in FIG. 3 is not required, and the number of required bus connection circuits can also be eliminated.

The path connection circuit shown in Fig. 4 operates by autonomously creating a necessary lock from the basic clock by simply specifying a few operating conditions (BRT, PHN, TSN in this example). Unlike conventional circuits in which all of the circuits are supplied externally, bottle necks do not occur when integrated into an LSI.

An in-exchange line support section for accommodating non-multiplexed lines can also be configured as shown in FIG. 10 using the bus connection circuit 2C of the present invention.

As described in detail of the invention, by using the bus connection circuit of the present invention to configure an exchange line support section that accommodates multiple lines, a demultiplexing circuit is not required and the number of necessary bus connection circuits is reduced. It is economical because it can be

In addition, the bus connection circuit of the present invention has versatility (extreme ) Line support section, 2C... It has many lines accommodating non-multiplexed lines, has a small number of input signals, and is suitable for LSI implementation.

[Brief explanation of the drawing]

Fig. 1 shows the configuration of a conventional exchange with a distributed function configuration, Figs. 2 and 3 show the configuration of a conventional exchange line corresponding section, Fig. 4 shows the bus connection circuit of the present invention, and Figs. 5 to 8 show the bus connection. The circuit timing diagrams of FIGS. 9 and 10 are examples of the configuration of an exchange line corresponding section using the bus connection circuit of the present invention, respectively. 1... Exchange, 2... Line support section, 3... Common section, 4°4*, 4b, 4a, 4d-' bus, 5, 5a, 5
b, 5A, 5B... line, 6... code conversion circuit, 7
...Signal processing circuit, 7A...Synchronization circuit, 7A-1,
7A-2...Signal line, 8...Bus connection circuit, 8A,
8B... Clock supply circuit, 9... Demultiplexing circuit,
10... Bus connection circuit, 11... Register, 12-
1 to 12-4...speed conversion circuit, 13-1 to 16-4
... Tri-state element, 14... Line state detection circuit, 15-1 to 15-4... Speed conversion circuit, 16-1
~16-4... Tri-state element, 17, 1B.
...Register, 19...Data transmission control circuit, 20.
... Tri-state element, 21... Timing generation circuit, 2B... Accommodates multiple lines ■ Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Patent attorney Gobe Tamamushi (3 others)

Claims (1)

[Scope of Claims] A line support unit that accommodates a line and includes a code conversion circuit, a signal processing circuit, and a bus connection circuit that transmits, receives, and processes information to and from the line; A common bus that transmits and receives information to and from the exchange device using time slots assigned to each bus, and a common bus that exchanges information by shifting the time slot position of the information on the bus. In the bus connection circuit of the equipment line correspondence section, which is composed of a timing generation circuit that receives and temporarily stores input multiplexed data at the timing given from the timing generation circuit; and a register of the first brother that receives and temporarily stores the input multiplexed data at the timing given from the timing generation circuit; and a register that takes in the data in the first register at the timing given from the timing generation circuit. , a circuit that circulates the captured data at the transfer speed of the data transfer bus, converts the speed, and sends the speed-converted data to a specific time slot position of the data transfer bus; a line state detection circuit that generates a status signal representing a line state based on data in the first register; and a line state detection circuit that receives a status signal from the line state detection circuit at a timing given by the timing generation circuit; A circuit that circulates the status signal at the transfer speed of the status signal transfer bus, converts the speed, and sends the speed-converted status signal to a specific time slot position of the status signal transfer path, and at the timing given by the timing generation circuit. , a second register that receives data from the data transfer bus and temporarily stores it, and a third register that receives and temporarily stores the line control signal from the line control signal transfer bus at the timing given from the timing generation circuit. , a data transmission control circuit that determines and transmits data to be transmitted to the line based on the received data from the second register and the line control signal instruction from the sixth register at the timing given by the timing generation circuit; A path connection circuit characterized by comprising: