JPS59229847A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59229847A
JPS59229847A JP10522783A JP10522783A JPS59229847A JP S59229847 A JPS59229847 A JP S59229847A JP 10522783 A JP10522783 A JP 10522783A JP 10522783 A JP10522783 A JP 10522783A JP S59229847 A JPS59229847 A JP S59229847A
Authority
JP
Japan
Prior art keywords
case
circuit
allowable temperature
package
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10522783A
Other languages
Japanese (ja)
Inventor
Tsuneto Sekiya
関谷 恒人
Osamu Matsuura
修 松浦
Shoichi Furuhata
古畑 昌一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP10522783A priority Critical patent/JPS59229847A/en
Publication of JPS59229847A publication Critical patent/JPS59229847A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Abstract

PURPOSE:To enable to integrally form a module without decreasing the using efficiency by containing an accessory circuit such as a drive circuit having a circuit element which includes a lower allowable temperature than the allowable temperature of a semiconductor element, and providing means for integrally coupling a package. CONSTITUTION:A resin case 1 for containing a power transistor and a resin case 2 for containing an accessory circuit are associated by engaging a recess 3 with a projection 4. An accessory circuit is connected to a power transistor by connecting a metal terminal 5 exposed on the surface of the case 1, i.e., terminals of emitter, base and collector to a metal terminal 6 of the cases via leads. Since the case 1 does not contain a capacitor having low allowable temperature, it can be tested at a high temperature, and when the case 2 contains a circuit element having low allowable temperature is tested at the low temperature, and then associated therewith.

Description

【発明の詳細な説明】 発明の属する技術分野 どの半導体素子とその駆動用回路とを備えた半導体装置
である。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor device including a semiconductor element and a driving circuit thereof.

〔従来技術とその問題点〕[Prior art and its problems]

複数の半導体素子および他の回路素子からなるシ“ 半導体装置をモ曾ニール化する傾向が強くなっている。 A system consisting of multiple semiconductor elements and other circuit elements There is a growing trend toward monolithic semiconductor devices.

トランジスタ、サイリスタなどと従来は別個のプリント
板などに設けられたその駆動回路、保獲回路などを、同
一パッケージに収納してモジュールにすることも当然考
えられるが、この場合、次のような問題が存在する。す
なわち、パワートランジスタを例にとれば半導体素子と
しての耐熱性は150υにもかかわらず、例えばスナバ
回路のような保護用回路はコンデンサを含み、その耐熱
性は100℃前後である。このため同一パッケージに収
納すれば全体の保証温度を下げねばならず、素子を含む
半導体装置を許容温度の高い半導体素子の使用効率を下
げることなく、一体にモジュ一本考−案は、出力用半導
体素子を収容したノくツケージと、その半導体素子の許
容温度より低G)許容温度を有する回路素子を含む駆動
回路などの付属回路を収容したパッケージと、両ノくツ
ケージを一体tこ結合するための手段を備えることによ
って上記の目的を達成する。
Naturally, it is conceivable that transistors, thyristors, etc. and their drive circuits, capture circuits, etc., which were conventionally provided on separate printed boards, could be housed in the same package to form a module, but in this case, the following problems would arise: exists. That is, taking a power transistor as an example, although the heat resistance as a semiconductor element is 150υ, a protection circuit such as a snubber circuit includes a capacitor, and its heat resistance is around 100°C. For this reason, if they are housed in the same package, the overall guaranteed temperature must be lowered, and the idea is to integrate a single module into one module without reducing the efficiency of using semiconductor devices that have a high allowable temperature. A socket cage housing a semiconductor element, a package housing an accessory circuit such as a drive circuit including a circuit element having a lower allowable temperature (G) than the allowable temperature of the semiconductor element, and both socket cages are integrally coupled together. The above objective is achieved by providing means for.

一体に結合するための手段としては、一方のノくツケー
ジに設けられた凸部と他方のノ(ツケージに設けられた
その凸部に嵌合する凹部、ある(t)(ま一方のパッケ
ージの貫通孔を通って他方の)くツケー第1図に示した
パワートランジスタを収容した樹脂ケース1と付属回路
を収容した樹脂ケース2は、ケースlに設けられた凹部
3にケース2に設けられた凸部4を嵌合させることによ
って第2図に示すように組み合わせられる。付属回路と
ノクワートランジスタの接続は、樹脂ケース1の表面に
露出している金属端子5、すなわちエミッタ、ペース、
コレクタ各端子と樹脂ケースの金属端子6と導線によっ
て接続することによって行われる。
As a means for integrally joining, there is a convex part provided on one package and a concave part fitted to the convex part provided on the other package. The resin case 1 housing the power transistor shown in FIG. By fitting the protrusions 4, they are combined as shown in FIG. 2.The connection between the attached circuit and the knocker transistor is made through the metal terminals 5 exposed on the surface of the resin case 1, that is, the emitter, paste,
This is done by connecting each terminal of the collector to the metal terminal 6 of the resin case using a conducting wire.

樹脂ケースlは許容温度の低いコンデンサ等を収容して
いないため高い温度で試験でき、許容温度の低い回路素
子を収容した樹脂ケース2は低い温度で試験した上で組
み合わすことができる。このようにパワートランジスタ
と付属回路を別個に試験して組み合わせるので製造歩留
り上有利であり、かつ組み合わせられた装置の信頼性が
高い。また樹脂ケース1の方のみ温度上昇を許容する設
計とし、例えば耐熱性の高い樹脂を使用すればよく、パ
ワートランジスタを高温で作動できるため素子の使用効
率も向上する。
The resin case 1 can be tested at a high temperature because it does not contain a capacitor or the like with a low allowable temperature, and the resin case 2 containing circuit elements with a low allowable temperature can be tested at a low temperature and then combined. Since the power transistor and the attached circuit are tested separately and combined in this way, it is advantageous in terms of manufacturing yield, and the reliability of the combined device is high. Further, only the resin case 1 is designed to allow a temperature rise, for example, a resin with high heat resistance may be used, and since the power transistor can be operated at high temperature, the usage efficiency of the element is also improved.

第1図、第2図に示す実施例では付属回路とノくワート
ランジスタの接続は樹脂ケース外の配線で行われる。こ
の場合配線の長さ、配線のパターンによっては固有振動
現象を生ずることがある。第3図はそのような配線を不
要にしたもので、パワートランジスタを収容した本体側
の樹脂ケース1には金属製の開口スリット部7が埋め込
まれでおり、付属回路の樹脂ケース2にはそのスリット
部7に嵌着できる金属突出部8が設けられている。
In the embodiment shown in FIGS. 1 and 2, the connection between the accessory circuit and the power transistor is made by wiring outside the resin case. In this case, a natural vibration phenomenon may occur depending on the length of the wiring and the pattern of the wiring. Figure 3 shows a model that eliminates the need for such wiring; a metal opening slit 7 is embedded in the resin case 1 on the main body side that houses the power transistor, and the resin case 2 for the attached circuit has a metal opening slit 7 embedded therein. A metal protrusion 8 that can be fitted into the slit 7 is provided.

開口スリット部7および金属突出部8はそれぞれケース
内部の素子あるいは回路と電気的に接続されているので
突出部8をスリット部7に上から差し込み、ケース1の
穴9とケース2の穴10を利用して共線めすれば両ケー
ス1,2が一体化されると共にパワートランジスタと付
属回路の電気的接続も行われて外部での配線の必要のな
いモジュールができ上がる。
The opening slit portion 7 and the metal protrusion portion 8 are electrically connected to the elements or circuits inside the case, so insert the protrusion portion 8 into the slit portion 7 from above and connect the hole 9 of the case 1 and the hole 10 of the case 2. If they are used and collinear, both cases 1 and 2 are integrated, and the power transistor and the attached circuit are electrically connected, creating a module that does not require external wiring.

第4図は別θ)配線不要の実施例で、素子を収容した樹
脂ケース1と付属回路を収容した樹脂ケース2とは上下
に組み合わせられ、付属回路と素子との電気的接続はケ
ースlより突出したビン11をケース2に埋め適才れた
プラグ12に差し込むことによって行われる。素子の主
端子13はケース2の表面に露出した主端子14の下に
嵌め込まれ、出力は主端子14から取り出すことができ
る。
Figure 4 shows an example in which no wiring is required (separate θ).The resin case 1 housing the element and the resin case 2 housing the attached circuit are combined vertically, and the electrical connection between the attached circuit and the element is made from case l. This is done by burying the protruding bottle 11 in the case 2 and inserting it into a suitable plug 12. The main terminal 13 of the element is fitted under the main terminal 14 exposed on the surface of the case 2, and the output can be taken out from the main terminal 14.

第5図の実施例では、樹脂ケース2に明けられた取付は
穴15に差し適才れ、イ尉脂ケース1に設けられた雌ね
じ穴16(図で1ま1個のみ示す)にねじ込まれる止め
ねじ17によって両ケースを結合する。素子と付属回路
の接続はこの止めねじ17によって同時lこ行われ、両
ケースの間に配線ブスバー18をはさむことにより外部
回路との接続もできる。
In the embodiment shown in FIG. 5, the mounting holes made in the resin case 2 are inserted into holes 15, and the fixing screws are screwed into female screw holes 16 (only one is shown in the figure) provided in the plastic case 1. Both cases are connected by screws 17. Connection between the element and the attached circuit is made simultaneously by the set screw 17, and connection with an external circuit is also possible by inserting a wiring busbar 18 between both cases.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明は許容温度の高い素子部と許容
温度の低い付属回路部とを別個のパッケージに収容し、
適応した結合手段で一体としてモジュール化するもので
、別個にそれぞれの許容温度の範囲で試験したのち組み
合わせることが製造歩留り上有利であり、信頼性も向1
しする0また、各部の保証温度が独立して選定できるの
で素子の使用効率を高めることができ、さらに一体化の
ための結合上同時に祇気的接続も行うようにすれば配線
の手数が省略でき、接続の信頼性も向上し、接続配勝の
固有振動現象の問題もなくなるなど得られる効果はすこ
ぶる大である0
As described above, the present invention accommodates the element section with a high allowable temperature and the attached circuit section with a low allowable temperature in separate packages,
It is modularized as an integrated unit using suitable coupling means, and it is advantageous in terms of manufacturing yield to combine after testing each separately in the allowable temperature range, and it also improves reliability.
In addition, since the guaranteed temperature of each part can be selected independently, it is possible to increase the efficiency of element usage.Furthermore, if the connection for integration can be made at the same time, the trouble of wiring can be eliminated. The results are extremely large, such as improving the reliability of the connection and eliminating the problem of natural vibration in the connection.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の斜視図、第2図はその組合
せ後の斜視図、第3図、第4図、第5図はそれぞれ異な
る笑施例の斜視図である。 1.2:樹脂ケース、3:凹部、4:凸部、7:開口ス
リット部、8:突出部、11:ピン、12ニブラグ、1
5:取付は穴、16:雌ねじ穴、17:止めねじ。 第1図 第2図 第3図 第4図 9 第5図
FIG. 1 is a perspective view of one embodiment of the present invention, FIG. 2 is a perspective view of the combination thereof, and FIGS. 3, 4, and 5 are perspective views of different embodiments. 1.2: resin case, 3: recess, 4: protrusion, 7: opening slit, 8: protrusion, 11: pin, 12 nib lug, 1
5: Mounting hole, 16: Female threaded hole, 17: Set screw. Figure 1 Figure 2 Figure 3 Figure 4 Figure 9 Figure 5

Claims (1)

【特許請求の範囲】 l)出力用半導体素子を収容したパッケージと該半導体
素子の許容温度より低い許容温度を有する回路素子を含
む付属回路を収容したパッケージと両パッケージを一体
に結合するための手段を備えたことを特徴とする半導体
装置。 2、特許請求の範囲第1項記載の装置において両パンケ
ージを一体に結合するための手段が出力用半導体素子と
付属回路とを電気的に接続する手段とを兼ねたことを特
徴とする半導体装置。 3)特許請求の範囲第1項または第2項記載の装置にお
いて、両パッケージを一体に結合するための手段が一方
のパッケージに設けられた凸部と他方のパッケージに設
けられ、該凸部ζこ嵌合する凹部であることを%徴とす
る半導体装置。 4)特許請求の範囲第1項または第2項記載の装置にお
いて、両パッケージを一体に結合するための手段が一方
のパッケージの貫通孔を通って他方のパッケージのねじ
穴にねじ込まれる止めねじであることを特徴とする半導
体装置。
[Scope of Claims] l) A package containing an output semiconductor element, a package containing an auxiliary circuit including a circuit element having a lower allowable temperature than the allowable temperature of the semiconductor element, and means for joining both packages together. A semiconductor device characterized by comprising: 2. A semiconductor device according to claim 1, characterized in that the means for uniting both pancages together also serves as means for electrically connecting the output semiconductor element and the auxiliary circuit. . 3) In the device according to claim 1 or 2, means for joining both packages together is provided on a convex portion provided on one package and on the other package, and the convex portion ζ A semiconductor device characterized by a recess that fits into the recess. 4) In the device according to claim 1 or 2, the means for joining both packages together is a set screw screwed into a threaded hole in the other package through a through hole in one package. A semiconductor device characterized by the following.
JP10522783A 1983-06-13 1983-06-13 Semiconductor device Pending JPS59229847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10522783A JPS59229847A (en) 1983-06-13 1983-06-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10522783A JPS59229847A (en) 1983-06-13 1983-06-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59229847A true JPS59229847A (en) 1984-12-24

Family

ID=14401773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10522783A Pending JPS59229847A (en) 1983-06-13 1983-06-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59229847A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006920A (en) * 1987-03-18 1991-04-09 Telenorma Telefonbau Und Normalzeit Gmbh Electrical components
JP2002164492A (en) * 2000-11-10 2002-06-07 Fairchild Korea Semiconductor Kk Intelligent power module package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50147665A (en) * 1974-05-16 1975-11-26
JPS54128269A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Hybrid package type integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50147665A (en) * 1974-05-16 1975-11-26
JPS54128269A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Hybrid package type integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006920A (en) * 1987-03-18 1991-04-09 Telenorma Telefonbau Und Normalzeit Gmbh Electrical components
JP2002164492A (en) * 2000-11-10 2002-06-07 Fairchild Korea Semiconductor Kk Intelligent power module package
JP4676640B2 (en) * 2000-11-10 2011-04-27 フェアチャイルドコリア半導體株式会社 Intelligent power module package

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