JPS59228788A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS59228788A
JPS59228788A JP10369683A JP10369683A JPS59228788A JP S59228788 A JPS59228788 A JP S59228788A JP 10369683 A JP10369683 A JP 10369683A JP 10369683 A JP10369683 A JP 10369683A JP S59228788 A JPS59228788 A JP S59228788A
Authority
JP
Japan
Prior art keywords
soldering
printed wiring
thin film
resistance layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10369683A
Other languages
Japanese (ja)
Inventor
芝原 優
森光 正明
遠山 攻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10369683A priority Critical patent/JPS59228788A/en
Publication of JPS59228788A publication Critical patent/JPS59228788A/en
Pending legal-status Critical Current

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Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、チップ部品のように極めて高精度の取(=J
けを必要とするのに適したプリント配線板の製造方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to extremely high-precision processing (=J
The present invention relates to a method of manufacturing a printed wiring board suitable for use in a printed wiring board that requires cutting.

従来例の構成とその問題点 一般にプリント配線板の製造方法は第1図に示すように
、絶縁基板1に導電体パターン2を形成し、この導電体
パターン2の形成面に半田付するランド3を残し、全面
に半田付抵抗層4を形成する構成になっている。
Conventional Structure and Problems Generally, as shown in FIG. 1, a method for manufacturing a printed wiring board involves forming a conductive pattern 2 on an insulating substrate 1, and soldering a land 3 to the surface on which the conductive pattern 2 is formed. The structure is such that a soldering resistive layer 4 is formed on the entire surface, leaving behind.

しかしながら、最近は電子機器の小型化や電子部品技術
の進歩によって、チップ部品を多く用いるようになり、
高精度のプリント配線板が要求されており、例えば、半
田付のランド3と半田付抵抗層4のズレが0.1問以下
、さらには、0.05聰以下の精度が要求されるように
なっている。
However, due to the miniaturization of electronic devices and advances in electronic component technology, more and more chip components are now being used.
High-precision printed wiring boards are required, for example, the misalignment between the soldered land 3 and the soldered resistive layer 4 is required to be less than 0.1, and even less than 0.05. It has become.

このように高精度のプリント配線板になると、従来の製
造方法で、半田伺抵抗層4を形成しても、精度は0.2
閾が限度であり、0.1M以下の精度が得られなく品質
問題がしばしば発生している。これは、半田伺抵抗層4
の位置合わせの際のずれ。
When it comes to high-precision printed wiring boards like this, even if the solder resistor layer 4 is formed using the conventional manufacturing method, the precision is 0.2.
The threshold is the limit, and accuracy of 0.1M or less cannot be obtained, which often causes quality problems. This is the solder resistance layer 4.
Misalignment during alignment.

スクリーン製版素材の伸縮・印刷条件(印圧、印刷スピ
ード)等に起因していると考えられている。
It is thought that this is caused by the expansion and contraction of the screen plate making material, printing conditions (printing pressure, printing speed), etc.

従って従来では、このずれた半田伺抵抗層4を後で、刃
先等で削ずりとる修正工程が必要となる。
Therefore, conventionally, it is necessary to perform a correction process in which the misaligned solder resistance layer 4 is subsequently scraped off with a cutting edge or the like.

寸だ、チップ部品実装時の位置ずれの要因となり不良が
増大するため、生産性2品質の点で著しく不利になるも
のであった。
In fact, this is a significant disadvantage in terms of productivity and quality because it causes positional deviation during chip component mounting and increases the number of defects.

層との位置ずれが無く、高精度のプリント配線が可能な
プリント配線板の製造方法を提供するものである。
The present invention provides a method for manufacturing a printed wiring board that allows highly accurate printed wiring without misalignment with layers.

発明の構成 上記目的を達成するために、本発明は絶縁基板に導電体
パターンを形成し、この導電体パターン上に半田付抵抗
層との密着性が悪く、厚みの均一な薄膜を形成させた後
、全面に半田付抵抗層を形成し、上記導電体パターンの
表面上の半田付抵抗層および上記薄膜を剥離した後に、
ランドを形成しない導電パターン上には再度半田付抵抗
層をノ1.<−成するものである。
Structure of the Invention In order to achieve the above object, the present invention forms a conductive pattern on an insulating substrate, and forms a thin film having a uniform thickness and poor adhesion to the soldering resistance layer on the conductive pattern. After that, a soldering resistance layer is formed on the entire surface, and after peeling off the soldering resistance layer and the thin film on the surface of the conductive pattern,
On the conductive pattern where no land is formed, a soldering resistive layer is again applied. <-.

半田伺抵抗層との密着性が悲い薄膜上の半田イ」抵抗層
の剥離は容易であり、上記薄膜が形成された導電体パタ
ーンの上面の半田付抵抗層だけを剥離することが可能で
あり、半田付抵抗層を剥離した部分であるランドと半a
l +1’抵抗層の位置ずれは生じることがない。
It is easy to peel off the soldered resistive layer on a thin film that has poor adhesion to the soldered resistive layer, and it is possible to peel off only the soldered resistive layer on the top surface of the conductor pattern on which the thin film is formed. Yes, the land and half a are the parts where the soldering resistance layer is peeled off.
No displacement of the l+1' resistance layer occurs.

実施例の説明 以下本発明の一実施例におけるプリント配線板の製造方
法について図面とともに説明する。
DESCRIPTION OF EMBODIMENTS A method of manufacturing a printed wiring board according to an embodiment of the present invention will be described below with reference to the drawings.

まず第2図に示すように合成樹脂からなる絶縁基板50
片面に銅よシなる導電体6を設け、銅張積層板を形成す
る。そして第3図示すように第2図の銅張積層板上の導
電体6をエツチングし、導電体パターン7a、ybを形
成する。
First, as shown in FIG. 2, an insulating substrate 50 made of synthetic resin
A conductor 6 made of copper is provided on one side to form a copper-clad laminate. Then, as shown in FIG. 3, the conductor 6 on the copper-clad laminate of FIG. 2 is etched to form conductor patterns 7a and yb.

次に第4図に示すように、導電体パターン7a。Next, as shown in FIG. 4, a conductor pattern 7a is formed.

7b上に、半田付抵抗層との密着性が悪く、厚みの均一
々薄膜8を形成する。この薄M8は、銅の表面にのみ形
成され、かつ半田付抵抗層との密着性の悪いアルキルイ
ミダゾール系溶液に浸漬させることにより形成させる。
A thin film 8 having a uniform thickness and poor adhesion to the soldering resistance layer is formed on the soldering resistor layer 7b. This thin M8 is formed only on the surface of copper and is formed by immersion in an alkylimidazole solution that has poor adhesion to the soldering resistance layer.

アルキルイミダゾールは常温では、はとんど水に溶けな
いが、酸の雰囲気でイオン化すると水に溶解するように
なるので浸漬は可能である。イオン化したイミダゾール
は銅と強い化学反応を示して、銅と錯体を形成し、銅の
表面に単分子の膜を生じる。このようにしてできた単分
子の膜の上に長鎖のアルキル基によるファンデルワール
スの結合力によって、アルキルイミダゾールが、次々に
集合して膜が成長し、約0.2μmの厚さの薄くて均一
な薄膜8が形成される。このようにして、できあがった
薄膜3は、長鎖のアルキル基による疎水性を示し、紫外
線硬化型インキ等により形成された半田付抵抗層との密
着性は悪い。
Alkylimidazoles are hardly soluble in water at room temperature, but when ionized in an acid atmosphere, they become soluble in water, so immersion is possible. Ionized imidazole exhibits a strong chemical reaction with copper, forming a complex with copper and producing a monomolecular film on the copper surface. On the monomolecular film formed in this way, alkylimidazoles aggregate one after another due to the van der Waals bonding force of long-chain alkyl groups, and a film grows to a thickness of approximately 0.2 μm. A uniform thin film 8 is formed. The thin film 3 thus formed exhibits hydrophobicity due to the long-chain alkyl group, and has poor adhesion to the soldering resistance layer formed with ultraviolet curable ink or the like.

次に第5図に示すように、導電体パターンγa。Next, as shown in FIG. 5, a conductor pattern γa is formed.

為・よr゛ 7 kイ膜8を形成した絶縁基板5の全面に、−ホキシ
アクリレート系の紫外線硬化型インキでソルダーレジス
トと呼ばれる半田付抵抗層9を印刷法等で形成する。
For this purpose, a soldering resistive layer 9 called a solder resist is formed on the entire surface of the insulating substrate 5 on which the transparent film 8 has been formed using a printing method or the like using -oxyacrylate-based ultraviolet curable ink.

次に第6図に示すように、機械的研磨等により、導電体
パターン7a、7bの表面の半田伺抵抗層9を剥離する
。なお導電体パターン7a、7b上の半田付抵抗層9は
アルキルイミダゾール系の薄膜8を介していることによ
り、剥離しやすい。
Next, as shown in FIG. 6, the solder resistance layer 9 on the surfaces of the conductor patterns 7a, 7b is peeled off by mechanical polishing or the like. Note that the soldered resistance layer 9 on the conductor patterns 7a, 7b is easily peeled off because the alkylimidazole thin film 8 is interposed therebetween.

そして次に第7図に示すように塩酸等の酸、またに:機
械的研磨で導電パターン7a、7bの表面のアルキルイ
ミダゾール系の薄膜8を剥離する。
Then, as shown in FIG. 7, the alkylimidazole thin film 8 on the surfaces of the conductive patterns 7a and 7b is removed by using an acid such as hydrochloric acid or by mechanical polishing.

その後第8図に示すように半田付けするランド10を設
ける導電体パターン7bを残し、再度半田付抵抗層11
を導電体パターン7a上に形成する。
After that, as shown in FIG. 8, the conductor pattern 7b on which the land 10 to be soldered is provided is left, and the soldering resistance layer 11 is re-soldered.
is formed on the conductor pattern 7a.

ランド10を設ける導電体パターン7b上の半田付抵抗
層9を除くため、ランド10と半田付抵抗層9との位置
ずれは無く、高精度のプリント配線が可能なプリント配
線板が製造できる。
Since the soldering resistance layer 9 on the conductor pattern 7b on which the land 10 is provided is removed, there is no positional shift between the land 10 and the soldering resistance layer 9, and a printed wiring board that allows highly accurate printed wiring can be manufactured.

なお、上記実施例では片面プリント配線板の場合を示し
たが両面プリント配線板のものでも同様の効果を得るこ
とができる。′=1だ薄膜8としてアルキルイミダゾー
ル系のものを用いたが、酸化皮膜を用いることもできる
In the above embodiment, a single-sided printed wiring board was used, but the same effect can be obtained with a double-sided printed wiring board. '=1.Although an alkylimidazole film was used as the thin film 8, an oxide film may also be used.

発明の効果 以上のように本発明は、導電体パターン上に半田伺抵抗
層との密着性の悪い薄膜を設けた後、絶縁基板の全面に
半田付抵抗層を形成し、導電体・くターン上の半田付抵
抗層を剥離することによりどのように高精度の要求のも
のであっても、ランドと半田付抵抗層とのずれはなくな
る。その結果、半田付抵抗層を刃先等で修正する修正工
程を設ける必要もほとんどなくなり、生産性が向上し、
コストの低減化が図れ、またチップ部品実装時の位置ず
れによる接触不良も減少して、品質の高いプリント配線
板が製造でき、工業的価値の大なるものである。
Effects of the Invention As described above, the present invention provides a thin film with poor adhesion to the solder resistor layer on the conductor pattern, and then forms the solder resistor layer on the entire surface of the insulating substrate. By peeling off the upper soldering resistance layer, no matter how high precision is required, there is no misalignment between the land and the soldering resistance layer. As a result, there is almost no need for a correction process to correct the soldering resistance layer with a cutting edge, etc., improving productivity.
It is possible to reduce costs, reduce contact failures due to misalignment during chip component mounting, and produce high-quality printed wiring boards, which is of great industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のプリント配線板の構造を示す要部断面図
、第2図〜第8図は本発明の一実施例におけるプリント
配線板の製造方法を示す工程図である。 5・・・・・絶縁基板、了a 、7b・・・・・・導電
体パターン、8・・・・・薄膜、9,11・・・・・半
田付抵抗層、1Q・・・・・・ラント。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第2
図 花3図 a 糞5図 う1で
FIG. 1 is a sectional view of a main part showing the structure of a conventional printed wiring board, and FIGS. 2 to 8 are process diagrams showing a method of manufacturing a printed wiring board in an embodiment of the present invention. 5... Insulating substrate, 7b... Conductor pattern, 8... Thin film, 9, 11... Soldering resistance layer, 1Q...・Rant. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure flower 3 figure a, feces 5 figure U1

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板に導電体パターンを形成し、この導電体パター
ン上に、半田付抵抗層との密着性が悪く、厚みの均一な
薄膜を形成させた後、全面に半田付抵抗層を形成し、上
記導電体パターンの表面上の上記半田付抵抗層および上
記薄膜を剥離した後に、ランドを形成しない上記導電体
パターン上には再度半田付抵抗層を形成するプリント配
線板の製造方法。
A conductor pattern is formed on an insulating substrate, a thin film with a uniform thickness and poor adhesion with the soldering resistor layer is formed on the conductor pattern, and then a soldering resistor layer is formed on the entire surface. A method for manufacturing a printed wiring board, which comprises peeling off the soldering resistive layer and the thin film on the surface of the conductive pattern, and then forming a soldering resistive layer again on the conductive pattern where no land is formed.
JP10369683A 1983-06-09 1983-06-09 Method of producing printed circuit board Pending JPS59228788A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10369683A JPS59228788A (en) 1983-06-09 1983-06-09 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10369683A JPS59228788A (en) 1983-06-09 1983-06-09 Method of producing printed circuit board

Publications (1)

Publication Number Publication Date
JPS59228788A true JPS59228788A (en) 1984-12-22

Family

ID=14360935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10369683A Pending JPS59228788A (en) 1983-06-09 1983-06-09 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS59228788A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164490A (en) * 1986-12-26 1988-07-07 日本シイエムケイ株式会社 Manufacture of printed wiring board
JPH01321683A (en) * 1988-06-23 1989-12-27 Nec Corp Manufacture of printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164490A (en) * 1986-12-26 1988-07-07 日本シイエムケイ株式会社 Manufacture of printed wiring board
JPH01321683A (en) * 1988-06-23 1989-12-27 Nec Corp Manufacture of printed wiring board

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