JPS59227159A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59227159A JPS59227159A JP10119983A JP10119983A JPS59227159A JP S59227159 A JPS59227159 A JP S59227159A JP 10119983 A JP10119983 A JP 10119983A JP 10119983 A JP10119983 A JP 10119983A JP S59227159 A JPS59227159 A JP S59227159A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- melting point
- wiring
- high melting
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 238000002844 melting Methods 0.000 claims abstract description 22
- 230000008018 melting Effects 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000002955 isolation Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 150000002739 metals Chemical class 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000005259 measurement Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 235000013305 food Nutrition 0.000 description 2
- 241000270666 Testudines Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
本発明は、ＬＳＩの高集積化を可能にする半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that enables high integration of LSI.
従来、層間絶縁膜で絶縁分離された半導体層と金属層と
を接続する時、半導体層上の絶縁層に選択的にコ１ツタ
クト・ホールを形成後金Ｍｉを蓄積することによル金属
層と＃導体層がコンタクト・ポール領域の面積部分のみ
で接触していた。一方、縮小化の進むＬＳＩにおいて、
コンタクト９ホール寸法はサブミクロンの大きさになる
。しかしながらコンタクト・ホール面積が小さくなるこ
とによシ、金属と半導体の接触抵抗が増大し、ＬＳＩの
電気特性を劣化させる。例えば８４層とＡ１層の接触抵
抗は１μｍ口のコンタクト−ホールで１０００を起える
。またサブミクロン寸法を持つコンタクト拳ホールでは
、オーミックなコンタクト特性を碍ることか困難になる
。従って従来の半導体装置で社コンタクト・ホール寸法
を１μｍ より小さくすることができずＬＳＩの微細化
に制限を与えるという欠点があった。本発明は、かかる
従来の欠点を取シ除き、接触抵抗がコンタクト・ホール
寸法に依存しないことを特長としコンタクト・ホールの
微細化を可能にし、ＬＳＩの高集積化を可能にする半導
体装置を提供する。以下実施例を用いて説明する。第１
図・第２図は、従来の金Ｒ層とＦ３ｉ基板拡散層との接
憂・麦を示す断面図と平面図である。Ｅ３ｉ基板１には
、拡散層２が形成され、へ！配線屑５と拡散Ｎ２は層間
絶縁膜ｓ４ｏ、３で、１！、縁分離されている。ＡＩ配
線層と拡散層の接続柱、層間絶縁膜に選択的に形成され
たコンタクト・ホール４を通して接続される。従来の構
造ではＡ！配線層５と拡散層２の接触面積は第２図の４
の領域になる。Ａ！配線層と拡散層の接触面積はコンタ
クト・ホール面積に等しいため、コンタクト・ホール寸
法が小さくなるに伴込、Ａｊ配線と拡散層との接触抵抗
が増大し、コンタク）ｊポールの微細化に制限を与える
。このためＬＳＩの高集積化が困難になる。Conventionally, when connecting a semiconductor layer and a metal layer that are insulated and separated by an interlayer insulating film, a contact hole is selectively formed in the insulating layer on the semiconductor layer, and then gold Mi is accumulated in the metal layer. The and # conductor layers were in contact only in the area of the contact pole region. On the other hand, in LSIs that are becoming smaller,
The contact 9-hole dimensions are on the submicron scale. However, as the contact hole area becomes smaller, the contact resistance between the metal and the semiconductor increases, degrading the electrical characteristics of the LSI. For example, the contact resistance between the 84th layer and the A1 layer is 1000 for a 1 μm contact hole. Furthermore, in contact holes with submicron dimensions, it is difficult to improve ohmic contact characteristics. Therefore, in conventional semiconductor devices, the size of the contact hole cannot be made smaller than 1 .mu.m, which limits the miniaturization of LSIs. The present invention eliminates such conventional drawbacks, and provides a semiconductor device which is characterized in that the contact resistance does not depend on the contact hole dimensions, enables miniaturization of the contact hole, and enables high integration of LSI. do. This will be explained below using examples. 1st
FIG. 2 is a sectional view and a plan view showing the relationship between the conventional gold R layer and the F3i substrate diffusion layer. A diffusion layer 2 is formed on the E3i substrate 1, and then! Wiring waste 5 and diffusion N2 are interlayer insulating film s4o, 3, 1! , the edges are separated. Connection pillars between the AI wiring layer and the diffusion layer are connected through contact holes 4 selectively formed in the interlayer insulating film. With the conventional structure, A! The contact area between the wiring layer 5 and the diffusion layer 2 is 4 in FIG.
becomes the area of A! Since the contact area between the wiring layer and the diffusion layer is equal to the contact hole area, as the contact hole size becomes smaller, the contact resistance between the Aj wiring and the diffusion layer increases, limiting the miniaturization of the contact)j pole. give. This makes it difficult to achieve high integration of LSI.
帛３図・第４図は、本発明による金属層とＳ＜基板拡散
層との接続を示す断面図と平面図である。3 and 4 are a cross-sectional view and a plan view showing the connection between the metal layer and the S<substrate diffusion layer according to the present invention.
ＳＺ基板１】には、拡散［１２が形成され、ＡＡ配線胎
１６と拡散＃Ｉ２は層間絶縁膜ｓｈｏ、玲で分離されて
いる。Ａ７配＃層１６と拡散層１２の接続は、拡散層上
に形成された高融点金属１７＠コンタクト・ホール領域
の高融点金属１４及びＡＡ配線層底面の高融点食［１５
によ多形成される。高融点食Ｆ％１４・１５・１７は同
一物質で構成される。このＵ、ＡＡ配線層１６と拡散層
１２の接続における接触抵抗は、Ａ１層と高融点金属の
接触領域（第４図ｉ５．１６ ）の接触抵抗及び高融点
金属と拡散層の接触領域（第４図１２ 、１７ ）の接
触抵抗の２つに分けられる。本発明によれば、接触領域
の大きさは、コンタクト・ホール領域の面積（第４図１
４）に依存せず、へ！配線領域の面積（第４図１６ ）
及び拡散領域の面＊、 （ｍ ４図１２ ）に依存する
。従って、コンタクト・ホール寸法が小さくなってもＡ
！配線層と拡散層の接触抵抗は、ｔｌとんど変化しない
。このためコンタクト・ホール寸法がＬＳＩの電気的特
性に与える影響が無視でき、コンタクト・ホールの微細
化が可能になｐ、ＬＳＩの高集積化が可能になる。亀５
図は本発明によるＭＯＢ・ＦＦ！Ｔの断面図である。８
ｉ基板２１上には、 Ｐｏ１ｙ８ｉ電極２９・ゲート族
オ・ソース・ドレインおからなるＭＯＢ・ＦＦＴが形成
されている。２２は素子分離ｓｈｏ！ 膜である。Ａ
！配線層３３とゲート電極２９・ソース・ドレイン領域
邪の接続は、拡散層表面の高融点金ＪＩｊｇ２４拳ゲー
ト電極表面の高融点金属３ｏ・コンタクト・ホール領域
の高融点食ＦＡ２５・３１及びＡ１層下の高融点食ＪＦ
Ｊ２７・３２によル行なわれる。ここで高融点金属を用
いたのは高温熱処理を可能にするためである。本発明に
よれば、ＡＪ配線層とゲート電極の接触抵抗は、コンタ
クト・ホール面積に依存せず、ＡＪ配線面積とゲート′
電極面ｆＪｆに依存する。又、Ａ７１配線層とソース・
Ｗビレ４フ層の接触抵抗杖、コンタクト・ホール面積に
依存せず、へ！配線面積とソース・ドレイン拡散層の面
積に依存する。従ってＭＯＢ−ＦＥＴが縮小化され、コ
ンタクト・ホール寸法が１μｍ２以下になっても、Ａ！
配線面積・ゲート電極面積及びソース・ドレイン拡散層
面積は１μｍ２より大きく取ることができ、接触抵抗の
増大を防ぐことができる。A diffusion #12 is formed on the SZ substrate 1, and the AA wiring layer 16 and the diffusion #I2 are separated by interlayer insulating films. The connection between the A7 wiring layer 16 and the diffusion layer 12 is achieved by the high melting point metal 17 formed on the diffusion layer @ the high melting point metal 14 in the contact hole region and the high melting point corrosion [15] at the bottom of the AA wiring layer.
Formed in polymorphism. High melting point foods F%14, 15, and 17 are composed of the same substance. The contact resistance in the connection between the U, AA wiring layer 16 and the diffusion layer 12 is the contact resistance of the contact area between the A1 layer and the high melting point metal (Fig. 4 i5.16) and the contact area of the high melting point metal and the diffusion layer (Fig. It can be divided into two types: contact resistance (Figures 12 and 17). According to the present invention, the size of the contact area is determined by the area of the contact hole area (see FIG.
4) Don't rely on it! Area of wiring area (Fig. 4 16)
and the plane * of the diffusion region, depending on (m 4 Fig. 12). Therefore, even if the contact hole size becomes smaller, A
! The contact resistance between the wiring layer and the diffusion layer hardly changes at tl. Therefore, the influence of the contact hole dimensions on the electrical characteristics of the LSI can be ignored, making it possible to miniaturize the contact hole and achieve high integration of the LSI. Turtle 5
The figure shows MOB/FF according to the present invention! It is a sectional view of T. 8
On the i-substrate 21, a MOB/FFT consisting of a Po1y8i electrode 29, a gate group, a source, and a drain is formed. 22 is element isolation sho! It is a membrane. A
! Connections between the wiring layer 33 and the gate electrode 29/source/drain region are made using the high melting point gold JIjg24 on the surface of the diffusion layer, the high melting point metal 3o on the surface of the gate electrode, and the high melting point corrosion FA25/31 in the contact hole region and under the A1 layer. High melting point food JF
It will be held on J27/32. The reason why a high melting point metal is used here is to enable high temperature heat treatment. According to the present invention, the contact resistance between the AJ wiring layer and the gate electrode does not depend on the contact hole area;
It depends on the electrode surface fJf. In addition, the A71 wiring layer and the source
Contact resistance rod with 4 layers of W fins, independent of contact hole area, to! It depends on the wiring area and the area of the source/drain diffusion layer. Therefore, even if the MOB-FET is downsized and the contact hole size becomes less than 1 μm2, A!
The wiring area, gate electrode area, and source/drain diffusion layer area can be set to be larger than 1 μm 2 , and an increase in contact resistance can be prevented.
以上説明したように、本発明によれば、微細化されたコ
ンタクト・ホール寸法に接触抵抗が依存せず、ＭＯＥＩ
＠ＦＥＴの縮小ができ、ＬＳＩ工の高集積化が可能にな
る。As explained above, according to the present invention, the contact resistance does not depend on the miniaturized contact hole dimensions, and the MOEI
@FET can be downsized, and high integration of LSI technology is possible.
第１図：従来の金属層とＳＺ基板拡散層との接続を示す
断面図
第２図；従来の金属層とｓｉ基板拡散層との接続を示す
平面図
第３図二本発明による金属層とｓｉ基板拡散層との接続
を示す断面図
第４図二本発明による金属層とｓｉ基板拡散層との接続
を示す平面図
第５図二本発明によるＭＯ８ａｌＰＪ！ｉＴの断面図ｉ
−ｎ Ｏ２１・・８ｉ基板
２・１２・−拡散層
ａ ＠ １Ｂ ＋１ ＠ Ｆ３ｉ０ｓＩＴ８縁膜４・・
コンタクト・ホール
５・＠Ａノ配線
１４−−コンタクト・ホール
１５・１７・・高融点金属
１６・・ＡＡ配線
２２・嗜素子分離ｓｉｏ！
お・・ソース・ドレイン拡散層
鴎・・ソース・ドレイン表面高融点金属層５・轡コンタ
クト・ホール高融点金属
あ・・層間絶縁膜ｓｚｏ。
２７・・高融点金属配線層
あ・・ゲート絶縁膜ｓｈｏ。
四・ ・Ｐｏ１ｙ８ｉゲート電極
（資）・・ゲート電極表面高融点金属層３１・・コンタ
クト・ホール高融点金属３２拳・高融点金属配線層
以 上
出願人 株式会社諏訪精工舎
代理人 弁理土星 上 務Figure 1: A cross-sectional view showing the connection between a conventional metal layer and an SZ substrate diffusion layer. Figure 2: A plan view showing a connection between a conventional metal layer and an Si substrate diffusion layer. FIG. 4 is a cross-sectional view showing the connection to the Si substrate diffusion layer. FIG. 5 is a plan view showing the connection between the metal layer and the Si substrate diffusion layer according to the present invention. MO8alPJ! Cross section of iT
-n O21...8i substrate 2, 12... -diffusion layer a @ 1B +1 @ F3i0sIT8 edge film 4...
Contact hole 5, @A wiring 14--Contact holes 15, 17, high melting point metal 16, AA wiring 22, element isolation sio! Oh...source/drain diffusion layer...source/drain surface high melting point metal layer 5/contact hole high melting point metal...interlayer insulating film szo. 27...High melting point metal wiring layer...Gate insulating film sho. 4. Po1y8i gate electrode (capital) Gate electrode surface high melting point metal layer 31 Contact hole High melting point metal 32 layers High melting point metal wiring layer and above Applicant Suwa Seikosha Co., Ltd. Agent Benri Saturn Senior Managing Director
Claims (1)
ｉｉ層との接続において、該半ｄ１体層表面・該絶縁層
に選択的に形成されたコンタクト書ホール及び該金属層
底面には該金属層と同ａまたは異種の金属が蓄積してな
ることを特長とする半導体装置。 ｔ２＋シリコンゲート及びＡ！配線を持つＭＯＳ・ＦＩ
ＩＣＴにおいて、ソース・ドレイン拡散領域表面・ゲー
ト電極表面・ＡＪ配線層底面及びコンタクト９ホール領
域には高融点全屈が蓄積してなることを特徴とする特許
請求の！＃、囲第１項記載の半導体装置。[Claims] A semiconductor layer and gold j that are insulated and separated by an interlayer insulating crotch.
In connection with layer II, metal of the same type as or different from that of the metal layer is accumulated on the surface of the semi-d1 layer, the contact hole selectively formed in the insulating layer, and the bottom of the metal layer. A semiconductor device featuring: t2+silicon gate and A! MOS/FI with wiring
In ICT, a patent claim characterized in that high melting point total bending is accumulated on the surface of the source/drain diffusion region, the surface of the gate electrode, the bottom surface of the AJ wiring layer, and the contact 9 hole region! #, the semiconductor device described in box 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10119983A JPS59227159A (en) | 1983-06-07 | 1983-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10119983A JPS59227159A (en) | 1983-06-07 | 1983-06-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59227159A true JPS59227159A (en) | 1984-12-20 |
Family
ID=14294261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10119983A Pending JPS59227159A (en) | 1983-06-07 | 1983-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59227159A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6257234A (en) * | 1985-09-06 | 1987-03-12 | Hitachi Ltd | Wiring structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4840301A (en) * | 1971-09-23 | 1973-06-13 |
-
1983
- 1983-06-07 JP JP10119983A patent/JPS59227159A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4840301A (en) * | 1971-09-23 | 1973-06-13 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6257234A (en) * | 1985-09-06 | 1987-03-12 | Hitachi Ltd | Wiring structure |
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