JPS6037770A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6037770A JPS6037770A JP14702983A JP14702983A JPS6037770A JP S6037770 A JPS6037770 A JP S6037770A JP 14702983 A JP14702983 A JP 14702983A JP 14702983 A JP14702983 A JP 14702983A JP S6037770 A JPS6037770 A JP S6037770A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- contact
- area
- connection hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 47
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Abstract
Description
【発明の詳細な説明】
−｝ Ｚｔ Ｉｌｌイ ｌ＋ Ｔ． Ｏ Ｔ ｔＴ’＋
Ｔ’ｊ イＪ（ 丁！１ Ｉし ｆ−７ｉＴ台し ｒ
ｌ ４− ７− ｅｌＡ ；：”Ｌ休装置に関する。[Detailed Description of the Invention] −} Zt Illi l+ T. OT tT'+
T'j iJ( ding!1 Ishi f-7iT base r
l4-7-elA;:”Relating to L-stop device.
従来、Ｒり間絶緑膜で絶縁層１’ｉ［ｈされた半導体層
と金属層とを接続する時、半導体層上の絶縁層に選択的
にコンタクト・ホールを形成後金属を蓄積することによ
り金属層と半導体層がコンタクト・ホール領域の面積部
分のみで接触していた。一方、縮小化の進むＬＳＩにお
いて、コンタクト・ホール寸法はサブミクロンの大きさ
になる。しかしながらコンタクト・ホール而’ｆｌが小
さくなることにより１金属と半導体の接触抵抗が増大し
、ＬＳＩの電気特性を劣化させる。例えばＳ：１層とＡ
ｔ層の接触抵抗は１μｍ［１のコンタク１・・ホールて
１００Ωを越える。またザブミクロシマ１法を持つコン
タクｉ・・ホールでは、オーミック′ｌ「コンタクト特
性を得ることが困触になる。従って従来の半導体装置で
はコンタクト・ホール＝Ｊ法を１ ／１ ｒｎＯより小
さくすることができずＬＳＩの微細化に制限を与えると
いう欠点があった。本発明は、かかる従来の欠点を取り
除き、接触抵抗がコンタクト・ホール寸法に依存しない
ことを特長としフンタクト・ホールの微細化を可能にし
、ＬＳＩの高集積化を可能にする半導体装置を提供する
。以下実施例を用いて説明する。第１図、第２図は、従
来の金属層と８１基板拡散層との接続を示す断面図と平
面図である。８１基板１には、拡散層２が形成され、Ａ
ｔ配線層５と拡散Ｒ・７２は層間絶縁膜ＳｉＯ２３で絶
縁分子ｉｉｌ＆されている。Ａｔ配腺層と拡散層の接続
は、層間絶縁膜に選択的に形成されたコンタクト・ホー
ル４を通して接続される。従来の描造ではＡｔ配線Ｆｒ
’Ｊ ５と拡散１’ｉ’５２の接触…１積は第２（２）
の４の領域になる。Ａ／配線層と拡散層の接触面積はコ
ンタクト・ホール面積に等しいため、コンタクト・ホー
ル寸法が小さくなるに伴い、Ａｔ配Ｘ９と拡散層との接
触抵抗が増大し、コンタクト・ホールの微細化に制限を
与える。このためＬＳＩの高集１１’ｒＪ化が困が（［
になる。Conventionally, when connecting an insulating layer 1'i[h with an R-interrupted green film to a metal layer, contact holes are selectively formed in the insulating layer on the semiconductor layer and then metal is accumulated. Due to this, the metal layer and the semiconductor layer were in contact only in the area of the contact hole region. On the other hand, in LSIs that are becoming smaller, the contact hole size becomes submicron. However, as the contact hole fl becomes smaller, the contact resistance between the metal and the semiconductor increases, deteriorating the electrical characteristics of the LSI. For example, S: 1 layer and A
The contact resistance of the t-layer exceeds 1 μm [1 contact 1 hole] and 100 Ω. In addition, with contact holes using the Zabumicroshima 1 method, it becomes difficult to obtain ohmic contact characteristics.Therefore, in conventional semiconductor devices, it is difficult to make the contact hole = J method smaller than 1/1 rnO. The present invention eliminates such conventional drawbacks and enables miniaturization of the contact hole by making the contact resistance independent of the contact hole dimensions. , provides a semiconductor device that enables high integration of LSI.It will be explained below using an example.FIG. 1 and FIG. 2 are cross-sectional views showing the connection between a conventional metal layer and an 81 substrate diffusion layer. 81 A diffusion layer 2 is formed on the substrate 1, and A
The t-wiring layer 5 and the diffusion R 72 are insulated by insulating molecules iil& by an interlayer insulating film SiO23. The At wiring layer and the diffusion layer are connected through contact holes 4 selectively formed in the interlayer insulating film. In the conventional drawing, At wiring Fr
Contact between 'J 5 and diffusion 1'i'52...1 product is second (2)
This is the fourth area. A/Since the contact area between the wiring layer and the diffusion layer is equal to the contact hole area, as the contact hole size becomes smaller, the contact resistance between the At interconnection layer X9 and the diffusion layer increases, leading to miniaturization of the contact hole. Give limits. For this reason, it is difficult to make LSI high-density 11'rJ ([
become.
第６図、第４図は、本発明による金属Ｊ’＞７と８１基
板拡散ｊ９〆ｉとの接続を示す断面は１と平面図である
。８１基板１１には、拡散Ｊ’ｇ １２が形成され１、
Ａｔ配線層１６と拡散層１２は層間絶縁膜５ｉＯ２１３
で分ｎｆされている。Ａｔ配線層１６と拡散層１２の接
続は、拡散層上に形成された全屈シリザイド１７．コン
タクト・ホール６１１ 域の金属シリサイド１４及びＡ
ｔ配置１４層底面の金属シリサイド１５により形成され
る。金Ａ・ｊＬシリサイド１４゜１５．１７は同一物質
で構成される。この時、Ａｔ配線層１６と拡散層１２の
接続における接触抵抗は、Ａｔ層と金属シリサイドの接
ｆ’ｊ・１；領域（第４図１５．１６）の接触抵抗及び
金属シリサイドと拡散層の接触領域（第４図１２．１７
）の接触抵抗の２つに分けられる。本発明によれば、接
触領域の大きさは、コンタクト・ホール領域の面積（第
４図、１４）に依存けず、Ａｔ配線ｆｉ域の面積（第４
閏、１６）及び拡散領域の面積（ら′５４図、１２）に
依存する。従ってコンタクト・ホール寸法が小さくなっ
てもＡｔ配ｐ」１層と拡散Ｒ・；の接触抵抗は、はとん
ど変化しない。このためフンタクト・ホール寸法がＬＳ
Ｉのｆｆｊｊ気的特性的特性る影響が無視でき、コンタ
クト・ホールの微細化が可能になり、ＬＳＩの高年ｆｌ
Ｌ１化が可能になる。第５図は本発明によるＭＯＳ−Ｆ
ＥＴの断面図である。Ｓｉ基板２１上には、Ｐ Ｏｌ
ｙ Ｓ層 ｉゲート電極２９、ゲートＪＩＳ：； ２８
１ソース・ドレイン２３からなるＭＯＳ−ＦＥＴが形成
されている。２２は素子分子’：（Ｆｓ １０２１Ｆ７
ｆｒア；６゜Ａｔ１ｖ！１９ ＪＧ ５５とゲート電極
２９．ソース・ドレイン領域２３の接続は、拡散１；・
７表面の金属シリサイド２４．ゲート電極表面の金属シ
リサイド３０．コンタクト・ホール領域の金属シリサイ
ド２５．３１及びり、１１Ｍ下の金属シリサイド２７．
３２により行なわれる。本発明によれば、Ａｔ配線ｊ（
・ｊとゲート電極の接触抵抗は、コンタクト・ホール面
積に依存せず、Ａｔ配π′４．！面（、ｙＨとゲート電
極面積に依存する。又、Ａｔ配イ（４層とソース・ドレ
イン層の接触抵抗は、コンタクト・ホール面積に依存せ
ず、Ａｔ配れ！面積とソース・ドレイン拡散層の商況１
に依存する。従ってＭＯＳ−ＦＫＴが縮小化さ、れ、コ
ンタクト・ホール寸法が１１１ｍ２以下になっても、Ａ
ｔ配線面積、ゲート電極面積及びソース・ドレイン拡散
層抵抗の増大を防ぐことができる。6 and 4 are cross-sectional views 1 and plan views showing the connection between metal J'>7 and 81 substrate diffusion j9〆i according to the present invention. 81 substrate 11, diffusion J'g 12 is formed 1,
The At wiring layer 16 and the diffusion layer 12 are made of an interlayer insulating film 5iO213
It is divided into minutes. The connection between the At wiring layer 16 and the diffusion layer 12 is made using a fully bent silicide layer 17. formed on the diffusion layer. Metal silicide 14 and A in contact hole 611 area
It is formed by the metal silicide 15 on the bottom surface of the t-arrangement 14 layer. Gold A.jL Silicide 14°15.17 is composed of the same material. At this time, the contact resistance in the connection between the At wiring layer 16 and the diffusion layer 12 is the contact resistance of the contact region f'j·1; Contact area (Fig. 4 12.17)
) can be divided into two types: contact resistance. According to the present invention, the size of the contact region does not depend on the area of the contact hole region (FIG. 4, 14), but the area of the At wiring fi region (FIG. 4, 14).
16) and the area of the diffusion region (Fig. 54, 12). Therefore, even if the contact hole size becomes smaller, the contact resistance between the At p'1 layer and the diffusion R2 hardly changes. Therefore, the dimension of the hole is LS.
The influence of the physical characteristics of I can be ignored, making it possible to miniaturize the contact hole, and improve the performance of LSI in older years.
L1 conversion becomes possible. FIG. 5 shows a MOS-F according to the present invention.
It is a sectional view of ET. On the Si substrate 21, P Ol
y S layer i gate electrode 29, gate JIS:; 28
A MOS-FET consisting of one source and drain 23 is formed. 22 is the element molecule': (Fs 1021F7
fr a;6°At1v! 19 JG 55 and gate electrode 29. The source/drain regions 23 are connected by diffusion 1;
7 Metal silicide on the surface 24. Metal silicide on the gate electrode surface 30. Metal silicide 25.31 in the contact hole area and metal silicide 27.31 below 11M.
32. According to the present invention, the At wiring j (
・The contact resistance between j and the gate electrode does not depend on the contact hole area, and the contact resistance between At distribution π′4. ! The contact resistance between the At layer (4 layers and the source/drain layer does not depend on the contact hole area, but depends on the At layer area and the source/drain diffusion layer). Business situation 1
Depends on. Therefore, even if the MOS-FKT is downsized and the contact hole size becomes less than 111m2, the A
It is possible to prevent increases in the t-wiring area, gate electrode area, and source/drain diffusion layer resistance.
以上説明したように、本発明によれば、微粁１化された
コンタクト・ホール寸法に接触抵抗が依存せず、）シ０
８−ＦＥＴの縮小ができ、ＬＳＩの高集積化が可能にな
る。As explained above, according to the present invention, the contact resistance does not depend on the size of the contact hole made into a small size, and
The 8-FET can be downsized and the LSI can be highly integrated.
第１図・・・・・・従来の金属Ｅｑとｓ １ｐ、ｇ板波
ｆｆｔ Ｉ；’７との接続を示す断面図
第２図・・・・・・従来の金ｒｊＳＪ”７ｔと８１基板
拡１１に層との接続を示す平面はＩ
第３図・・・・・・本発明による金）；Ｓ層とＳｉ基板
拡散層との」：！こ級を示す１ｉＪｉ而図
第４図・・・・・・本発明による金属ＲｊとＳ ｉ、
：Ｉ（ｊｉ板拡１１に層との接続を示す平面図
第５図・・・・・・本発明によるＭ ＯＳ ＝Ｆ Ｅ
Ｔの断面図
１．１１．２１・・・・・・８１基板
２．１２・・・・・・拡散ｈ
４・・・・・・コンタクト、・ホール
５・・・・・・ｐ、ｔｐ（５線
１４・・・コンタクト・ホール
１５．１７・・・・・・金属シリサイド１６・・・Ａｔ
配線
２２・・・素子分”ｊ（ｆ ８ ｉ ０２２３・・・ソ
ース・ドレイン拡散層
２４・・・ソース・ドレイン表面金属シリサイド２５・
・・コンタクト・ホール金属シリサイド２６・・・層間
絶縁膜ＳｉＯ□
２７・・・金Ｍシリサイド配線
２８・・・ゲート絶縁１１ｒ；ｉ ８ ｉｏ 、。
２９・・・Ｐ Ｏ１ｙ Ｓ ｉゲート電極３０・・・ゲ
ート１゛ニ極表面金属シリサイド３１・・・コンタクト
・ホール金属シリサイド３２・・・金属シリサイド配線
層
３３・・・ＡＡｉ記線
以 上
出願人 株式会社諏訪精工舎Figure 1: Cross-sectional view showing the connection between conventional metal Eq and s 1p, g plate wave fft I;'7 Figure 2: Conventional gold rjSJ''7t and 81 substrate The plane showing the connections with the layers in the enlarged 11 is I. Figure 4 shows this class...Metals Rj and S i according to the present invention,
:I (Plant view showing the connection with the layer on the ji plate 11. FIG. 5. MOS = F E according to the present invention.
Cross-sectional view of T 1.11.21...81 Substrate 2.12... Diffusion h 4... Contact, Hole 5... p, tp ( 5 wire 14...Contact hole 15.17...Metal silicide 16...At
Wiring 22... Element part "j (f 8 i 0223... Source/drain diffusion layer 24... Source/drain surface metal silicide 25.
...Contact hole metal silicide 26...Interlayer insulating film SiO□ 27...Gold M silicide wiring 28...Gate insulation 11r; i 8 io,. 29...P O1y Si Gate electrode 30...Gate 1' diode surface metal silicide 31...Contact hole metal silicide 32...Metal silicide wiring layer 33...AAi markings Applicant Suwa Seikosha Co., Ltd.
Claims (1)
いる半導体層と金属Ｒ５との接続において、該半導体層
表面、該絶縁層に選択的に形成されたコンタクト・ホー
ル及び該金属層底面には金属シリサイドが蓄積してなる
ことを特徴とする半導体装置。 （２） シリコンゲート及びＡｔｉ！ｉＬ！線を持つＭ
ＯＳ・ＦＫＴにおいて、ソース・ドレイン拡散領域表面
・ゲー） ’ｉｉ、、り極表面・ｈｔ配線’Ｅ（ｉ底面
及びコンタクト・ポール領域には金属シリサイドが蓄積
してなることを特？：ｔとする特許請求の範囲第１項記
載の半導体装置。[Claims] (i) In the connection between the semiconductor layer and the metal R5, which are insulated by I+IJ insulation jIi■, the contact formed selectively on the surface of the semiconductor layer and the insulating layer. A semiconductor device characterized in that metal silicide is accumulated in the hole and the bottom surface of the metal layer. (2) Silicon gate and Ati! iL! M with a line
In OS/FKT, metal silicide is accumulated on the bottom surface of the source/drain diffusion region/gate) 'ii, electrode surface/ht wiring'E (i) and the contact/pole area. A semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14702983A JPS6037770A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14702983A JPS6037770A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037770A true JPS6037770A (en) | 1985-02-27 |
Family
ID=15420923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14702983A Pending JPS6037770A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037770A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57124476A (en) * | 1981-01-26 | 1982-08-03 | Toshiba Corp | Manufacture of semiconductor device |
-
1983
- 1983-08-10 JP JP14702983A patent/JPS6037770A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57124476A (en) * | 1981-01-26 | 1982-08-03 | Toshiba Corp | Manufacture of semiconductor device |
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