JPS5922448A - Initial phase setting circuit of pll - Google Patents

Abstract

PURPOSE:To attain a stable phase locking by pull-in operation, by utilizing an alarm signal where a receiving signal goes to ''0'' by the pull-in phase locking of normalizing or high-order group side and a reset of a frequency-division circuit of an input clock, and making the phase difference at a phase comparison start pi/2. CONSTITUTION:When the alarm signal AIS is at ''1'' (out of phase of high-order group side or intermission of signal), an output signal of the AND condition of a frequency-division output of the prescribed frequency-division stage of frequency division circuits 16, 17 is inputted from an AND circuit 19 to a differentiating circuit 18, and its differentiated output is inputted to an AND circuit 20. Then, frequency division circuits 11, 12 are reset periodically in synchronizing operation of the frequency division circuits 16, 17. When a high-order group signal is restored to the normal state and the alarm signal AIS goes to ''0'', the AND circuit 20 is closed and the resetting of the frequency division circuits 11, 12 is not performed. That is, the phase difference of each frequency division output signal inputted to a phase comparator 13 is nearly pi/2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an initial phase setting method for a PLL, which initially sets the phase difference at the start of PLL phase comparison to be within a predetermined range, and performs stable synchronization pull-in. It is related to circuits.

Prior Art and Problems In a PCM signal transmission system, a clock is recovered from a received signal, the jitter of the recovered clock is suppressed, and a clock is output by a phase locked loop (PLL), and the received signal is identified using the clock. This is what we do. For example, a conventional PLL for this purpose uses a clock regenerated from a received signal as an input clock WCLK, divides the frequency by N in a frequency divider circuit 1, and further divides the frequency by 2 in an i frequency divider circuit 2, as shown in Fig. 1. , the output of the voltage controlled oscillator 5 is used as an output clock RC for identifying the received signal.
LK, and this output clock is divided by N by the frequency dividing circuit 6,
Furthermore, the frequency is divided by two in a frequency dividing circuit 7, the output signal phase of the frequency dividing circuit 2 and the output signal phase of the frequency dividing circuit 7 are compared in a phase comparator 3, and the comparison output is subjected to voltage control via a low-pass filter 4. This is used as a control voltage for the oscillator 5.

The phase comparison characteristic of the relationship between the phase difference of P'LL and the phase comparison output has a triangular wave shape as shown in FIG.
Assuming that the phase difference in the steady state is φ, the phase difference at which the phase comparator 3 starts phase comparison when the normal state returns from loss of synchronization or input loss is not constant, so for example, the phase difference at the start of phase comparison is When is α, a steady state may be reached as shown by the dotted line. This process is relatively slow, and during this time the output clock phase changes by more than π, that is, a slip occurs, and the phase of the output clock shifts during received signal identification, causing 1 bit to be missed. It turns out.

Also, on the receiving side, it is converted into a lower group signal by a demultiplexer,
Data identification is performed on this lower group signal using a clock synchronized with the lower group signal using the PLL described above. In that case, if the demultiplexer side is out of synchronization, the identification data will be incorrect even if the lower group is synchronized, so if the demultiplexer side is out of synchronization, an alarm signal will be sent to the lower group circuit. It is something to do. for example,
(a) in Fig. 3 is the upper group signal, and at time t1, the upper group signal becomes normal, and the alarm signal also becomes “°” as shown in (b).
1″ to II OII, the subgroup becomes (c
As shown by +, the synchronization is brought into the state at time t2, but as mentioned above, it is determined that the synchronization is out of synchronization due to the misreading of one bit.
A resynchronization pull-in operation is performed at time t3, and the synchronization pull-in state is often reached at time L4.

Therefore, the synchronization pull-in state occurs after a time T1 after the lower group signal becomes normal, which has the drawback of requiring a relatively long time.

OBJECTS OF THE INVENTION The object of the present invention is to increase the speed of phase locking by setting the phase difference at the start of PLL phase comparison within a predetermined range. Examples will be described in detail below.

Embodiment of the invention FIG. 4 is a block diagram of an embodiment of the invention, where 11 is N
A first frequency dividing circuit that divides the frequency, 12 a second frequency dividing circuit that divides the frequency by 2, 13 a phase comparator, 14 a low-pass filter, 1
5 is a voltage controlled oscillator, 16 is a third frequency dividing circuit that divides the frequency by N, 17 is a fourth frequency dividing circuit that divides the frequency by 2, 18 is a differential circuit,
19.20 is an AND circuit. As mentioned above, the input clock WCLK is regenerated from the received signal and input to the PLL.
The output clock RCLK from the voltage controlled oscillator 15 is divided by frequency dividing circuits 11, 12, 16, and 17 and input to the phase comparator 13, and the phase comparison output is passed through the low-pass filter 14 to the voltage controlled oscillator 15. becomes the control voltage. In addition, an alarm signal AIS (8 fa
rm_Indica_onSignal) is input to the AND circuit 20. The output signal of this AND circuit 20 becomes a reset signal for the frequency divider circuits 11 and 12. Also frequency dividing circuit 1
6. The output from the predetermined frequency division stage of 17 is input to the AND circuit 19, and the output of the AND circuit 19 is input to the 1-frequency divider circuit 18.
is input.

When the alarm signal AIS is "1" (out of synchronization or signal disconnection on the higher-order group side), the AND condition output signal of the frequency division output of the predetermined frequency division stage of the frequency division circuits i6 and 17 is transferred from the AND circuit 19 to the differentiating circuit 18. is input to the AND circuit 20, and its differential output is input to the AND circuit 20.
is man-powered. Therefore, frequency divider circuits 11 and 12 are frequency divider circuits 1
It is reset periodically in synchronization with the frequency division operation of 6.17.

Alarm signal A when the higher-order group signal returns to normal state.
When IS becomes "0", the AND circuit 20 is closed and the frequency divider circuits 11 and 12 are no longer reset.

In other words, the phase comparison when the higher-order group signal is in a normal state is
Immediately after the frequency dividing circuits 11 and 12 are reset in synchronization with the frequency dividing operation of the frequency dividing circuits 16 and 17, the phase difference between the frequency divided output signals input to the phase comparator 13 is π/ It will be around 2. Therefore, phase synchronization pull-in becomes faster.

FIG. 5 shows the phase comparison characteristic of the relationship between the phase difference and the comparison output similar to that in FIG. .12 is reset in synchronization with the frequency dividing operation of the frequency dividing circuits 16 and 17, so that it becomes close to π/2 as shown by a, and the steady state is reached as shown by the solid arrow. Pulling is performed in the direction where the phase difference φ is achieved. Therefore, no phase slip occurs.

FIG. 6 is a time cheat for explaining the operation, where fa) is the upper group signal, fbl is the 11th report signal (AIS), (C
1 indicates the synchronous pull-in state of the lower group, (cl+ indicates the reset signal. When the upper group signal becomes normal at time t1, the alarm signal also changes from "1" to "0". As a result, (d)
The reset signal will not be output as shown in
Phase synchronization is performed by the phase comparison output of the phase comparator 13, and a synchronization state is achieved at time t2. In this case, unlike the conventional example described above, no phase slip occurs, so that the synchronized state once pulled in will not be lost. Therefore T
The synchronization pull-in will be completed in time 2. As is clear from comparing this time T2 with time T1 in FIG. 3, TI>T2, and the configuration of the present invention enables high-speed synchronization pull-in. As such, the present invention provides an alarm signal AIS that becomes "0" when the received signal becomes normal or when the higher order group side synchronizes,
Frequency divider circuit 11.1 that divides the input clock WCLK
2 is used to set the phase difference at the start of phase comparison to, for example, around π/2, making it possible to shorten the time until phase synchronization is established. Furthermore, since this configuration requires only a slight addition to the conventional configuration, it is possible to set an economically stable initial phase of the PLL. Note that the alarm signal AIS “work” and “0” are gate circuit 2.
It is also possible to reverse the above-described embodiment depending on the configuration of the 0, etc., and various other additions and changes can be made.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional PLL, Fig. 2 is a phase comparison characteristic diagram illustrating the start of phase comparison, Fig. 3 is a time chart illustrating synchronization pull-in, and Fig. 4 is a diagram of a PLL according to an embodiment of the present invention. The block diagram, FIG. 5 is a phase comparison characteristic diagram illustrating the start of phase comparison in the embodiment of the present invention, and FIG. 6 is a time chart 1 for explaining synchronization pull-in in the embodiment of the present invention. 11 is a first frequency dividing circuit, 12 is a second frequency dividing circuit, 13 is a phase comparator, 14 is a low-pass filter, 15 is a voltage controlled oscillator, 16 is a third frequency dividing circuit, and 17 is a fourth frequency dividing circuit. 18 is a differential circuit, and 19.20 is an AND circuit. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Tamamushi Kagobe and 3 others 27 Figure 1 Figure 2 Figure 3 Figure 4 RCL Figure 5 Figure 6 Figure 1 ■ (d)

Claims (1)

[Claims] A PLL that compares a signal phase obtained by frequency-dividing an input clock with a signal phase obtained by frequency-dividing an output clock output from a voltage-controlled oscillator, and uses the comparison output as a control voltage of the voltage-controlled oscillator.
A first frequency dividing circuit that divides the input clock by N, a second frequency dividing circuit that divides the output of the first frequency dividing circuit by two, and a second frequency dividing circuit that divides the output of the voltage controlled oscillator by N. A third frequency dividing circuit that divides the frequency, a fourth frequency dividing circuit that divides the output of the third frequency dividing circuit by two, and a predetermined frequency dividing stage of the third and fourth frequency dividing circuits. a differentiating circuit that differentiates the output of the logical product of the outputs of the differential circuit, and the output of the logical product of the output of the differentiating circuit and the alarm signal.
and a circuit for setting a reset signal for a second frequency dividing circuit.