JPH0918525A - Discriminating and timing extracting circuit - Google Patents

Abstract

PURPOSE: To provide a discriminating and timing extracting circuit which can extract a clock from burst input data instantaneously and has small deviation between the extracted clock and optimum discrimination and timing even when the continuance of the same code of the burst input data is long. CONSTITUTION: The oscillation of a 1st voltage-controlled oscillator 4a is controlled with a 1st gating signal outputted by a 1st gating circuit equipped with a delay circuit, an exclusive OR circuit, and a logic inverting circuit. The discriminating and timing extracting circuit TC1 which discriminates the burst input data by a 1st discriminating circuit 5a according to the clock outputted by this 1st voltage-controlled oscillator 4a locks the phase of the clock by a PLL 11 and connects the oscillation frequency control terminal of the 1st voltage-controlled oscillator 4a and the oscillation frequency control terminal of a 2nd voltage-controlled oscillator 4a in the PLL 11 to the output terminal of a low-pass filter 7 in the PLL 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification / timing extraction circuit for extracting a clock for identifying and reproducing a received signal and performing identification and reproduction in a receiving circuit for digital signal transmission, and more particularly to a packet burst signal. Respond instantly,
The present invention relates to an identification / timing extraction circuit that extracts a clock.

[0002]

BACKGROUND ART An identification / timing extraction circuit in a digital transmission system receives a data signal deteriorated by being transmitted through a communication medium, identifies and reproduces it,
It is a circuit that realizes transmission characteristics without quality deterioration.

FIG. 11 is a diagram showing the phase relationship among input data, clocks, and identification data, and FIG. 12 is a diagram showing an example of burst transmission waveforms.

NRZ (None-return-to-Zer) which is usually used in the above digital transmission system.
In the o) code transmission method, since the clock component is not transmitted, it is necessary to extract the clock for performing the identification reproduction. Further, the burst data transmission system receives a burst packet signal as shown in FIG. In the above system, when the phase of each data packet is asynchronous, it is necessary to instantaneously extract the clock corresponding to each burst input data.

FIG. 13 is a diagram showing a prior example of an identification / timing extraction circuit for burst transmission.

A prior example of this identification / timing extraction circuit is the circuit disclosed by the inventor of the present application in Japanese Patent Application No. 7-42430, in which the phase of input data is 1 / of the transmission rate.
The delay circuit 1 delays the phase by two cycles, the exclusive OR circuit 2, the logical inversion circuit 3, and the voltage controlled oscillator 4 whose oscillation is controlled by the gating signal output from the logical inversion circuit 3, The exclusive OR of the input data and the delayed output is taken, the inversion signal is used as a gating signal to control the start / stop of the oscillation of the voltage controlled oscillator 4, and the oscillation signal output from the voltage controlled oscillator 4 is It is used as a clock for identification reproduction.

FIG. 14 is a timing chart in the above prior art.

In the preceding example, the input data and 90
The switch of the sign of the NRZ signal is detected by taking the exclusive OR of the delayed data and the start / stop phase control signal of the voltage controlled oscillator 4 which outputs the clock. . Therefore, in the above prior art example, the clock can be extracted instantaneously.

Further, by using an inversion signal of the output signal of the exclusive OR circuit 2 as a gating signal,
When the same code continues, the gating signal is always "H".
Therefore, depending on the oscillation frequency of the voltage controlled oscillator 4,
Since the voltage-controlled oscillator 4 continues to oscillate, in the above-described prior art example, it becomes possible to continue to generate the clock even when the input data is continuous with the same sign.

[0010]

However, in the above-mentioned prior art example, it is necessary to externally provide a reference clock or a reference oscillation frequency control voltage for the clock frequency. Therefore, in the above prior art example, since the clock frequency is determined by the external reference frequency that is asynchronous with the input data, when the transmitted data fluctuates,
The clock cannot follow and input data cannot be identified and reproduced at the optimum timing. In particular, when the same code is continuous, the phase error is accumulated, so even a slight fluctuation is greatly affected. In other words, due to frequency error, phase error accumulates during the same-code consecutive period of input data, and the longer the homo-code consecutive period is, the larger the deviation from the optimal identification / timing becomes, and the identification error of the input data becomes larger. There is a problem that it will occur.

FIG. 15 is a timing chart showing an example in which the phase error is accumulated due to the frequency error during the same sign continuous period in the above-mentioned prior example.

In FIG. 15, when the frequency f of the voltage controlled oscillator 4 and the frequency f _{0 of the} input data match (f = f ₀ ), the oscillation frequency f is higher than the frequency f _{0 of the} input data ( f> f ₀ ), the oscillation frequency f is lower than the frequency f _{0 of the} input data (f <f ₀ ).

Frequency error (that is, the above frequencies f and f ₀
(F> f ₀ , f <f ₀ )), the phase error (f−f ₀ ) from the normal phase becomes large in the final bit when the same sign in the input data continues. That is, the phase error Δ after the same sign is consecutive due to the frequency error Δf
φ is represented by the following equation (n is the number of consecutive bits of the same sign). Δφ = (1 / Δf) × n On the other hand, the longer the time when the same sign of the input data continues, the larger the deviation from the optimal identification / timing, and eventually the identification error occurs. As a method for solving the problem, a PLL (Phase Lock Loop) for synchronizing the input data and the extraction clock
It is conceivable to use the method.

However, the conventional PLL cannot respond instantaneously to burst data whose phases are different from each other because it takes a long time to pull in the synchronization of the frequency and the phase. There is a problem that the optimum clock cannot be extracted by simply combining the conventional example of the extraction circuit with the conventional PLL.

According to the present invention, the clock can be instantaneously extracted from the burst input data, and even if the same sign of the burst input data continues for a long time, there is little deviation between the extracted clock and the optimum identification / timing. It is an object to provide an identification / timing extraction circuit.

[0016]

According to a first aspect of the present invention, there is provided a first gating circuit including a delay circuit, an exclusive OR circuit, and a logical inversion circuit, and the first gating circuit includes: A first voltage-controlled oscillator whose oscillation is controlled by a first gating signal that is output, and a first identification circuit that identifies burst input data based on a clock output from the first voltage-controlled oscillator. A second gating circuit that outputs a second gating signal when the rising edge of the burst input data is detected, and an oscillation controlled by the second gating signal. A voltage-controlled oscillator, a signal from which the clock frequency component of the burst input data is extracted, and a clock output from the second voltage-controlled oscillator. A phase comparator for comparing phases and a low-pass filter for removing a high frequency component of an output signal of the phase comparator are provided, and an oscillation frequency control terminal of the first voltage controlled oscillator and a second voltage controlled oscillator of the second voltage controlled oscillator are provided. An oscillation frequency control terminal is connected to the output terminal of the low pass filter.

According to a second aspect of the present invention, there is provided a first gating circuit including a delay circuit, an exclusive OR circuit, and a logical inversion circuit, and a first gate output by the first gating circuit. Oscillation controlled by the first signal
Of the burst input data, the identification / timing extraction circuit comprising the voltage controlled oscillator of 1) and the first identification circuit for identifying the burst input data based on the clock output from the first voltage controlled oscillator. A second gating circuit that outputs a second gating signal when detecting a signal, a second voltage controlled oscillator whose oscillation is controlled by the second gating signal, and a second voltage controlled oscillator that outputs the second gating signal. A second identification circuit for identifying the burst input data based on the clock
A phase comparator that compares the identification signal output by the first identification circuit with the identification signal output by the second identification circuit, and a low-pass filter that removes high-frequency components of the output signal of the phase comparator. The oscillation frequency control terminal of the first voltage control oscillator and the oscillation frequency control terminal of the second voltage control oscillator are connected to the output terminal of the low pass filter.

Further, the invention according to claim 3 has a sample hold switch for connecting the output of the phase comparator and the low-pass filter only when the phase comparison is input to the phase comparator.

[0019]

According to the present invention, a first gating circuit having a delay circuit, an exclusive OR circuit, and a logical inversion circuit, and a first gating signal output from the first gating circuit causes oscillation. Since the first voltage controlled oscillator to be controlled and the first discrimination circuit for discriminating the burst input data based on the clock output from the first voltage controlled oscillator are included, the clock is instantaneously extracted from the burst input data. In addition, since the phase comparison result is held by the low-pass filter and the first voltage controlled oscillator generates the clock based on the held contents, even if the same sign of the burst input data continues for a long time, There is little discrepancy between the extracted clock and the optimal identification / timing.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a first embodiment of the present invention.
It is a figure which shows timing extraction circuit TC1.

This identification / timing extraction circuit TC1 is
Clock gating circuit (first gating circuit)
10, a voltage-controlled oscillator with gating (first voltage-controlled oscillator) 4a, a burst PLL 11, and a first identification circuit 5a.

The clock gating circuit 10 outputs 1 when the sign of the burst input data Data in is changed.
It is a circuit that generates a pulse of / 2 cycle, and is configured by a 1/2 cycle delay 1a, an exclusive OR circuit 2a, and a logic inverting circuit 3. The first gating signal Gating # output by the clock gating circuit 10
1 is used as the gating input of the first voltage controlled oscillator 4a.

The burst PLL 11 includes a second burst gating circuit (second gating circuit) 6 and a voltage-controlled oscillator with gating (second voltage-controlled oscillator) 4.
b, 1/2 cycle delay 1b, exclusive OR circuit 2b
, A phase comparator 8 and a low pass filter 7. The first identification circuit 5a identifies the input data based on the clock output from the voltage controlled oscillator 4a.

The second gating circuit 6 is a circuit which detects the rising edge of the leading code of the burst input data Data in and outputs the second gating signal Gating # 2, and the voltage control with gating in the burst PLL 11 is performed. It controls the oscillation of the oscillator 4b.

The second delay circuit 1b is a circuit for delaying the burst input data Data in by ½ cycle of the transmission rate. The second exclusive OR circuit 2b is
It is a circuit that takes an EX-OR logic of two signals of the signal delayed by the delay circuit 1b and the burst input data Data in.

The phase comparator 8 compares the phase of the signal of the second exclusive OR circuit 2b and the phase of the signal of the second gating circuit 6. The low pass filter 7 removes a high frequency component of the output signal of the phase comparator 8.

The second voltage controlled oscillator 4b has an oscillation frequency control terminal and controls oscillation by the output signal of the second gating circuit 6. Further, the oscillation frequency control voltage terminal of the second voltage controlled oscillator 4b and the oscillation frequency control voltage terminal of the first voltage controlled oscillator 4a for generating the first clock are connected to the output terminal of the low pass filter 7. There is.

The clock gating circuit 10 is
6 is an example of a first gating circuit including a delay circuit, an exclusive OR circuit, and a logical inversion circuit. The voltage-controlled oscillator 4a is an example of a first voltage-controlled oscillator whose oscillation is controlled by the first gating signal output from the first gating circuit. The first identification circuit 5a is an example of a first identification circuit that identifies burst input data based on the clock output from the first voltage controlled oscillator.

The burst gating circuit 6 is an example of a second gating circuit that outputs a second gating signal when the rising edge of the leading code of the burst input data is detected. The voltage controlled oscillator 4b is an example of a second voltage controlled oscillator whose oscillation is controlled by the second gating signal. Furthermore, the phase comparator 8 is an example of a phase comparator that compares the phase of the signal in which the clock frequency component of the burst input data is extracted with the clock output from the second voltage controlled oscillator.

Next, the operation of the above embodiment will be described.

FIG. 2 is a timing chart showing the operation of the above embodiment.

NRZ (None-return-to-
Zero input burst input data Data in is delayed by the delay circuit 1a by a half cycle of the transmission rate,
This delayed signal and burst input data Data i
The exclusive OR circuit 2a EX-ORs the two signals with n.
The logic gating circuit 3 inverts this signal to obtain a clock gating signal Gating # 1.
Get.

That is, the clock gating signal Ga
The toning # 1 generates a 1/2 cycle pulse when the code of the burst input data Data in is switched, and when the burst input data Data in has the same code,
Sends "H" level.

Then, the clock gating signal Gat
ing # 1 is used as a control signal for stopping / starting the oscillation of the voltage controlled oscillator 4a, and the voltage controlled oscillator 4a outputs the clock CLK # 1. That is, burst input data D
When the sign of ata in changes, the voltage controlled oscillator 4
a outputs the clock CLK # 1 having a 1/2 cycle, and the clock gating signal Gating # 1 becomes the “H” level when the burst input data Data in has the same sign, the low-pass filter 7 operates during this period. Pulse with frequency corresponding to output voltage (clock CLK # 1)
Is output from the voltage controlled oscillator 4a. Then, by using this clock CLK # 1, the first identification circuit 5a performs data reproduction.

On the other hand, the delay circuit 1b and the exclusive OR circuit 2
b generates a clock pulse detection signal, and the phase of the clock pulse detection signal and the phase of the pulse output from the voltage controlled oscillator 4b are compared by the phase comparator 8, and the high frequency component in the signal of the comparison result is low-passed. A pulse having a frequency according to the output voltage of the low-pass filter 7 which is removed by the filter 7 is output from the voltage controlled oscillator 4b.

That is, the phase of the clock pulse detection signal corresponding to the phase of the input data and the phase of the output pulse of the voltage controlled oscillator 4b are locked so that the output voltage of the low pass filter 7 has no phase difference between the two comparison pulses. Maintained constant. The output voltage of the low pass filter 7 is maintained constant even when the burst input data Data in has the same sign.

The voltage-controlled oscillator 4b has the same circuit configuration as the voltage-controlled oscillator 4a for clocks, and as described above, the output voltage of the low-pass filter 7 is:
Since the burst input data Data in is kept constant even when the same sign continues, the voltage controlled oscillator 4a whose oscillation frequency is controlled by the output voltage of the low-pass filter 7 generates a clock having a constant frequency.

That is, the voltage controlled oscillator 4a generates a clock having a constant frequency even when the burst input data Data in has the same sign. Further, in this case, since the output voltage of the low-pass filter 7 is a clock having the same frequency as the clock detected from the burst input data Data in, the burst input data Data is output.
Voltage controlled oscillator 4a even when in has the same sign
Generates a clock that is not offset from the proper clock.

Further, since the voltage controlled oscillator 4b starts its operation at the same time as the rising edge of the burst input data detected by the gating circuit 6, the voltage controlled oscillator 4b can instantaneously extract the clock from the burst input data, and
The voltage controlled oscillator 4a can also instantaneously extract the clock from the burst input data.

Therefore, the clock CLK # 2 having the same phase as the burst input data is instantaneously obtained, which allows the burst PLL 11 to be longer than the pull-in time of the conventional PLL.
The pull-in time at becomes shorter.

Further, the oscillation frequency of the clock voltage controlled oscillator 4a allows an error with respect to the data rate to some extent, so that the identification clock can be extracted even during the pull-in period. That is, in the above embodiment, the gating signal Gating # 1 of the clock gating circuit 10 is used.
Since the identification and timing of the clock are determined by the phase of, the duty ratio of the clock is slightly deteriorated by the frequency error of the oscillators 4a and 4b, but a certain optimum identification point is maintained.

Next, the above identification / timing extraction circuit TC
The configuration of the identification / timing extraction circuit TC2, which is a modified example of No. 1, will be described.

FIG. 3 shows the identification / timing extraction circuit TC2.
FIG.

This identification / timing extraction circuit TC2 is
Burst PL in identification / timing extraction circuit TC1
A burst PLL 11a is provided in place of L11. The burst PLL 11a is a detection circuit for generating a clock pulse (pulse for phase comparison) from input data.
It is a circuit that shares a part of the clock gating circuit 10. That is, the phase comparator 8a compares the phase of the output signal of the exclusive OR circuit 2a in the clock gating circuit 10 with the output signal of the second voltage controlled oscillator 4b.

The identification / timing extraction circuit TC2 also performs the same operation as the identification / timing extraction circuit TC1.

FIG. 4 shows a voltage-controlled oscillator 4 with gating.
It is a circuit diagram which shows the specific example of a, 4b.

Voltage-controlled oscillators 4a and 4b with gating
Is composed of an odd number of logical inversion circuits 3 and an AND circuit 51, and has an oscillation frequency control voltage application terminal 52, an oscillation start / stop control voltage application terminal 53, and a clock output terminal 54. Oscillation frequency control voltage application terminal 52
Is connected to the output terminal of the low pass filter 7, and the oscillation start / stop control voltage application terminal 53 is connected to the output terminal of the clock gating circuit 10 or the output terminal of the burst gating circuit 6.

Voltage-controlled oscillators 4a and 4b with gating
Is based on a ring oscillator in which an odd number of logic inversion circuits 3 are connected. Further, by inserting the logical product circuit 51 in the loop of the logical inversion circuit 3, it is possible to easily realize the gating function. That is, one input of the AND circuit 51 is a loop of the ring oscillator, and the other input of the AND circuit 51 has a control signal Gating Signal for controlling oscillation / stop of the oscillator.
(Gating signal Gating # 1 or Gatin
g # 2) is applied. The voltage controlled oscillators 4a, 4
When "H" is input to the oscillation control terminal 53 of b, an oscillation loop is formed to oscillate, and conversely, when "L" is input to the oscillation control terminal 53 (burst input data is no longer detected), Since the logic product output level is fixed, the oscillation loop is disconnected and oscillation stops.

In the oscillators 4a and 4b shown in FIG. 4, the oscillation frequency can be controlled by applying a control voltage from the outside. That is, when controlling the oscillation frequency, for example, by connecting a current source to the logic inverting circuit 3 and adjusting this current source, the time constant of the transistor forming the loop changes, so the oscillation frequency changes.

FIG. 5 is an explanatory diagram of a specific example of the burst gating circuit 6, FIG. 5 (1) is a circuit diagram showing the burst gating circuit 6, and FIG. 5 (2) is a timing chart thereof. Is.

The burst gating circuit 6 is composed of a peak detection diode 61, a level hold capacitor 62, a reset FET 63, and an inverter amplifier (logic inverting circuit) 3.

As shown in FIG. 5A, the burst gating signal Ga output from the burst gating circuit 6 is output.
The toting # 2 is once reset to "L" by the reset signal Reset, and the burst input data Dat
When ain is detected, it goes to "H" and is held at "H" until the next reset signal Reset is received.

FIG. 6 shows another embodiment of the identification / identification
It is a circuit diagram showing a timing extraction circuit TC3.

The identification / timing extraction circuit TC3 includes a clock gating circuit 10, a voltage-controlled oscillator with gating 4a, an identification circuit 5a, and a burst PLL 11b.
It is composed of The burst PLL 11b includes a burst gating circuit 6, a phase comparator 8a, a low-pass filter 7, a voltage-controlled oscillator with gating 4b, and
It is composed of an inverter and an identification circuit 5b.

The identification / timing extraction circuit TC3 is similar to the identification / timing circuit TC1 in that the oscillator 4b of the PLL is used.
The second discrimination circuit 5b for discriminating the burst input data by the clock CLK # 2 outputted by the first discriminator 5a is newly provided. The phase comparator 8a compares the phases of # 2 and # 2, and the high-pass component of the phase comparison result is removed by the low-pass filter 7.

FIG. 7 shows the identification / timing extraction circuit TC3.
6 is a timing chart of FIG.

First, the clock gating signal Gati
ng # 1, burst gating signal Gating # 2
Is generated similarly to the case of the identification / timing extraction circuit TC1.

Then, the burst gating signal Gat
PLL whose oscillation start phase is controlled according to ing # 2
Data D identified and reproduced by the clock CLK # 2 of
EC # 2 and clock gating signal Gating #
Clock CL whose start / stop of oscillation is controlled according to 1
The phase comparator 8a compares the reproduction data DEC # 1 identified and reproduced by K # 1 in phase.

Therefore, the two input data for phase comparison basically have the same logic pattern. Therefore, when the data and the clock are compared, the phase caused by the difference in the logic patterns to be compared when the same code continues. Comparison error can be eliminated.

In the timing chart shown in FIG. 7,
Although an example of falling comparison is shown, as described above, the reproduction data DEC # 1 and DE that are input to the phase comparator 8a are
It has the same logical pattern as C # 2, and no logical phase error occurs. Therefore, the phase error when the same code is continuous is reduced, and the clock frequency holding characteristic is improved.

In the discrimination / timing extraction circuit TC3, the phase comparison error is smaller than that in the discrimination / timing extraction circuit TC1 because the phase comparison is performed only at the changing points without comparing the phases when the same signs are consecutive.

FIG. 8 shows another embodiment of the identification / identification
It is a block diagram showing a timing extraction circuit TC4.

The identification / timing extraction circuit TC4 includes a clock gating circuit 10, a voltage-controlled oscillator with gating 4a, an identification circuit 5a, and a burst PLL 11c.
It is composed of

The burst PLL 11c includes a burst gating circuit 6, a phase comparator 8b, a sample hold control circuit 90, a low pass filter 91 with a sample hold switch, and a voltage controlled oscillator 4b with a gating.
And a discrimination circuit 5b and a delay circuit 1c.

The identification / timing extraction circuit TC4 is newly provided with a second identification circuit 5b for identifying burst input data by the clock CLK # 2 by the voltage controlled oscillator 4b, and is provided with the first and second identification circuits 5a and 5b. A sample in which the phase comparator 8b compares the reproduction data DEC # 1 and DEC # 2 and delays the identification data DEC # 2 by T / 2, and the output signal of the delay circuit 1c and the burst input data. A hold control circuit 90 and a low-pass filter with a sample-hold switch 91 for turning on / off the connection between the phase comparator 8b and the low-pass filter 7a by a control signal of the control circuit 90 are provided.

Next, a concrete example of the low-pass filter 91 with a sample hold switch will be shown.

FIG. 9 shows the identification / timing extraction circuit TC4.
9A is a diagram showing a specific example of a low-pass filter 91 with a sample hold switch in FIG. 9, FIG. 9A is a diagram showing an example of the circuit configuration thereof, and FIG. 9B is a timing chart thereof.

The low-pass filter 91 with a sample-hold switch has a sample-hold control circuit 90, a sample-hold switch 92, and a low-pass filter 7a. The sample hold control circuit 90 inputs an exclusive OR circuit for inputting the burst input data Data in and the output data of the delay circuit 1c, and a logic for inputting the output of this exclusive OR circuit and the output data of the delay circuit 1c. And a product circuit. A normal CMOS switch is used as the sample hold switch 92, and a general lag / lead filter is used as the low pass filter 7a.

The sample hold control circuit 90 is shown in FIG.
As shown in (2), the sample hold switch 92 is turned on only when the phases are compared. Conversely speaking, since the sample hold switch 92 is turned off during the period other than the phase comparison, the capacitor forming the low pass filter 7a is opened in a circuit manner during the period other than the phase comparison. Therefore, the leak current does not flow, and the change of the oscillation frequency control voltage output from the low pass filter 7a is small,
The phase comparison error is further smaller than that of the identification / timing extraction circuits TC1 and TC2.

FIG. 10 shows the identification / timing extraction circuit TC.
It is a figure which shows the simulation result of No. 4.

An extracted clock corresponding to the burst input data is instantly obtained, and it can be confirmed that the identification data is reproduced by this extracted clock. By the burst gating PLL 11c, it is possible to obtain, together with the burst input data, comparison data having substantially the same phase from the beginning of the data. Further, the oscillation frequency control voltage Vref is held by the sample hold during the homo-code continuation period (“L” in the identification data) between bursts. Therefore, a clock having a constant oscillation frequency synchronized with the burst input data is transmitted. You can see that it is continuing.

In each of the above embodiments, the clock phase can be synchronized at the same time as the burst input data is received, and the code can be identified from the first bit of the burst input data. Furthermore, since the burst input data and the clock signal can be synchronized at high speed, the phase error in identification can be reduced and the homo-code continuity resistance can be improved. Furthermore, the PLL configuration eliminates the need for external components such as a reference oscillator, which enables a high-speed response of the identification / timing extraction circuit and high accuracy of the identification phase in a receiver that performs burst data transmission. Further, since the structure is easy, a general CMOS structure can be realized, which is effective in reducing the size and cost of the receiving circuit.

[0073]

According to the present invention, in the discrimination / timing extraction circuit, a clock can be instantaneously extracted from the burst input data, and even if the burst input data has the same sign for a long time, the extracted clock can be extracted. There is little difference between the optimal identification and timing.

[Brief description of the drawings]

FIG. 1 is a diagram showing an identification / timing extraction circuit TC1 according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment.

FIG. 3 is a diagram showing an identification / timing extraction circuit TC2.

FIG. 4 is a circuit diagram showing a specific example of voltage-controlled oscillators with gating 4a and 4b.

FIG. 5 is an explanatory diagram of a specific example of the burst gating circuit 6.

FIG. 6 is a circuit diagram showing an identification / timing extraction circuit TC3 which is another embodiment of the present invention.

FIG. 7 is a timing chart of an identification / timing extraction circuit TC3.

FIG. 8 is a block diagram showing an identification / timing extraction circuit TC4 which is another embodiment of the present invention.

FIG. 9 is a diagram showing a specific example of a low-pass filter 91 with a sample hold switch in an identification / timing extraction circuit TC4.

FIG. 10 is a diagram showing a simulation result of the identification / timing extraction circuit TC4.

FIG. 11 is a diagram showing a phase relationship between input data, a clock, and identification data.

FIG. 12 is a diagram showing an example of a burst transmission waveform.

FIG. 13 is a diagram showing a prior example of an identification / timing extraction circuit for burst transmission.

FIG. 14 is a timing chart in the above prior art example.

FIG. 15 is a timing chart showing an example in which a phase error is accumulated due to a frequency error during the same sign continuous period in the preceding example.

[Explanation of symbols]

1a, 1b, 1c ... 1/2 cycle delay circuit, 2a, 2b ... Exclusive OR, 3 ... Logic inversion circuit, 4a ... First voltage-controlled oscillator with gating, 4b ... Second voltage control with gating Oscillator, 5a ... 1st discrimination circuit, 5b ... 2nd discrimination circuit, 6 ... Burst gating circuit, 7 ... Low pass filter, 8, 8a, 8b ... Phase comparator, 10 ... Clock gating circuit, 11, 11a , 11b, 11c ... Burst PLL, 31 ... Reset terminal, 51 ... AND circuit, 52 ... Oscillation frequency control terminal, 53 ... Gating terminal, 90 ... Sample hold control circuit, 91 ... Low pass filter with sample hold switch, 92 ... Sample hold switch.

Claims (3)

[Claims] 1. A first gating circuit including a delay circuit, an exclusive OR circuit, and a logical inversion circuit, and the first gating circuit.
A first voltage controlled oscillator whose oscillation is controlled by a first gating signal output from the first gating circuit, and a first voltage controlled oscillator for identifying burst input data based on a clock output from the first voltage controlled oscillator. When the rising edge of the burst input data is detected in the identification / timing extraction circuit which is composed of an identification circuit,
A second gating circuit that outputs a gating signal of; a second voltage controlled oscillator whose oscillation is controlled by the second gating signal; and a signal in which a component of the clock frequency of the burst input data is extracted. And a low-pass filter that removes high-frequency components of the output signal of the phase comparator; and a phase comparator that compares the phase with the clock output from the second voltage-controlled oscillator. An identification, characterized in that the oscillation frequency control terminal of the oscillator and the oscillation frequency control terminal of the second voltage controlled oscillator are connected to the output terminal of the low pass filter.
Timing extraction circuit. 2. A first gating circuit including a delay circuit, an exclusive OR circuit, and a logical inversion circuit, and the first gating circuit.
A first voltage controlled oscillator whose oscillation is controlled by a first gating signal output from the first gating circuit, and a first voltage controlled oscillator for identifying burst input data based on a clock output from the first voltage controlled oscillator. When the rising edge of the burst input data is detected in the identification / timing extraction circuit which is composed of an identification circuit,
A second gating circuit that outputs a gating signal of; a second voltage controlled oscillator whose oscillation is controlled by the second gating signal; and a clock that is output by the second voltage controlled oscillator. A second discrimination circuit for discriminating the burst input data; a phase comparator for comparing the discrimination signal outputted by the first discrimination circuit with the discrimination signal outputted by the second discrimination circuit; A low-pass filter for removing high-frequency components of the output signal of the first voltage-controlled oscillator, and an oscillation frequency control terminal of the second voltage-controlled oscillator and an oscillation frequency control terminal of the second voltage-controlled oscillator. An identification / timing extraction circuit characterized by being connected to. 3. The discrimination / timing extraction circuit according to claim 2, further comprising a sample hold switch that connects the output of the phase comparator and the low-pass filter only when the phase comparison is input to the phase comparator. .