JPS59222951A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS59222951A JPS59222951A JP58098881A JP9888183A JPS59222951A JP S59222951 A JPS59222951 A JP S59222951A JP 58098881 A JP58098881 A JP 58098881A JP 9888183 A JP9888183 A JP 9888183A JP S59222951 A JPS59222951 A JP S59222951A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- parts
- thickness
- tips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ） 産業上の利用分野
この発明は、半導体装置用リードフレーム、特に８０端
子を超える多数の４’ｌ子をもった半導体装置に使用し
得る高密度実装用のリードフレームに関するものである
。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention is a lead frame for semiconductor devices, particularly a lead frame for high-density packaging that can be used for semiconductor devices having a large number of 4'l terminals exceeding 80 terminals. This relates to lead frames.
（ロ） 従来技術
従来、半導体％ ｉｔにおいては、第１図に示すような
リードフレームが使用されている。このリードフレーム
は、フレーム１の中央部に半導体装置を載せるためのタ
ブ２を設け、そのタブ２に向けて多数のリード３を設け
たものであり、リード３の先端と半導体装置田」に・フ
イヤボンテ゛イングが施され、串気的’Ｊ ’＋Ｄ続が
行なわれる。(b) Prior Art Conventionally, a lead frame as shown in FIG. 1 has been used in semiconductor manufacturing. This lead frame has a tab 2 in the center of a frame 1 for mounting a semiconductor device, and a large number of leads 3 facing the tab 2. Fire bonding is applied, and a ``J'' + D continuation is performed.
リード８は半導体装置とともに樹１指モールドされるイ
ンナーリード部３ａと、樹脂モールド外において背向側
へ屈曲されプリント基板に差１＾まれるアウタリード部
３１〕とから成る。The lead 8 consists of an inner lead part 3a which is molded together with the semiconductor device, and an outer lead part 31 which is bent backwards outside the resin mold and is attached to the printed circuit board.
」二記・；「Ｌ造のリードフレームは、量産性に優れ、
外１３にとの接続の信Ｊ、、Ｑ’４４Ｊ：、か胚い利点
かあり、従来約８０端子までの半導体装置に使用されて
いる。”2: “The L-shaped lead frame has excellent mass productivity.
J, Q'44J: It has many advantages in connection with external terminals and has been conventionally used in semiconductor devices with up to about 80 terminals.
ヒ９ 発明によって解決しようとする問題点」二記のリ
ードフレームは、打抜六法又はフォトエツチング法によ
って動作されるが、いずれの方法による場合も材料の４
７１’！ ｉｆより小さい間隙を安ｊｒシて精１島よく
あけることは困′！ゴ１てあり、現状では’ｈ Ｆ￥
０．２５ ｍｍで、リード１ｆｊ１の１ｉＪＪ １（Ｍ
は強開−ヒ０．２ＯＮｎか赴艮度である。H9. Problems to be Solved by the Invention The lead frame described in 2. is operated by the six punching methods or the photo-etching method, but in either method, the material is
71'! It is difficult to easily open a gap smaller than if! There is a Go1, and currently 'h F￥
0.25 mm, lead 1fj1 1iJJ 1(M
is a strong opening of 0.2ONn or a degree of force.
一方、半導体素子の集積度が屈まるに伴い、在］極）′
蕾子勢′が坩１大し、これに対応できるリードフレーム
か要求されるか、従来のリードフレームによってこれに
対処しようとすれば、会４本のサイズを犬キくシてリー
ド数を琳１大せさるをえなかった。On the other hand, as the degree of integration of semiconductor devices decreases,
If the size of the flower buds is 1 large, and a lead frame that can accommodate this is required, or if you try to deal with this with a conventional lead frame, you will need to increase the size of the buds by increasing the number of leads by increasing the size of 4 buds. I didn't catch a single big monkey.
そこで、この発明は全１．ドのサイズを左程太きくしな
いで８０端子以上の半導体装置に対応できるリードフレ
ームを僅供することを目的とするものである。Therefore, this invention has a total of 1. The object of the present invention is to provide a lead frame that can accommodate a semiconductor device having 80 or more terminals without increasing the lead size too much.
に） 問題点を解決するための手段
上記の目的を達成するために、この発明はリードフレー
ムにおけるリードの厚さをリード先端に至るに従い次第
に薄くなるように形成したものである。B) Means for Solving the Problems In order to achieve the above object, the present invention is such that the thickness of the leads in the lead frame is formed so that it gradually becomes thinner as it reaches the tips of the leads.
リードをこのように形成すると、リード先端部において
リード＝ｊの間隙を従来より小さくすることができると
ともに、リード基部においては十分な強度をもたせるこ
とかできる。By forming the lead in this manner, the gap of lead=j can be made smaller at the lead tip than in the past, and sufficient strength can be provided at the lead base.
（ホ） 実施例
第２図はこの発明のリードフレームを使用して製作した
半導体装置の一例である。(E) Embodiment FIG. 2 shows an example of a semiconductor device manufactured using the lead frame of the present invention.
インナーリード部３ａの先端に金又は銀メッキ４を施し
、そのメッキ４の月ζ分とタブ２」二に固着した半導体
素子５とをボンディングワイヤ６により接続し、これら
の部分に樹脂モールド７を施し一体化している。Gold or silver plating 4 is applied to the tip of the inner lead portion 3a, and the portion of the plating 4 is connected to the semiconductor element 5 fixed to the tab 2'' by a bonding wire 6, and a resin mold 7 is attached to these parts. Almsgiving is integrated.
茅３メ１は」二記リード３及びタブ２の拡大）衝面１ｙ
１である。第２〆１及び第３凶かられかるように、リー
ド、づは先端に至るに従い次第にトカくなるように形成
されている。また、第３区１の場合のリード３は、銅又
は調合金相８の上下に、鉄・ニッケル合金層９．９を設
けた積層体によって形成したものを示しているが、銅又
は鋸合金の重層又は′妖・ニラ・１ル合金の止−で形成
してもよい。Kaya 3me 1 is 2ki lead 3 and tab 2 enlargement) impact 1y
It is 1. As can be seen from the second and third ends, the lead is formed so that it gradually becomes tighter as it reaches the tip. In addition, the lead 3 in the case of Section 3 1 is shown as being formed of a laminate in which iron-nickel alloy layers 9.9 are provided above and below a copper or prepared alloy phase 8, but It may be formed by a multilayer of or a layer of an alloy of chives, chives, and aluminum.
また、秩・ニッケル合金層の場合、これを三層に分け、
上下両層においてはニッケルの割合を３５〜５０％とす
ることによつ゛Ｃ半尊体素子と熱膨少特性を合わせ、ま
た中１．４１１においては；伏の割合を５０％を超え′
るようにすることにより、コストを低ｉｒｎ＆ Ｌ、ま
た熱伝尊苓を同上することができる。In addition, in the case of Chichi-nickel alloy layer, it is divided into three layers,
By setting the proportion of nickel in both the upper and lower layers to 35 to 50%, the thermal expansion characteristics are matched with those of the C half-piece element, and in the case of 1.411, the proportion of nickel is made to exceed 50%.
By doing so, the cost can be lowered and the heat transfer rate can be reduced.
−１−記のようなリード３を荷するリードフレームは、
４ｔ 鋳（エレクトロフォーミング）によって製作する
ことができる。Ｉｆ、 Ｗｆは、基体となる＋ｉＪ（四
Ｊ二に所！々厚さをもって所要の金属めっきを施し、そ
の後に母型からめつき部分を剥肉１トシてす品とする手
段をいい、めっき厚を任意にコントロールすることによ
り、任意のＪνさをもった製品を得ることかできるもの
である。The lead frame carrying the lead 3 as shown in -1- is
It can be manufactured by 4t casting (electroforming). If and Wf refer to the method of applying metal plating to the required thickness of +iJ (4 J 2!) as the base, and then stripping the plated part from the matrix to make the product, and the plating thickness By arbitrarily controlling Jν, it is possible to obtain a product with an arbitrary Jν value.
蘭鋳により、上記のリードフレームを製作するには、ま
ずリードフレーム全体の母型を作成し、その母型上にイ
ンナーリード部３ａの先端部に要求される板厚まで隔鋳
を行ない、その後インナーリード部３ａの先端部をマス
クし、アウターリード１３ｂで要求される板厚まて７η
鋳を行ない、マスクおよび母型から剥離することにより
、所要のリードフレームを得ることができる。To manufacture the above lead frame by orchid casting, first create a master mold for the entire lead frame, perform interval casting on the master mold to the thickness required for the tip of the inner lead part 3a, and then cast the inner lead frame. The tip of the lead part 3a is masked, and the plate thickness required for the outer lead 13b is 7η.
A desired lead frame can be obtained by performing casting and peeling from the mask and matrix.
また、インナーリード部に３ａにマスクを被せる方法に
代えて、第４図に示すような、孔１０のあいた陽極１１
を用い、孔１０部分にインナーリード部：３ａを対向さ
せて…鋳を行なうことにより、アウターリード部３ｂか
らインナーリード部３ａにかけて次第に薄くなるめっき
層を形成することができる。Moreover, instead of the method of covering the inner lead part with a mask 3a, an anode 11 with a hole 10 as shown in FIG.
By performing casting with the inner lead portion 3a facing the hole 10 portion, a plating layer that gradually becomes thinner from the outer lead portion 3b to the inner lead portion 3a can be formed.
なお、インナーリード部３ａの先端やタブ２ヒにＪｒｌ
ｆｌｉず金や年の部分めっ：８ψＬ理は゛トガ坊の最終
屏′ｌハ″において由ｌノ「にｊ里扁：した工程として
行なうことかできる。In addition, Jrl is attached to the tip of the inner lead part 3a and the tab 2hi.
The 8ψL process can be performed as a step in the final screen of Togabo.
θ（に、ｔ ２ ｄ 、１＜のリードを有するリードフ
レームの具体的な）１ノ造方法を説明する。A specific method for manufacturing a lead frame having leads of θ (with, t 2 d, 1<) will be described.
１１ ’、 秩・ニッケル中層のｉノ５合〕１ｒ：ト
イ・−；４炊として、嘩ビ３ノ昌１＞１．−べの（？１
１凋（１を４夢Ｉにするため鏡面仕上すしたステンレス
（４７１を１吏用し、その面にフォトレジスト法により
所要の陰極パターンを形成した。陽極として、昂−７４
し１に示すように、インナーリード部に対応する部分に
孔を設けた４２％ニッケル・鉄合金板を使用した。11', Chichi/nickel middle layer i-5 go] 1r: Toy -; 4 cooking, Kenbi 3 no Sho 1 > 1. -Beno(?1
In order to change 1 to 4 Yume I, one piece of mirror-finished stainless steel (471) was used, and the required cathode pattern was formed on its surface by photoresist method.
As shown in Figure 1, a 42% nickel-iron alloy plate with holes provided in the portion corresponding to the inner lead portion was used.
スルフｒミント１ヶ浴によす、ニッケルを４０〜５０％
にコントロールした鉄・ニッケル合４＞めっき層・をｊ
ｌｇ、 ｈ側にＩ；イ為させた。このときのめっき厚は
、インナーリード）」≦で０．０５〜０．０７ Ｔｕｎ
、 アウターリード部てｏ、１３〜０．１５ｍであっ
た。1 bath of sulfur mint, 40-50% nickel
Iron-nickel mixture controlled to 4> plating layer
I made the lg and h sides do I; The plating thickness at this time is 0.05 to 0.07 Tun
The outer lead portion was 13 to 0.15 m.
ｆｊお、に記の山、’ＩＪ？イサ、インナーリードａＢ
に対応した１１１５分にのみ呆４１米のごとき孔を設け
たアクリル侍ｉ脂板を陰祠ノ砂に！４１ね、シアン浴に
よりインナーリード部先端（ζづめつきを施した。fj O, Niki no Yama, 'IJ? Isa, inner lead aB
An acrylic samurai plate with a hole like 41 rice only for 1115 minutes corresponding to the shadow shrine sand! Step 41: The tips of the inner leads (ζ-stamps) were applied in a cyan bath.
（２）〔積層体の場合〕
陰極は上記１と同様。第１回目の（６ｍにおいて、陽ｈ
ｐとして鉄・ニッケル合金槻を使用し、陰極側にニッケ
ルを４０〜５０％にコントロールした０、０１５〜０．
０２０ｘの鉄・ニッケル台金層を全面均一に噸希させた
。次に、第２回目の゛串鋳において、第４ν１に示すこ
とき孔のあいたリン脱談銅板を陽極とし、硫酸銅浴にて
１１）鋳を行ない、インナーリード部の累積めつき厚０
．０３〜０．０５馴、アウターリード部の累積めつき厚
０，１１〜０．１４ｍｍをｆ尋た。案６３１゜（７）目
の作工鋳を第１回目と同様に行ないイン六−リード都の
累積めつきＩｄ ０．０５〜０．０７ｍｍ、アウターリ
ード部の累積めっき層０．１３〜０．１５圏の三；−構
造のリードフレームを作成した。(2) [In case of laminate] The cathode is the same as in 1 above. The first time (at 6m, positive h
0, 015 to 0.0, using an iron-nickel alloy as p, and controlling nickel to 40 to 50% on the cathode side.
The 020x iron/nickel base metal layer was uniformly diluted over the entire surface. Next, in the second skewer casting, 11) casting was carried out in a copper sulfate bath using the perforated phosphorus-removed copper plate shown in No. 4v1 as an anode, and the cumulative plating thickness of the inner lead part was 0.
．． 03 to 0.05 mm, and the cumulative plating thickness of the outer lead portion was 0.11 to 0.14 mm. The work casting of Plan 631° (7) was carried out in the same manner as the first time, and the cumulative plating Id of the inner lead was 0.05 to 0.07 mm, and the cumulative plating layer of the outer lead was 0.13 to 0. 15 Circle 3: - Created a lead frame for the structure.
（ハ）効果
り、上述へたように、この発明のリードフレームは、リ
ードの厚さをリード先端に至るに従い薄くなるよう形成
したことにより、アウターリード部における強閾を低下
することなく、インナーリード部の１１４］隙及びピッ
チを従来の場合より小さく形成できるので、集λａぽか
高く、したがって４１！１子数の多い半−爪木素子に使
用することかできる。(c) Effects: As mentioned above, the lead frame of the present invention is formed so that the thickness of the leads becomes thinner toward the lead tips, so that the strong threshold at the outer lead portion is not reduced, and the inner Since the gap and pitch of the lead portion can be made smaller than in the conventional case, the concentration λa is relatively high, and therefore it can be used in a half-claw wood element with a large number of 41!1 children.
なお、この発明のリードフレームを用いた半導体装置の
大きさく月止耐脂の平面形状）の−列を従来例との比較
で示せは次のとおりである。The comparison of the size and planar shape of the semiconductor device using the lead frame of the present invention with the conventional example is as follows.
従来の８０ピンの場合 １５Ｘ２０■
この発明の１２８ピンの場合： １ ｄＸ２２柳従来法
による１２８ピンの場合：２４×３２＋肌In the case of conventional 80 pins: 15X20 ■ In the case of 128 pins of this invention: 1 dX22 Yanagi In the case of 128 pins according to the conventional method: 24 × 32 + skin
、？４３１図は従来のリードフレームの平面１メＬ第２
図はこの発明のリードフレームを使用して一作した半導
体装置の閉面ｔ〆１．第３図はこの発明の場合のリード
の４広大所而Ｕ：、１、第４［Ｙｌは陽イ・；ｐ伽の拡
大斜視Ｉズ１である。
１ ・・フレーム、？・・タブ、３・・・リード、３ａ
・・・インナーリード部、３ｂ・・・アウターリード部
。,? Figure 431 shows the conventional lead frame 1 meter L 2nd plane.
The figure shows the closed surface of a semiconductor device manufactured using the lead frame of the present invention. FIG. 3 is an enlarged perspective view of Reed's four vast locations U:, 1, and 4 [Yl is positive. 1...Frame? ...Tab, 3...Lead, 3a
... Inner lead part, 3b... Outer lead part.
Claims (1)
を設けた半碑１太装置用リードフレームにおし）で、リ
ードの厚さをリード先端に至るに従い次第にＡｌ１：
くなるよう形成したことを特徴とする半導体装置用リー
ドフレーム。 （２） 上記リードの先端部を含むインナーリード部
をその先端に至るに従いアウターリード部より次第に７
咋くなるよう形成したことを特徴とする特許請求の範囲
第１項に記載の半導体装置用リードフレーム。 （３） 上記のリードフレームをｂＫ ｇＪｆにより
形成したことを特徴とする特許請求の＋１４１４囲弔１
項又は第２項に記載の半畳）・ド装酋用リードフレーム
。 ｌ４）１−記リードを鉄・ニッケル合金により形成し、
」二Ｆ １１１１Ｊ１４ニア ｉこおいては二′ノケル
の去す合を３５・〜５０％以ド、申出１層において鉄の
割合を５０％を超えるようにした特許請求の範囲病３３
項に記載の半導体装置用リードフレーム。 （５） 上記リードを異種合間の積（（２）体により
形成したことを特徴とする特許言青求の範囲第３項に記
載の半導体装置用リードフレーム。[Scope of Claims] (1) A lead frame for a device with multi-source leads provided with required gaps in the frame), the thickness of the leads is gradually increased from Al1 to the lead tip. :
A lead frame for a semiconductor device, characterized in that the lead frame is formed so as to have a shape. (2) Gradually move the inner lead part, including the tip of the lead above, to the outer lead part until it reaches the tip.
The lead frame for a semiconductor device according to claim 1, wherein the lead frame is formed to be flexible. (3) +1414 Enclosure 1 of patent claim characterized in that the above lead frame is formed of bK gJf.
The lead frame for half-tatami (half-tatami) and do-sho (half-tatami mats) and do-shoki as described in paragraph (2). l4) 1- The lead is formed of an iron-nickel alloy,
2F 1111J14 Near i In this case, the proportion of iron in the first layer is set to exceed 50%, and the ratio of iron in the first layer is set to exceed 50%.
A lead frame for a semiconductor device as described in . (5) The lead frame for a semiconductor device according to item 3 of the patent claim, wherein the lead is formed of a product of different types ((2)).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58098881A JPS59222951A (en) | 1983-06-02 | 1983-06-02 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58098881A JPS59222951A (en) | 1983-06-02 | 1983-06-02 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59222951A true JPS59222951A (en) | 1984-12-14 |
Family
ID=14231494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58098881A Pending JPS59222951A (en) | 1983-06-02 | 1983-06-02 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59222951A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0204102A2 (en) * | 1985-06-03 | 1986-12-10 | Motorola, Inc. | Direct connection of lead frame having flexible, tapered leads and mechanical die support |
| JPS63173351A (en) * | 1987-01-13 | 1988-07-16 | Toshiba Corp | Lead frame of semiconductor device |
| JPH04114460A (en) * | 1990-09-04 | 1992-04-15 | Mitsui High Tec Inc | Lead frame and manufacture thereof |
| EP0778618A3 (en) * | 1992-12-23 | 1998-05-13 | Shinko Electric Industries Co. Ltd. | Lead frame and method for manufacturing it |
| US5973388A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe |
| US7102216B1 (en) * | 2001-08-17 | 2006-09-05 | Amkor Technology, Inc. | Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making |
-
1983
- 1983-06-02 JP JP58098881A patent/JPS59222951A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0204102A2 (en) * | 1985-06-03 | 1986-12-10 | Motorola, Inc. | Direct connection of lead frame having flexible, tapered leads and mechanical die support |
| EP0204102A3 (en) * | 1985-06-03 | 1987-11-19 | Motorola, Inc. | Direct connection of lead frame having flexible, tapered leads and mechanical die support |
| JPS63173351A (en) * | 1987-01-13 | 1988-07-16 | Toshiba Corp | Lead frame of semiconductor device |
| JPH04114460A (en) * | 1990-09-04 | 1992-04-15 | Mitsui High Tec Inc | Lead frame and manufacture thereof |
| EP0778618A3 (en) * | 1992-12-23 | 1998-05-13 | Shinko Electric Industries Co. Ltd. | Lead frame and method for manufacturing it |
| US5909053A (en) * | 1992-12-23 | 1999-06-01 | Shinko Electric Industries Co. Ltd. | Lead frame and method for manufacturing same |
| US5973388A (en) * | 1998-01-26 | 1999-10-26 | Motorola, Inc. | Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe |
| US7102216B1 (en) * | 2001-08-17 | 2006-09-05 | Amkor Technology, Inc. | Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making |
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