JPS5922286A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up operation, by using three or more comparison potential values by sense amplifiers and discriminating an output from the sense amplifier in accordance with the charge/discharge of row/line potential. CONSTITUTION:Comparison potential values V1, V2, V3 are set up on the basis of the potential of a node S as shown in the figure. When the potentia of S>V1, A=''1'' and A'=''0'' are set up in the sense amplifier. To other sense amplifiers, the same manner is applied, If S>V1 when the node S is turned from ''0'' to ''1'', ''1'' is detected and outputted. If S<V3 when S is turned from ''1'' to ''0'', ''0'' is detected. Consequently, the time crossing the comparison potential with the potential of S is increased, the speed of the operation can be increased. Even if the node S is discharged to ''0'' at a point exceeding the V1, the potential is discriminated as ''0'' if reducing lower than the V2. When the node S exceeds V2 once and then drops lower than the V2 again, high speed operation is avilable even if the operation shown by the figure is generated because the V2 level exists near the node S by providing the potential V2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory that operates at high speed.

[Technical background of the invention and its problems]

FIG. 1 shows the structure of a general information read-only semiconductor memory ROM. In the figure, 1 is a column decoder, 2, 2 . ... is the column line, 33, ...
is a MOS transistor for column selection, 4 is a row decoder, and 5 is a row decoder.
959... is a row line, 6,6. ... is 5'e5 in each line
+ MOS that becomes the Mumori cell driven by...
) transistor, 7 is a MOS for the load to charge each column line 2゜2, ...) transistor, 8 is a sense amplifier with an output buffer function, and the transistor 3.6 is an enhancement type transistor. However, a depletion type transistor is still used as the transistor 7.

The operation of the ROM having such a configuration is as follows. First, the column decoder 1 selects an arbitrary column selection transistor 3. On the other hand, when an arbitrary row line 5 is selected by the row decoder 4, one transistor 6 located at the intersection of the column line 2 and the selected row line 5 is driven by the row line 5, and the sense point S and Column line 2 is charged or discharged depending on the information stored in transistor 6. Then, the sense amplifier f8, which also has an output buffer function and is connected to the sense point S, detects the potential of the column line 2 and outputs the memory information of the selected memory cell transistor 6. Information on the memory cell MOS transistor 6 is determined depending on whether its drain is connected to the column line 2 or not.

For the gold stone decoder and column decoder, the drain is connected to column line 2.
It is assumed that the memory cell MOS transistor 6 connected to the memory cell MOS transistor 6 is selected.
is discharged through. If a memory cell MOS transistor 6 whose drain is not connected to a column line is selected, the column line 2 and the sense point S are charged by the transistor 7. In this way, the sense amplifier/capuffer 8 detects whether the column line is in a discharged state or a charged state depending on the selected memory cell, and the stored information is "0".
”, outputs “1”.

By the way, in the above ROM, the load transistor 7
If the conduction resistance of
Charge 1β2 quickly. However, this transistor 7
hinders the discharging operation of the column line 2, so if the conduction resistance is small, the discharging speed of the column line 2 becomes slow. Column line 2 like this
When charging, it is desirable that the conduction resistance of the transistor 7 be small, and when discharging, it is desirable that it be large, but it is not possible to satisfy both at the same time. Therefore, it is necessary to compromise on the charging/discharging time of the column line 2 within an allowable range.

Conventionally, the sense amplifier 8 that detects the potential of the column line 2 is
Since the intermediate potential between the potential corresponding to the low logic level and the potential corresponding to the high logic level of column line 2 is fixed as the sense potential, for example, in the case of HA where the high logic level is +5V and the low logic level is QV, Since +2.5 V is set as the sense level, it takes a long time for the column line potential to reach the above sense level when charging and discharging the column line 2. Therefore, in the past, the information read speed was slow, and high-speed operation was required. The disadvantage is that it cannot be done.

Also, even if you set the sense level to a level other than +2.5V, since the potential at one point is set as the sense level, the detection of the discharge level will be delayed if the charge can be detected quickly, and if the discharge can be detected quickly, the sense level will be delayed. There was only a delay in detecting the charge level.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device capable of high-speed operation.

[Summary of the invention]

In order to achieve the above object, the present invention provides at least three sense amplifiers that respectively compare the potential of a column line with a comparison potential and detect the level of data in a memory cell, and A means is provided for determining data from the memory cell using one of the sense amplifiers depending on the memory cell.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows the sense point S in Figure 1 and the comparison potential V, +Vl.
+ Sense amplifier 1 that detects data by comparing V3
1.12.13, and FIGS. 3 and 4 show the transistors 21 to 38 and 41 to 5 that determine data from the memory cell 6 using one of the sense amplifiers depending on the potential of the column line.
This figure shows a logic circuit consisting of 3 elements, and the output is obtained at Z.

As shown in FIG. 5, the comparison potentials include data from the memory cell, that is, a potential V1 that is slightly higher than the low level of the potential of the node S, an intermediate potential V2 between the low level of the node S and the high level of the node S, and the potential V2 of the node S. ' Potential v3 slightly lower than the high level of potential
The sense amplifier 1 compares the potential of the node S with vI.
Compare, when the potential of S > V sO, A=゛1”, A=”0”
Make it.

Similarly, the sense amplifier f12 is B- when the potential of S > V xQ
1", B=-0". The sense amplifier 13 sets C="1" and d="0" when the potential of S>V3.

A circuit formed in this manner operates faster than a conventional circuit with one comparison potential. For example, when the node S changes from the "0" level toward the "1" level, if S exceeds the potential of vl, it is detected as the "1" level, and the output Z is set to "1". When S changes from the "1" level to the "0" level, if S falls below the potential of v3, it is detected as the "0# level. Therefore, conventionally, the time at which the comparison potential and the potential of S intersect is As shown in Fig. 5, the potential v2 is provided to speed up the data detection time even when the node S shows such a change. Even if S is discharged to the "0" level when it exceeds the potential of V, it is judged to be the "0" level if it drops by 2. In this way, the potential v2
By providing , the node S becomes V! V again after crossing the
, since the v2 level is nearby, high-speed operation is possible even when the operation shown in FIG. 5 occurs. Note that in this example, three types of comparison potentials are provided, but the more potentials there are, the faster it is possible to deal with noise-like thieves as shown in FIG.

FIGS. 2 to 5 will be explained in more detail.

Suppose that the switching node S is at the ``0'' level.In this case (a)
A=“0”, B-“0”, c=”0”, f,=”1”
.

fl="0", 〒2=11', f2=@O", z=
Data reading is performed with υ as "O" and output 2-"0".

Next, suppose that the node S is gradually charged and exceeds the potential of "I".At this time, (b) A - "B, B = "0", c
=”o”, 〒1 give: 1”.

Since fl="0", f2="1"+r,, =O, the logic section 61 in FIG.
It is read as "1". Here, since vl is a low value, it outputs 2-"1" even after being charged a little, and the operation is accelerated.

Next, if node S exceeds the potential of v2 (c) A=
@1”, B="1", C="O" 1 f l="1"
rf1=”o”t, =@Q#, r, =
== will Therefore, the logic section 62 in FIG. 4 is established and 2="1".

Assume here that the node S has fallen below the 'center point' of v2 as shown in FIG. At this time) A=”1”t B=-0”, C=”0’*
t, -61#1, f1=-QN, 〒2=″0″, f
2 = "l', so the logic parts 61, 62, 63 in Fig. 4
Both are true, and -f Z = "0" is reached. In this way, the data of the sense amplifier 12 is applied to the output 2, and Z=
Although it becomes ``0'' and the change in node S is quickly detected.
It is. When the node S exceeds the potential of v3 from the state (c) above, (e) A = "l", B = "l', C = "l'
″+ fl =”0’ + fl = “1”, 〒2 = “0”
, f2="1", so the logic part 63 is established and z=゛1
”, and Z remains at “1”.

Next, if node S becomes lower than the potential of v3, (to) A-“1”, B=“1”, C=-0”
, f□=”02°f1=”1″, 12=”0″
, f2 is "1", so none of the logic units 61 to 63 is established and Z="O", and Z="0" is quickly read out.

Next, if node S falls below the potential of V2, ())
A=″1″, B=1#
, C= “0” r fl ””
1″.

Since fl-"0"l, t, = "0" and f2-"l", none of the logic parts 61 to 63 is established, and z-"o".

Note that the present invention is not limited to ROM, but also RAM (Random Aecess Memory).
), the memory cells are usually made up of cross-coupled flip-flops 0, so that read data from the memory cells can be obtained as an output Q and its inverted data. And this Q,
Q becomes a pair of inputs of the sense amplifier.

Suppose that the data is being read from a memory cell in which data with Q = "0" is stored.Next, another memory cell is selected, and the data stored in this memory cell is changed to Q = "0". If Q is “0” and Tsukasa is “1”, then Q is “1”.
They will be discharged from "0" to "0", and each will be charged from "0" to "1". Therefore, where Q and Q intersect, the potential of Q decreases and the potential of each other increases, and Q
, immediately after the potentials of Q match (for example, the midpoint between Q or the same high potential level and low potential level), new data will be read at the point where the potentials of each other become lower than the potential of Q. Become. In this way, conventionally, data was read at approximately the midpoint between the high potential level and the low potential level of Q.

- When applying the power tree invention, only one data Q needs to be used. For example, the output Q may be inputted to S in FIG.

In this way, vl and V3 are set to a potential slightly higher than the low level of the potential of the node S, and a potential slightly lower than the high level of the potential of the node S, respectively. The data in the memory cell can be detected by a slight change in the potential of S, and the data read speed in the RAM is faster than in the conventional example.

Still, v2 is Q, that is, the low level of the potential of node S,
Since it is set in the middle of the brightness level, the data reading speed of υ will never slow down compared to the conventional example, and it will be more resistant to noise operations.

〔Effect of the invention〕

As explained above, according to the present invention, by using three or more comparison potentials from the sense amplifier and determining the output from the sense amplifier according to the charging and discharging of the column line, it is possible to achieve high-speed operation and reduce noise. Therefore, it is possible to provide a semiconductor memory that is strong in physical operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a ROM, FIG. 2 is a block diagram of a sense amplifier section according to an embodiment of the present invention, FIGS. 3 and 4 are diagrams showing a logic circuit section of the same embodiment, and FIG. FIG. 6 is a diagram showing how the column line potential changes in the same embodiment. 2...Column m, 6...Memory cell, 11-13...
Sense amplifier, 21-53...transistor. Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) A memory cell, a column line that receives data from the memory cell, and at least three sense amplifiers that compare the potential of this column line with a comparison potential and detect the level of data in the memory cell. and means for determining data from the memory cell using any one of the sense amplifiers according to the potential of the column line. (2) The means is for determining whether the potential of the column line υ is in a discharging direction or in a charging direction, based on a potential comparison result in the sense amplifier, and determining data from the memory cell. The semiconductor memory according to item 1.