JPS5922285B2 - information storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information storage device, and particularly to a magnetic storage device such as a magnetic disk or a floppy disk.

As shown in Figure 1, the recording surface of a magnetic disk or flat-topped disk (hereinafter simply referred to as a disk) consists of several tracks 2 that are concentric with the center of the disk 1, and these tracks are divided into several parts. Sector 3
It consists of

This sector also consists of an address part 4 in which a sector address is stored and a data part 5 in which data is stored, as shown in FIG. In the middle part there is a space 6 called a gap. An address marker 7 indicating that it is an address section is recorded at the beginning of the address section 4, and an address marker 8 similarly indicating that it is a data section is recorded at the beginning of the data section 5. Now, when trying to read data in a certain sector on a specific track, first search for the address part 4 of the target sector 10, and then, when it is found, move the address marker 8 to read the data part 5 of that sector. Start searching. However, if for some reason the rear address marker 8 is not found and the address part 14 of the next sector 11 is detected,
If address parts 4 and 14 are detected consecutively, the conventional circuit system defines this as an error. However, for some reason, address marker IT in address section 14 of sector 11 could not be detected, and data section 1
5 address markers 18 may be detected. In this case, the control circuit is originally searching for the data portion of sector 10, but it misidentifies the data portion 15 of sector 11 as the desired data and starts reading.
If this is read correctly, there is a drawback that no error is displayed even though the data portion has been misidentified. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an information storage device that detects an error if the data check of the data section is not completed within a certain period of time, and can properly perform error detection on a sector-by-sector basis.

Accordingly, in the present invention, a plurality of sectors are arranged consecutively,
Each sector has an address part and a data part.
This is realized in an information storage device in which the data portions are read in order. That is, it has a clocking means for performing a timekeeping operation, a detection means for detecting at least an address marker attached to the data section of each sector, and a data analysis means for checking the data of the read data section. When the address marker is detected, the time measuring means starts the time measuring operation, and after the address marker is detected by the detecting means, the data in the data section is loaded into the data analyzing means, and the time measuring means calculates a certain period of time. If the data check operation is not completed by the time the clock is counted, an error is generated. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing a control logic circuit of an information storage device according to an embodiment of the present invention.

The relationship between the data format on the disk shown in FIG. 2 and the function of the logic circuit shown in FIG. 3 will be explained below. A read signal 20 read from the disk 1 is applied to an address marker detection circuit 21, a target address detection circuit 23, and an AND gate 27. The address marker detection circuit 21 is a circuit that detects address markers 7, 8, 17, and 18 in the read signal 20. When this circuit 21 detects a signal corresponding to the address marker 17 of the address section 4, 14 in each center 10, 11, the address marker detection signal 22 becomes true.
When a signal corresponding to the address markers 8, 18 of the data portions 5, 15 is detected, the address marker detection signal 28 becomes true. Then, the signal 22 is applied to the target address detection circuit 23, and the signal 28 is applied to the AND gate 26. The target address detection circuit 23 detects whether the addresses in the address sections 4, 14 are the target addresses or not. Upon receiving the address marker detection signal 22, the target address detection circuit 23 immediately outputs the read signal 20.
Begin to decipher.

When the entire address part 4 is read and it is determined that it is the target address, the address detection signal 24
Make true. This signal 24 is applied to a timer circuit 25 and AND gates 26 and 27. The timer circuit 25 performs a timekeeping operation at a fixed timing, and immediately starts the timekeeping operation upon receiving the signal 24.

Now, when the address marker detection circuit 21 detects the address marker 8 of the data section 5 from the read signal 20, the address marker detection signal 28 becomes true.

Therefore, since the AND condition of the address detection signal 24 and the address marker detection signal 28 is satisfied in the AND gate 26, the AND gate 26 is opened and a signal is given to the data section analysis circuit 29. Further, the data in the data section 5 of the read signal 20 is also given to the AND gate 27, and in the same way, the AND gate 27 is opened and this data is given to the data section analysis circuit 29.
The data section analysis circuit 29 is activated by the signal sent from the AND gate 26 and immediately starts a CRC check on the data in the read signal 20 sent through the AND gate 27, for example, the data in the data section 5. and,
This data is output as a data signal 30 and transferred to memory. During this time, the timer circuit 25 continues to measure time. Eventually, when the end of the data section 5 is reached and the data CRC check is completed, the CRC end signal 31 becomes true. This signal 31 is given as a RESET signal to the target address detection circuit 23 via the timer circuit 25 and the OR gate 32. Therefore, the timing operation of the timer circuit 25 is stopped by this signal 31, and the timeout error signal 33 never becomes true. Timer circuit 25
The time limit is set so that the timeout occurs after the address section 4 is detected and before the next address marker 17 is detected, and approximately in the middle of the gap 6 that exists after the end of the data section 5. On the other hand, for some reason, the address marker detection circuit 21 detects the address marker 8 in the data section 5.
If not detected, the address marker detection signal 28 from the address marker detection circuit 21 will not become true.

Therefore, for example, if the address detection signal 24 is
6, since the address marker detection signal 24 is not true, the AND condition of the AND gate 26 is not satisfied, and no signal is given from the AND gate 26 to the data section analysis circuit 29. Therefore, the data part analysis circuit 29 will not be activated. On the other hand, as described above, the timer circuit 25 starts its time counting operation in response to the address detection signal 24 and continues its time counting operation, until the predetermined time, that is, the set time limit is reached.

Then, the timer circuit 25 outputs a timeout error signal 33. This timeout error signal 33 is applied to the target address detection circuit 23 via the OR gate 32 and resets this circuit 23. Further, even if the address marker detection circuit 21 detects the address marker 8 of the data section 5, a timeout error signal 33 is output if the CRC check of the data in the data section 5 is not completed within a certain period of time.

That is, when the address marker 8 of the data section 5 is detected in the address marker detection circuit 21, the address marker detection signal 28 becomes true, so the AND condition of the AND gate 26 is satisfied, and the AND gate 26 analyzes the data section. A signal is applied to circuit 29.

Therefore, the data section analysis circuit 29 starts operating and immediately starts a CRC check of the data in the data section 5 of the read signal 20 sent via the AND gate 27. On the other hand, the timer circuit 25 continues to measure time.

Therefore, in the data part analysis circuit 29, the data CR
If no C check is performed, or even if a CRC check is performed, there may be errors in the data.
If the check takes a long time, the timer circuit 2
5 has finally counted a certain period of time, and the timeout error signal 33 becomes true. Of course, when the CRC check is completed within a certain period of time, the CRC end signal 31 is sent to the timer circuit 2.
5 and the timer circuit 25 is reset, so the timeout error signal 33 does not become true.

As explained above, according to the present invention, if the data check of the data section is not completed within a certain period of time after detecting the address section, it is possible to determine an error, and error detection can be performed properly in sector units. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structure of tracks and sectors on a disk, FIG. 2 is a diagram showing the structure of sectors arranged on a track, and FIG. 3 is a block diagram of a control logic circuit according to an embodiment of the present invention. It is. In the figure, 1... disk, 2...
Track, 3... Sector, 4, 14...
・Address section, 5, 15... Data section, 6...
...Gap, 7, 8, 17, 18... Address marker, 10, 11... Sector, 21...
...Address marker detection circuit, 23...
Target address detection circuit, 25...timer circuit, 29...data part analysis circuit.

Claims (1)

[Claims] 1. In an information storage device in which a plurality of sectors are arranged consecutively, each sector has an address field and a data field, and the data field is read after reading the address field, at least the data field of each sector is It has a detection means for detecting the attached address marker, a timekeeping means for performing a timekeeping operation, and a data analysis means for checking the data of the read data section, and when the address section of a certain sector is detected. , causes the clocking means to start a timekeeping operation, and after the address marker is detected by the detection means, the data in the data section is inputted into the data analysis means, and the data in the data section is read by the timekeeping means until the timekeeping means measures a predetermined time. An information storage device characterized in that an error occurs when data analysis means does not complete a data check operation.