JPS59221169A - Method and apparatus for processing picture data - Google Patents

Abstract

PURPOSE:To realize a picture data processing method to which optional and proper repeat compressing method is applied effectively by utilizing the periodicity of a dots formed binary-coding picture data so as to process data thereby converting the data into a data having a high repetition. CONSTITUTION:The dots formed binary-coding picture data obtained by the filtering processing is set to an input register 63 via an input terminal 68 and calculated with a data in a comparison register corresponding to bits in an EXOR circuit 65. The result of this operation is set to a line buffer 66 and a series of operations is repeated until the buffer 66 is occupied. When the line buffer 66 is occupied, its content is applied to a repeat compressing circuit 67, where a data for one line's share is compressed. Further, this is repeated until the processing of the entire picture is finished, so as to compress the dots formed binary-coding picture data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data processing method window and device that makes it possible to effectively apply a repeat compression method by utilizing the periodicity of image data to convert it into highly repeatable data. .

2. Description of the Related Art Conventionally, as a processing method and apparatus for processing image data of a continuous tone image such as a photograph, there is a C halftone binary image data processing method and apparatus. FIG. 1 shows a configuration diagram of a halftone binary image processing apparatus, and FIGS. 2 to 5 show explanatory diagrams of a halftone binary image processing method. In FIG. 1, a continuous tone image 1 such as a photograph is read and scanned by a high-resolution L-axis scanner 2 to obtain a tone signal 6 for each pixel.

Separately, a threshold value daple for halftone dot formation as shown in FIG.
Prepare and memorize it in advance.

As shown in the second factor, the two types of threshold tables (5) and () consisting of 6×6 pixels are an example of dealing with a 72-gradation signal. 71. It is clear that various arrangements of the threshold values in the threshold tables (A) and C[3] are actually possible and are not necessarily limited to those shown. As a combination of these threshold values table 2 and (J3) of FIG. 2, a threshold value filter as shown in FIG. 3, for example, is generated equivalently to the filter signal circuit 5 of FIG. 1 in terms of signal processing.

Then, the binarization circuit 6 compares the threshold value of each pixel in the electrical filter signal circuit 5 with the input grayscale signal 6 of each pixel, and filters the grayscale signal 6. Accordingly, the original gradation signal 6 is converted into halftone binary image data as shown in FIG. 4 as an output signal of the processing device shown in FIG.

The halftone binary image data signal illustrated in FIG. For example, each matrix area (a), (b) t (c), (d) consisting of 6×6 pixels in the same figure is shown.
and (e), the gradation value in the original image is 1, respectively.
The cases of 1.12, 13, 57 and 58 are shown.

Based on the halftone binary image data signal 7 created in this way, a CRT phototypesetting machine, a laser phototypesetting machine, etc. is driven to reproduce the black and white of each pixel, thereby creating a halftone image, that is, a halftone image. The image is output on a photosensitive material.

FIG. 5 shows the minimum constituent unit of the threshold filter shown in FIG.
It is made up of pixels.

However, if we consider the amount of halftone binary image data, as shown in Figures 4 and 5, 1
One halftone dot forming block is composed of 12 x 12 pixels based on the halftone binary image data signal 7; Assuming that an image is to be output, the number of data bits (number of pixels) required for an image per square inch is 122X(1/2)8524J-5-! =;5.2X
10"et/7 square inches.

This shows that, for example, one image of 4 inches square (approximately IQcm square) requires an amount of data of 42 x 5.2 x 10ζ8.3 megabits. In other words, conventional image data processing using halftone binary image data signals has the problem of requiring a large-capacity memory because the amount of data is enormous.

The present invention was made in order to eliminate the drawbacks of the conventional methods described above, and by processing using the periodicity of halftone binary image data, it is possible to process data with high repeatability. The object of the present invention is to provide a method and apparatus for processing image data, thereby effectively applying any suitable repeat compression method.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows a block diagram of an image data processing device according to an embodiment of the present invention. In FIG. 6, the memory 61 has a storage capacity equivalent to one halftone dot forming block, that is, one cycle, as described in FIG. 5, in this case, 12 pixels x 12 columns. . Also, 62 is
This is an interface that manages pointers when writing to and reading from the memory 61. Furthermore, 66 is an input register, to which binary image data of the halftone dot forming block is inputted from an input terminal 68, and 64 is a comparison data register, in which the column data set in the input register 6 is read out from the memory 61. and set.

Reference numeral 65 denotes an EXOR circuit that performs an exclusive OR operation for each bit of corresponding bit information by registering comparison data with the input register 66, and inputs the operation result of the EXOR circuit 65 to a line buffer 66. Furthermore, 67 is a well-known repeat compression circuit. This repeat compression circuit 67 performs data compression by storing the number of repetitions when the same data appears four times. The present invention performs data conversion so that this repeat compression method can be effectively utilized. That is, the feature is that the original halftone binary image data is converted into data with a large number of repetitions of the same data.

Next, the operation of the image data processing apparatus shown in FIG. 6 will be explained with reference to FIG. 7.

FIG. 7 (*This is an enlarged portion of the halftone dotted binary image data of FIG. 4 already mentioned, which corresponds to the uppermost halftone dot formation block. In this FIG. 7, One column made up of 12 vertical pixels will be called a "column".

As is clear from FIG. 7, the halftone binary image data is
The size of the mesh forming block, that is, in this case, identical or similar columns appear at intervals of the subordinate column in the horizontal direction.

For example, the No. 9 column and the No. 21 column are the same, and the No. 1.0 column and the No. 22 column differ by only one bit (pixel). The halftone binary image data of each column is processed as follows by the image data processing device shown in FIG. That is,
As described above, the halftone binary image data obtained by the filtering process is set in the input register 66 column by column (via the input terminal 68. The column data corresponding to the input column is stored in the buffer memory 61. Comparison data register 6 via Yodzuke t1 interface 62
Set to 4. Data in both registers 66 and 64 is operated on in a bit-by-bit manner in EXOR1rJ path 65, and the result of the operation is set in line buffer 66. Set the contents of the input register 66 to the buffer memory 61,
Column data after one cycle (temporarily reserved as comparison data for two pairs. The write/read pointer in the interface 62 is updated by "+1".

In this case, it goes through one cycle of 12 steps, and after one cycle of 12 steps, it becomes 1 again. In this way, this series of operations is repeated until the line buffer 66 is full. Furthermore, when the line buffer 66 becomes full, its contents are supplied to a repeat compression circuit 67, and the data for one line buffer is appropriately compressed by a well-known repeat compression method. The above operations are repeated until the data processing of the entire image is completed.

As a result, the halftone binary image data is compressed.

Next, the operation of the image data processing method according to this embodiment will be explained in FIG. 8. In FIG. 8, the fXB product code is the same as in FIG. In addition, the symbols ■ to ■ indicate the order of processing steps.
22 is an operation explanatory diagram showing the state when the data of O22 is input to the terminal 68. FIG. One-cycle buffer memory 6 in Figure 8
1 pointers 1 to 9 have human power data column No. 1
Already updated data corresponding to numbers 3 to 21 is set. In addition, data corresponding to columns No. 10 to 12 of the previous processing input data remains in pointers 10 to 12. Therefore, as described in FIG. The input data of a predetermined column is stored in the input register 66, and the column data of the one-period buffer memory 61 is stored as comparison data in processing step (3).
is introduced into register 64. Next, the comparison between the two is EXO
The R circuit 65 calculates the result, and the result is stored in the line buffer 66 in processing step (2). Then, by processing step ■, the data of pointer 10 is changed to column N.
o Updated to data corresponding to 21. Since the pointer is updated sequentially as shown by the broken line Pr in Fig. 8,
It changes from 10 to 11 and waits for the next column to be processed.

As is clear from the line buffer 66 in FIG. 8, the output signal of the EXOR circuit 65 processed according to the present embodiment has a "white" portion for the most part, and white columns are often repeated.

That is, in this embodiment, a halftone binary image 18 without border reversal is used.
! This means that the data signal 7 has been converted into highly repeatable data.

This means that if the data in the line buffer 66 is supplied to the repeat compression circuit, efficient data compression can be expected.

In the above embodiment, a case has been described in which one column consisting of 12 vertical pixels is processed as a "column", but the number of pixels in a "column" can vary depending on the size of the halftone dot forming block. . On the other hand, even if one row consisting of 12 horizontal pixels is treated as a "column" and the processing is performed using periodicity in the vertical direction, the process is exactly the same.

Further, in the above embodiment, data corresponding to the size of a halftone dot forming block is stored as comparison data in the one-period buffer memory 61, and a column corresponding to the input column is read out and compared in the EXOR circuit 65. In addition to this, it is also possible to temporarily store all the data for one row or one column in a halftone dot forming block, and then store the corresponding column between the data in the next row or column. Compare EX
It is also possible to perform an OR logical operation.

As described above, according to the image data processing method and apparatus according to the present invention, continuous tone images as halftone binary images require a large amount of data, which causes problems in both storage and transmission. In order to solve this problem, an image data processing device has been developed that utilizes the periodicity of halftone binary image data to convert it into data with high repeatability and compress the data.

Furthermore, as mentioned above, the halftone binary image data is converted into highly repeatable data suitable for the repeat compression method by utilizing the fact that it has approximately periodicity. As a result, it is possible to provide an image data processing method that contributes to efficient data compression, is applicable to various image processing fields, and has the effect of recreating images with high precision while having a small memory capacity. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional image data processing device, FIGS. 2 to 5 are explanatory diagrams of halftone z-value image data obtained by the device in FIG. 1, and FIG. 6 is a block diagram of a conventional image data processing device. A block configuration diagram of an image data processing device according to an embodiment of the invention, a seventh factor is an explanatory diagram of halftone binary image data processed in the same embodiment, and FIG. 8 is an explanatory diagram of halftone binary image data according to an embodiment of the invention. An explanatory diagram of the operation of the image data processing method is shown. 61... 1 cycle buffer memory, 62... Inter path, 66... Line buffer, 67... Repeat compression circuit, 68... Input terminal, 69... Output terminal. Patent applicant Shaken Co., Ltd. 1 Figure 3 (A) (B) Figure 7 Figure 8

Claims (1)

[Claims] (1) 97 floors for each pixel obtained by scanning the image with a scanner
In an image data processing method having halftone binary image data obtained by comparing 4 signals and tone signals repeatedly output based on a pre-stored halftone dot formation threshold table, the above halftone dot The converted binary image data is divided into two for each halftone dot forming block, and after converting it into data with high repeatability using the mutual similarity of the above halftone dot forming blocks, An image data processing method characterized in that data compression is achieved by replacing the same data portion with the number of repetitions of the same data. C) A gradation signal for each pixel obtained by scanning the image with a scanner. , an image processing device for halftone binary image data obtained by comparing gradation signals repeatedly output based on a threshold table for halftone formation stored in advance; a one-cycle buffer memory for storing the halftone binary image data corresponding to one cycle of the block, with the number of columns as blocks; and an input register for inputting the halftone binary image data for each column. , a comparison data register that inputs the previous column data in the one-cycle buffer memory corresponding to the column, and a logic circuit that performs an exclusive OR operation on the data of both the input register and the comparison data register. , a line buffer that stores the output signal of this logic circuit, and a line buffer that stores the output signal of this logic circuit.
An image data processing device comprising a repeat compression circuit that repeatedly compresses processing data in 7A.