JPS59221139A - Data reproducing circuit - Google Patents

Abstract

PURPOSE:To eliminate fluctuation of a pulse width due to the difference in the rising and falling speed of a pulse waveform and to attain accurate pulse width reproduction by detecting the rise and fall of the pulse waveform at the first moment. CONSTITUTION:A level shift circuit 12 shifts the level of an output signal of a preamplifier 1 to a low level and the signal is applied to a non-inverting terminal of a comparator 16 and an inverting terminal of a comparator 15. Further, a high-level peak holding circuit 10 holds a high level, a level shift circuit 13 shifts the level to a value decreased by a minute voltage from the high level and the result is applied to a non-inverting terminal of the comparator 15. Further, a low-level peak holding circuit 11 holds a low level, a level shift circuit 14 shifts the level to a level increased by a minute voltage more than the low level and the result is applied to an inverting terminal of the comparator 16. An output of the comparators 15, 16 is applied to an AND circuit 17. An output of the comparator 15 is delayed and inputted to a data terminal of an FF18. An accurate reproduced waveform nearly close to the transmission waveform is obtained from a Q output of the FF18.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a binary signal receiving device υ, particularly a data reproducing circuit ζ that can improve the yield when integrating a binary signal receiving device using an element. Regarding this.

(b) Prior Art and Problems A conventional data reproducing method using light will be explained below.

Figure 1 is a block diagram of the main points of conventional optical signal receiving equipment, and Figure 2 is a time chart showing the waveforms of each part in Figure 1. is a ""' in Figure 1.
Corresponding to C+ 6 to 1 points, (the solid line is the output of preamplifier 1, the dotted line is the output of preamplifier 2, and the DC control Mll [!
” indicates the reference input to the reference amplifier 4 plus the output of the IiJg reference amplifier 4.

In the figure, 1.2 is a preamplifier, 3 is a fixed reference amplifier, 4 is a variable reference amplifier, 5 is an I)C control circuit,
6.7 is a comparator, 8 is an OR circuit, 9 is a light receiving element, R, t
o + RW indicates resistance.

The operation will be explained below. When the original signal received by the light receiving element 9 is converted into an electric signal and amplified by the preamplifier 1, the signal shown in Fig. 2 (
A signal having a waveform as shown is obtained, and this signal is input to a fixed reference amplifier 3 and a variable reference amplifier 4. On the other hand, the output of the unmanned preamplifier 2, which has the same characteristics as the preamplifier 1, is input to a fixed reference amplifier 3 and a variable reference amplifier 41.
The output of this preamplifier 2 is shown in Figure 2 (false).The fixed reference J', j width filter 3 uses the output of the clear amplifier 2 as a reference input, and connects the preamplifier I.
The comparator 61 increases the output of the comparator 61 by increasing the output of At the same time, the threshold voltage is input to the comparator 7.

In the variable reference amplifier 4, the output is sent to the DC control circuit 5.
As shown in Figure 2 (C), the reference signal of the sum of its output voltage and the output potential of preamplifier 2 is obtained as shown in Fig. is used as a reference input, the input from the preamplifier 1 is amplified to obtain an output signal with the waveform shown in FIG. The threshold voltage input to the comparator 7 shown is o]
Variable 11 reference amplifier 4I input amplifier 1
The DC control circuit 5 adjusts so that the difference in the same potential between the output signal and the reference signal described above becomes the threshold value.

Therefore, the output of the comparator 6 is 9 as shown in FIG. 2(C).
The output of the comparator 7 is as shown in FIG. The standing υ point is taken as the rising point, and the 9th point is almost the rising point, and a reproduced waveform is obtained in which the pulse width does not fluctuate due to differences in the speed of the rise and fall of the pulse waveform. However, in the circuit shown in Fig. 1, the characteristics of clear amplifier 1 and preamplifier 2 do not match, and clear amplifier 2
When the output m pressure of the variable amplifier 4 fluctuates, the threshold level of the input signal of the variable amplifier 4 and the output of the fixed reference amplifier 3 change #7, causing a fluctuation in the pulse width of the reproduced waveform.

If the output fluctuation of the preamplifier 2 is relatively large, it may become impossible. Therefore, in such a data reproducing system, it is necessary to match the characteristics of the preamplifier 1 and the preamplifier 2, and there is a drawback that the yield becomes poor when integrated.

(c) Purpose of the Invention In view of the above-mentioned drawbacks, the object of the present invention is to provide a system that can accurately reproduce binary digit data, and in the case of an original, converts the digit digit into an electric digit as a preamplifier. An object of the present invention is to provide a data reproducing circuit that can configure an optical signal receiving device 77 using only a preamplifier and can improve the yield when integrated.

(W. Structure of the Invention In order to achieve the above second object, the present invention detects the rising and falling edges of the pulse waveform at the first moment of the pulse waveform pulse 1 due to the difference in the rising and falling speeds of the pulse waveform.) 0
ffRh is eliminated, and accurate pulses can be reproduced. By setting the threshold level for falling edge detection and setting the level slightly higher than the low level as the threshold level for rising edge detection, the falling and rising points can be determined accurately (
All the features are designed to be able to detect this, and as a result,
The preamplifier of the original signal receiving device is designed so that it can consist only of a preamplifier that converts an optical signal into an electrical signal.

(e) Embodiments of the Invention Below, nine simulations using light according to an embodiment of the present invention will be explained with reference to the drawings. FIG. 3 is a block diagram of the main parts of the optical signal receiving device according to the embodiment of the present invention, and (included in FIG. 4) are the transmitted signal waveforms, and (B) to (CJ are time charts of the waveforms in the valleys in FIG. Therefore, (B) to (6) are C corresponding to 7.1 at points b-g in Figure 3.
), G corresponds to point T in Figure 3.

Components in FIG. 3 that have the same functions as those in FIG. 1 are indicated by the same symbols. 1
0 is a high level peak hold circuit, 11 is a low level peak hold circuit, 12 to 14 are level shift circuits, 15
．． 16 is a comparator, 17 is an AND circuit, 18 is a flip 7
0 tube (hereinafter referred to as FF), 19 to 21 indicate knot circuit metals.

Koujo-go'! The output of the preamplifier 1, which is converted into an electrical signal, has a gentler fall and rise than the transmitter shown in FIG. Therefore, the level shift circuit 121 level-shifts the output signal of the preamplifier 1 to a low level, as shown in FIG. 4(C).
The entire waveform of the waveform shown in is applied to the negative terminal of the comparator 15 and the positive terminal of the comparator 16.

On the other hand, in the high level peak hold circuit 10, the preamplifier J
The high level of the output waveform of is held, and the level of the output is level-shifted by a level soft circuit 131 to a value that is a minute voltage Δv1 lower than the high level of the waveform of the output of the level shift +- circuit 12 shown in FIG. 4(c). and is applied to the positive terminal of comparator 15. Also, low level peak bold circuit 11 (trowel, preamplifier 1
The low level of the output waveform of Q is held, and its output is changed to the level of the output of the level shift circuit 141 and level shift circuit J2 (a level slightly higher than the low level of the waveform of Q by an amount of p' [IT pressure Δv2]). f is level-shifted and applied to the negative terminal of the comparator 16. From this, the outputs of the comparators 15 and 16 are
The waveform shown in Figure (6) (g) is obtained.

When the output sound AND circuit of the comparators 15 and 16 is added, the output becomes as shown in FIG. This output is added to the clock terminal of FF18 (on the other hand, comparator 15
The output is inverted via software circuits 19 to 21, and is slightly delayed before being inputted to the data terminal of FF'18. Therefore, the Q output of FF18 is 2! ! As shown in FIG. 4 (6), an accurate reproduced waveform that is almost the same as the transmitted waveform f in FIG. 4 (A) can be obtained. In this way, since only one preamplifier is required, the yield is improved when integrated.

Figures 5 to 9 show the high level peak hold circuit, low level peak hold circuit, and level shift circuit 1 in Figure 3.
2. It is a circuit diagram of the level shift circuit 13 and the level shift circuit 14.

In the figure, Tr1 to Tr< are transistors, R1-R2 are resistors, CI+C2 are capacitors, 22 to 24 are constant current circuits, 22 is a current circuit, and 23 is a current circuit.

, 24 is a leather ryuko.

FIG. 5 shows a normal daytime level peak hold circuit which holds the peak pressure of the input signal device level through the capacitor C11 and outputs the output voltage through the transistor Trt', and FIG. 6 shows the low level of the input signal through the capacitor C21. This is a normal low level peak hold circuit which holds the input signal and extracts the output voltage through the transistor Trye.The circuit shown in FIG. 7 corresponds to the level shift circuit 12 shown in FIG.

Through the same circuit using the transistor Try resistor RIk in FIG. 6, the level shift 1.
Same circuit as the circuit in Figure 6, and transistor Tr4,
Normal current I, l of constant current circuit 22.

This is a circuit that shifts the level by the voltage drop of XR and outputs it. The circuit shown in FIG. This I, XR is a circuit that shifts the level to a lower potential by the voltage drop of IzXRt due to engineering.

corresponds to ΔV, l in FIG. 4(C). Figure 9 is the third
This circuit corresponds to the level shift circuit 14 shown in the figure, and from the case of FIG.
匝1 whose level is shifted to a higher potential by the voltage drop of XR2
On the road, this IS XR2 @Figure 4 (Δ■ of Q.

corresponds to

(f) Effects of the invention in more detail (As explained here, according to the invention, the detection sound of the rise and fall of the pulse waveform is performed at the initial tolerance level, so the pulse 11 is caused by the difference in the speed of the rise and fall of the pulse waveform.
] fluctuations are eliminated, accurate pulse reproduction is possible, and in the case of an optical signal receiving device, only one ζ·1 amplifier is required, which has the effect of improving yield when integrated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a conventional optical signal receiving device.
2 is a time chart of the waveforms of each part in FIG. 1, FIG. 3 is a block diagram of the bag section of the optical signal receiving device according to the embodiment of the present invention, and FIG. 4 is a time chart of the waveforms of the transmitted signal and each part of FIG. Waveform timing (・, ?rj, Figures 5 to 9 are the high level peak hold circuit in Figure 3, the low level peak hold circuit,
2 is a circuit diagram of a level shift circuit 12, a level shift circuit 13, and a level shift circuit 14. FIG. In the figure, 1.2 is a preamplifier, 3 is a fixed reference amplifier, 4 is a variable reference amplifier i, 5 is a DC control circuit, and 6 is a
, 7, 15, 16 are comparators, 8 is an OR circuit, 9 is a light receiving element, 10 is a high level peak hold circuit, 11 is a low level peak hold circuit, 12 to 14 are level shift circuits, 17 is an AND circuit, 18 is a flip-flop, 19~
21 is a knot circuit, 22-24 are constant current circuits, Trl~
Tr4 is a transistor, R1 to Rt, Rho +'
R++ represents a resistor, and C, , C, represents a capacitor. Figure 1 Figure 16 Figure 713 Figure 9

Claims (1)

[Claims] A circuit that level-shifts the input signal to a low level and inputs it to the negative terminal of the first comparator and the positive terminal of the second comparator, and a circuit that peak-holds the high level of the input signal and level-shifts all of its outputs above. a circuit that manually shifts the level to a lower level by a slightly larger amount than the amount υ to the first comparator's original 1b;
A circuit that peak-holds the low level of the input signal, shifts its output to a level slightly lower than the level shift amount by V, and inputs the entire negative terminal of the second comparator; The output is delayed and inputted to the data terminal of the flip-flop, and the output obtained by calculating the AND of the outputs of the first comparator and the second comparator is inputted to the clock terminal of the flip-flop. A data reproducing circuit characterized in that the output is a reproducing output of the input signal.