JPS59221030A - Balancing circuit of load current - Google Patents

Balancing circuit of load current

Info

Publication number
JPS59221030A
JPS59221030A JP9417583A JP9417583A JPS59221030A JP S59221030 A JPS59221030 A JP S59221030A JP 9417583 A JP9417583 A JP 9417583A JP 9417583 A JP9417583 A JP 9417583A JP S59221030 A JPS59221030 A JP S59221030A
Authority
JP
Japan
Prior art keywords
current
winding
transistor
base
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9417583A
Other languages
Japanese (ja)
Other versions
JPH0254697B2 (en
Inventor
Takashi Yamashita
隆司 山下
Isao Yokoyama
勲 横山
Hiroshi Yamagai
山貝 浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd, Nippon Telegraph and Telephone Corp filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP9417583A priority Critical patent/JPS59221030A/en
Publication of JPS59221030A publication Critical patent/JPS59221030A/en
Publication of JPH0254697B2 publication Critical patent/JPH0254697B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors

Abstract

PURPOSE:To eliminate the use of many balancing transformers or a transistor which has a margin of breakdown strength by adding a collector current negative feedback winding to a driving transformer to correct an unbalanced current. CONSTITUTION:For a driving transformer DT, a winding N2 is used for negative feedback and a winding N3 is used to give the positive feedback of the sum of collector currents of all transistors TRQ1-Qn to the base of each TR and then supply a base current after these TRs are turned on. In such constitution of driving circuits A1-An, the current flowing to the winding N3 is positively fed back to a base winding N1. However the collector current of each TR flowing to the winding N2 is negatively fed back to the N1. This current can balance the current in a saturated ON state of plural switching TRs connected in parallel to each other and also can balance the variance of turn-off characteristics. Thus the voltage waveform obtained in a turn-off state of each TR can be balanced even with the inductance load.

Description

【発明の詳細な説明】 本発明(・ま、複数個のトランジスタで共通の負荷電流
を同時にスイッチングする場合に各トランジスタに流i
′+るコレクタ電流(負荷分担電流)のノくランスを容
易に達成し得る負荷電流バランス回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention (・When switching a common load current by multiple transistors at the same time,
The present invention relates to a load current balance circuit that can easily achieve a balance of collector current (load sharing current).

トランジスタをスイッチ素子として使用して負荷電流を
スイッチングする場合に単一のトランジスタを用いるの
では電流容置あるいは内部損失型各端子(コレクタ、エ
ミッタ、ベース)を並列接続して使用するとトランジス
タ間の特性の差によって各トランジスタを流れる電流に
アンバランスを生じる。この為従来は例えば第1図に示
す様な回路によって各トランジスタを流れる電流のバラ
ンスをとっていた。
When using a transistor as a switch element to switch the load current, it is not possible to use a single transistor, but if the current capacity or internal loss type terminals (collector, emitter, base) are connected in parallel, the characteristics between the transistors will change. This difference causes an imbalance in the current flowing through each transistor. For this reason, conventionally, the current flowing through each transistor was balanced by a circuit as shown in FIG. 1, for example.

第1図は直流電源Eiより供給されろ直流電力を駆動パ
ルス発生回路Pからの駆動信号によって駆動されるスイ
ッチ回路fτ′5Sによりスイッチング圧を得たい場合
は、外圧又は降圧のための主変圧器及び整流回路、平滑
回路等が負荷zLの中に含まれていてそれらにより得ら
れるものと考えれば、スイッチ回路部Sそのものは第1
図に示した通りの回路でよい。
Fig. 1 shows the DC power supplied from the DC power supply Ei. When it is desired to obtain the switching voltage by the switch circuit fτ'5S driven by the drive signal from the drive pulse generation circuit P, the main transformer for external voltage or voltage step-down is used. If we consider that the load zL includes a rectifier circuit, a smoothing circuit, etc., and is obtained by them, the switch circuit section S itself is the first
The circuit shown in the figure may be used.

第1図において、Pは駆動パルス発生回路、A1〜An
はそれぞれトランジスタQ1〜Qnをスイッチング動作
させるためのR%b回路であり、駆動トランスDTを持
ち、トランジスタQ1〜Q、nが駆動巻線N4からのオ
ン信号で一旦ONt、た後はコレクタ電流巻11Nz(
巻線N2には、エミッタ電流から巻線N1に流れるベー
ス電流を差引いた残りの電流、すなわちコレつ夕電流が
流れる)、ベース巻線Nxによりコレクタ電流を正帰還
してベース電流を供給するいわゆる電流帰還形の駆動回
路を構成している。
In FIG. 1, P is a drive pulse generation circuit, A1 to An
are R%b circuits for switching transistors Q1 to Qn, and each has a drive transformer DT, and transistors Q1 to Q, n are once turned ON by an on signal from drive winding N4, and then the collector current winding is turned on. 11Nz (
The current remaining after subtracting the base current flowing through the winding N1 from the emitter current, that is, the current flowing through the winding N2, flows through the winding N2.The base winding Nx supplies the base current by positive feedback of the collector current. It constitutes a current feedback type drive circuit.

この回路では各トランジスタ間の特性のバラツキによっ
て生じたコレクタ電流のアンバランスはバランス用変流
器(BT12〜BT11)によってバランス作用を受け
、各トランジスタの負荷分担電流量1〜ilがほぼバラ
ンスされる。しかしこの従来回路では、スイッチングト
ランジスタと同じ数のバランス用変流器が必要となるだ
けでなくトランジスタからみた負荷回路にバランス用変
流器が2個も挿入されたことになるため配線インダクタ
ンスが大となり、トランジスタのターンオフ時のコレク
タ・エミッタ間のザージ電圧を太き(する。またトラン
ジスタの蓄私時間にバラツキがあると最初にターンオフ
する蓄積時間の短いトランジスタのコレクタ・エミッタ
間サージ電圧が特に大となりターンオフ時の電圧波形に
アンバランスを生じ耐圧的に余裕をもったトランジスタ
を使用する必要がある。
In this circuit, the unbalance of the collector current caused by the variation in characteristics between each transistor is balanced by the balancing current transformer (BT12 to BT11), and the load sharing current amount 1 to il of each transistor is almost balanced. . However, this conventional circuit not only requires the same number of balancing current transformers as switching transistors, but also requires two balancing current transformers to be inserted into the load circuit seen from the transistor, resulting in a large wiring inductance. This increases the surge voltage between the collector and emitter when the transistor is turned off.Also, if there are variations in the storage time of the transistor, the surge voltage between the collector and emitter of the transistor with a short storage time that turns off first will be particularly large. This causes an imbalance in the voltage waveform at turn-off, and it is necessary to use a transistor with sufficient voltage resistance.

この様に従来例の回路では数多(のバランス用変流器を
必要としたり耐圧的に余裕のあるトランジスタを使用す
る必要性などからコスト高となる欠点があった。
As described above, the conventional circuit has the disadvantage of high cost due to the necessity of a large number of balancing current transformers and the necessity of using transistors with sufficient voltage resistance.

不発り旧゛よ上述のよう1よ従来技術の欠点を除去する
ためになさねたものであり、従って本発明の目的は、多
くのバランス用変流器を必要としたりせの並列接続スイ
ッチングトランジスタの負荷電流バランス回路を提供す
ることにある。
The present invention has been made in order to eliminate the disadvantages of the prior art as mentioned above, and it is therefore an object of the present invention to solve the problem of parallel connected switching transistors which require a large number of balancing current transformers. The purpose of this invention is to provide a load current balance circuit.

」:記目的を達成するため、本発明は、並列接続スイッ
チングトランシフタの負荷電流バランス回路であって、
少なくとも3巻線を有する駆動トランスを前記トランジ
スタの各々毎に対応して用意し、各トランジスタのベー
スとエミッタの間に、幻応せる駆動I・ランスの第1の
巻υを接続し、各トランジスタのエミッタに同じく対応
せる駆動トランスのh′520巻線の一端を接続すると
共に、各トランジスタのコレクタから前記第2の巻線の
他端に至る回路をすべて並列に接続し、さらに前記各駆
動トランスの第3の巻線に前記各トランジスタのコレク
タ電流の和(負荷電流)に比例した電流を流1如(シ、
前記第2の巻終電流が増加するときには前記第1の巻線
を流計するベース電流が減少し、前記第3の巻線電流が
増加するとぎには前記第1の巻線を流れるパー2電流が
増加するように、前記第1乃至第3の各巻線を前記駆動
トランスにおいて巻回して成ることを特徴としている。
”: In order to achieve the above object, the present invention provides a load current balance circuit for parallel-connected switching transformers, comprising:
A drive transformer having at least three windings is provided for each of the transistors, and a first winding υ of a corresponding drive I-lance is connected between the base and emitter of each transistor. One end of the h'520 winding of the corresponding drive transformer is connected to the emitter of the same, and all the circuits from the collector of each transistor to the other end of the second winding are connected in parallel, and each of the drive transformers A current proportional to the sum of the collector currents of the transistors (load current) is passed through the third winding of the transistor.
When the second winding final current increases, the base current flowing through the first winding decreases, and when the third winding current increases, the base current flowing through the first winding decreases. Each of the first to third windings is wound around the drive transformer so that the current increases.

次に図を参照して本発明の一実施例を説明する。Next, an embodiment of the present invention will be described with reference to the drawings.

第2図は本発明の一実施例を示す回路図である。FIG. 2 is a circuit diagram showing one embodiment of the present invention.

同実施例は、第1図においで示したバランス用変流器(
13T12〜BTn1)の代りに駆動トランスI) T
にアンバランス電流を補正する為のコレクタ電流負帰還
巻線を有することが特徴である。
This embodiment is based on the balancing current transformer (
Drive transformer I) T instead of 13T12~BTn1)
It is characterized by having a collector current negative feedback winding for correcting unbalanced current.

第2図の駆動トランスDTにオ6いてN2は負帰還巻線
として使用し、N3は全トランジスタのコレクタ電流の
和を各トランジスタのベースに正帰還してターンオン後
のベース電流を供給する為の巻線として使用する。この
イ、・毛にg動回路を構成するとN3巻線に流れる電流
(全トランジスタのコレクタ電流和Σjk)はベース巻
線N1に正帰還に=1 されるがN2巻線を流れる各トランジスタのコレクク電
流は負帰還されてn個のトランジスタのうEpm番目の
トランジスタのターンオン後のベース電流i +3 (
m )は次式で示される値になる。
In the drive transformer DT shown in Figure 2, N2 is used as a negative feedback winding, and N3 is used to positively feed back the sum of the collector currents of all transistors to the base of each transistor to supply the base current after turn-on. Use as winding wire. If a g-dynamic circuit is constructed in this way, the current flowing in the N3 winding (collector current sum of all transistors Σjk) will be given positive feedback to the base winding N1, but the collector current of each transistor flowing in the N2 winding will be positive feedback. The current is negatively fed back to the base current i +3 (
m) has a value expressed by the following formula.

但し’Inrm番目のトランジスタのコレクタ電流上記
(1)式より次のことが判る。ある一定の負荷(コレク
タ電流imが増えればそのトランジスタのベース電流I
B(m)が減少し、逆にコレクタ電流imが減少ずれば
ベース電流iB(。1)は増加する。
However, from the collector current of the 'Inrmth transistor, the following can be seen from equation (1) above. For a certain load (if the collector current im increases, the base current I of the transistor
If B(m) decreases and, conversely, collector current im decreases, base current iB(.1) increases.

すなわちこの負帰還動作は各トランジスタの負荷分担(
コレクタ電流11〜Inのバランス)作用として働くこ
とに1.cる。ここで N3 = −N2            ・・・曲−
・(2)但しn:並列数 とすればベース巻NNxへの総合電流帰還量を第1図の
場合と全く同じにすることができる。
In other words, this negative feedback operation distributes the load of each transistor (
1. Working as a balance of collector current 11~In). Cru. Here N3 = -N2 ... song -
(2) However, if n is the number of parallel circuits, the total amount of current feedback to the base winding NNx can be made exactly the same as in the case of FIG.

次に各トランジスタ間で番組時間のバラツキがあってm
’l目のトランジスタのターンオフ特性が他に比べて異
なる場合について考えるとa)蓄積時間が短かくターン
オフが速い場合他トランジスタのコレクタ電流よりも速
くm番目のトランジスタのコレクタ電流imが0となっ
ても上記(1)式に示すように他のトランジスタのコレ
クタ電流がベース電流r B (m )として帰還され
るのでコレクタ電流imが速くOとなることを妨げる効
果が発生する。
Next, there are variations in program time between each transistor.
Considering the case where the turn-off characteristics of the l-th transistor are different from those of the others, a) If the accumulation time is short and the turn-off is fast, the collector current im of the m-th transistor becomes 0 faster than the collector current of the other transistors. Also, as shown in the above equation (1), the collector currents of other transistors are fed back as the base current r B (m), so an effect occurs that prevents the collector current im from quickly reaching O.

b)蓄積時間が長くターンオフが遅い場合上記(1)式
においてm番目のトランジスタのコレクタ電流im以外
のコレクタ電流が0となった場合、ベース電流in(m
)は となる。(2)式よりN3≦N2(n≧2)であるから
ベース電流i B (m)はO又は負の電流となりベー
ス電流はすぐに0又は逆バイアス電流が発生し、コレク
電流imを速く0にする効果が発生する。
b) When the accumulation time is long and the turn-off is slow In the above equation (1), if the collector currents other than the collector current im of the m-th transistor become 0, the base current in(m
) becomes. From equation (2), since N3≦N2 (n≧2), the base current i B (m) becomes O or a negative current, and the base current immediately becomes 0 or a reverse bias current occurs, and the collector current im quickly becomes 0. The effect of

すなわち本発明に、しる回路は並列使用される複数個の
スイッチングトランジスタの飴和ON状態における電流
バランス作用だけでなくターンオフ特性のバラツキをも
バランスさせる作用があり、インダクタンス負荷の場合
に対しても各トランジスタのターンオフ時の電圧波形の
バランスが図られるので実用上の効果は非常に大きい。
In other words, in the present invention, the circuit has the effect of balancing not only the current in the ON state of a plurality of switching transistors used in parallel, but also the variation in turn-off characteristics, and is effective even in the case of an inductance load. Since the voltage waveforms at turn-off of each transistor are balanced, the practical effect is very large.

2q 3図は本発明の他の実AC+j例を示す回路図で
ある。同図に示す実施例Q11、並列使用数が多い場合
に対して第2図に示す回路に改良を加えた回路を示す1
、 第2図の回路では各駆動トランスの正帰還巻?つN3は
直列に接続され、これに負荷電流が直接流れる。従って
トランジスタの並列使用数が多い場合には主回路の配線
インダクタンスが犬となってトランジスタのターンオフ
時のザージ電圧を太き(発生させる原因となる。
Figures 2q and 3 are circuit diagrams showing other practical AC+j examples of the present invention. Embodiment Q11 shown in the figure shows a circuit 1 that is an improvement to the circuit shown in Fig. 2 for the case where there is a large number of parallel uses.
, In the circuit shown in Figure 2, the positive feedback winding of each drive transformer? N3 are connected in series, and the load current flows directly through them. Therefore, when a large number of transistors are used in parallel, the wiring inductance of the main circuit becomes a problem, causing a large surge voltage when the transistors are turned off.

第3図の回路ではN3巻線に流す電流は負荷電を通して
小さい電流に変換l−大きな負荷電流が各駆動トランス
を直接流れない様にして、主回路の配線インダクタンス
を低減すると共に駆動トランスのN3巻線を小電流化し
て製作容易にしたものである。
In the circuit shown in Fig. 3, the current flowing through the N3 winding is converted into a small current through the load current.L - By preventing large load currents from flowing directly through each drive transformer, the wiring inductance of the main circuit is reduced, and the N3 winding of the drive transformer is The winding has a small current and is easy to manufacture.

この場合、駆動トランスDT及び負荷電流変換用電流変
流器CTの巻数比の関係は N= = (N2′/N1 ’ ) −N2    ・
・・・・・・・・(3)とすれば第2図と全く同じ効果
にすることかできる。但しNl’、 N2’は変流器C
Tの1次巻線および2次巻線の各巻数である。
In this case, the relationship between the turns ratios of the drive transformer DT and the current transformer CT for load current conversion is N = = (N2'/N1') - N2 ・
If we use (3), we can achieve exactly the same effect as in Figure 2. However, Nl' and N2' are current transformer C
The number of turns of the primary winding and the secondary winding of T.

第3図においてダイオードD1は電流変流器CTの磁束
を確実にリセットするだめのものである。
In FIG. 3, diode D1 serves to ensure that the magnetic flux of current transformer CT is reset.

以上の如く本発明による回路は、電流帰還形駆動トラン
スのコレクタ電流を流す巻線をコレクタ電流バランスの
為の負帰還用動作の為に使用し、さらに全コレクタ電流
に比例する電流をベース電流として正帰還する様に新た
に巻線を設けることによって複数個のトランジスタのス
イッチング勧作?Cj i5fと電圧イζバランスさせ
るようにしたという21′j徽がある。
As described above, the circuit according to the present invention uses the winding that carries the collector current of the current feedback drive transformer for negative feedback operation for collector current balance, and further uses a current proportional to the total collector current as the base current. Is it possible to switch multiple transistors by adding new windings for positive feedback? There is a story in 21'j that it was made to balance Cj i5f and voltage ζ.

従1)て不発りJにJ、る負荷7i・、流バランス回路
は、従来の(、」;にバランス用変流器を使うこと)、
【<何個のトランジスタの51r’列使用に幻しても容
易に適用できるので、トランジスタをス・イツチ累子と
して使用する回路において、並夕旧(c f6tによっ
てスイッチ回路の容土lを容易に増大することができ大
容量のアコlツバ−1:、jli・旨、J’)C−AC
Tビq換のインバータ。
1) The current balance circuit is the same as the conventional one (using a current transformer for balance),
[<It is easy to apply it no matter how many transistors are used in the 51r' row, so in a circuit that uses transistors as a switch resistor, the capacity of the switch circuit can be easily reduced by A large-capacity accelerator that can be increased to 1:, jli, J')
T biq inverter.

]) C−+) C変t・1のコンバーク等−・の応用
にく力果犬ン、(:るものがある。
]) C-+) There are some difficulties in the application of C-variant t・1 convergence, etc., (:).

4 図面のf7iJ r’+’−な説明第1図は並列ス
イッチングトランジスタの負荷’1’、TM(ハ57 
、/(回1ii O)従来例を示す回1i’); I〉
<l、2F 2 [望。
4 f7iJ r'+'- explanation of the drawings Figure 1 shows the parallel switching transistor load '1', TM (Ha57
, /(Time 1ii O) Time 1i' showing the conventional example); I>
<l, 2F 2 [wish.

j:’j’、 :3図はそれぞれ不発pIJの一〜−1
3カイξ例を4くず回路図、でk)ろ。
j:'j', :3 figures are 1 to -1 of unexploded pIJ, respectively.
Draw the 3 examples with 4 scrap circuit diagrams.

符号説明 ト〕1・・・・・−7i’j jl+:スカ電圧、E・
・・・・・μIK動回路用電汀。
Code explanation] 1...-7i'j jl+: Scar voltage, E.
・・・・Electrical voltage for μIK dynamic circuit.

ZJ、・・・・・・負荷、Q1〜Qn・・・・−・−0
1;利便用されるスイツアングトンンジスク、Q・・−
・・・駆動用トランジスタ、A1〜An・・・・・トラ
ンジスタQl〜Qnの駆動回路、BT12〜B T n
l・・・・・・ノ(ランス用変bflr。
ZJ,...Load, Q1~Qn...--0
1; Conveniently used suites, Q...-
... Drive transistor, A1 to An... Drive circuit for transistors Ql to Qn, BT12 to B T n
l......ノ(Bflr for Lance.

器、P・・・・・・駆動)くルス発生回路、DT・・・
・・・B動トランス、R・・・・・・抵抗、D、DI 
 ・・・・・−タ゛イオード。
device, P...drive) pulse generation circuit, DT...
...B dynamic transformer, R...resistance, D, DI
・・・・・・-Diode.

CT・・・・−・変(&’dL S・・・・・・ス・イ
ツチ回路部。
CT...---change (&'dL S...Switch circuit section.

代狸人 ブ「埋土 並 木 昭 夫 代理人 弁理士 松 崎    清Daitanukito Bu “Buried Earth Namiki Akio Agent Patent Attorney Kiyoshi Matsuzaki

Claims (1)

【特許請求の範囲】[Claims] 1)並列接続スイッチングトランジスタの負荷電流バラ
ンス回路であって、少なくとも3巻線を有する原動トラ
ンスを前記トランジスタの各々毎に対応して用意し、各
トランジスタのベースとエミッタの間に、対応せろp:
、1.Q )、ランスの第1の巻にε)を接続し、各ト
ランジスタのエミッタに同じく対応せる鷹戸ノドランス
の第2の巻線の一端を接続すると共に、各トランジスタ
のコレクタから前記第20巻爵の他91蚤に至る回路を
すべて並列に接続し、さらに前記各4駆動トランスの第
3の巻縮に前記各トランジスタのコレクタ電流の和(負
荷電流)に比例した電流を流す如くし、前記g2の巻約
電流が増加するときには前記第1の巻線を流れるベース
電流が減少し、前記第3の巻m電流が増加ずろときには
前記第1の巻線を流れるベース電流が増加するように、
前記第1乃至第3の各巻線を前記駆動トランスにおいて
巻回して成ることを特徴とする負荷電流バランス回路。
1) A load current balance circuit for parallel-connected switching transistors, in which a driving transformer having at least three windings is provided for each of the transistors, and a driving transformer is provided between the base and emitter of each transistor.
, 1. Q), connect ε) to the first winding of the lance, connect one end of the second winding of the Takato transformer corresponding to the emitter of each transistor, and connect the 20th winding from the collector of each transistor to the The other 91 circuits are all connected in parallel, and a current proportional to the sum of the collector currents (load current) of the respective transistors is caused to flow through the third winding of each of the four drive transformers, and the g2 When the current in the third winding increases, the base current flowing through the first winding decreases, and when the current in the third winding increases, the base current flowing through the first winding increases,
A load current balance circuit characterized in that each of the first to third windings is wound in the drive transformer.
JP9417583A 1983-05-30 1983-05-30 Balancing circuit of load current Granted JPS59221030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9417583A JPS59221030A (en) 1983-05-30 1983-05-30 Balancing circuit of load current

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9417583A JPS59221030A (en) 1983-05-30 1983-05-30 Balancing circuit of load current

Publications (2)

Publication Number Publication Date
JPS59221030A true JPS59221030A (en) 1984-12-12
JPH0254697B2 JPH0254697B2 (en) 1990-11-22

Family

ID=14103000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9417583A Granted JPS59221030A (en) 1983-05-30 1983-05-30 Balancing circuit of load current

Country Status (1)

Country Link
JP (1) JPS59221030A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210739A (en) * 2014-11-26 2017-09-26 罗伯特·博世有限公司 For the method and apparatus for the power semiconductor switch for controlling parallel connection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210739A (en) * 2014-11-26 2017-09-26 罗伯特·博世有限公司 For the method and apparatus for the power semiconductor switch for controlling parallel connection

Also Published As

Publication number Publication date
JPH0254697B2 (en) 1990-11-22

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