JPS59219072A - Picture storage device - Google Patents

Abstract

PURPOSE:To improve the operating efficiency of a picture memory and to attain miniaturization and low cost by storing only a required part to a picture memory in a picture storage device used for the check of picture quality. CONSTITUTION:A desired area A of a displayed still picture is designated and a picture signal of a desired area designated over plural frames is stored in a picture memory 17. Thus only the required part except unnecessary part of the picture is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an image storage device suitable for use in image quality inspection in superposition management of television receivers.

[Background of the invention]

Conventionally, when manufacturing television receivers, a quality control step is provided as the final step of the production line, and the performance of the pre-vision receiver is inspected in this step.

For this performance test, methods are adopted depending on the target to be tested. One method is to project a test pattern, which is a still image, on the screen of the television receiver to be tested. There is a method for evaluating the performance of a television receiver to be inspected by inspecting the image quality of 1< turn.

Incidentally, in recent years, automation and labor saving have been promoted in the manufacturing process of television receivers, but in the quality control process, which is one of the processes, human labor is required for image quality inspection, with some exceptions. In reality, sensory tests are conducted based on visual evaluation of test patterns by experienced inspectors.

However, with this image quality inspection method based on visual evaluation,
There are problems such as individual differences in evaluation, poor reproducibility of evaluation, low test efficiency, and the need for skill in testing, making it extremely difficult to obtain objective test results. It was not possible to carry out proper quality control.

In order to solve this problem, a method has been proposed in which test patterns are automatically evaluated to obtain objective image quality inspection results.

This involves capturing an image of the test pattern displayed on the television receiver under test with a television camera, storing the image signal obtained by the television camera in an image storage device, and then reading it out with a computer. The images are then processed and image quality is inspected.

This image quality inspection method is a preferable method for inspecting the image quality of one image represented by one frame of image signal, but it can also be used to inspect the brightness and shape of the projected image, such as changes in flickering, shaking, and distortion of the projected image. Temporal changes in image quality are also not subject to image quality inspection.In fact, in the quality control process, many of the image quality inspection targets are such defective phenomena, so in order to detect such defective phenomena, it is necessary to The image memory used in the storage device must be large enough to store image signals of a large number of frames, which inevitably makes the image storage device larger and more expensive.

In addition, the defective phenomenon appeared over the entire screen, 9% appeared only at the periphery of the screen, or appeared at a specific position of the projected image, such as the boundary between projected color bars. However, the location where the defective phenomenon occurs varies depending on the cause. Therefore, even if all the image signals of a large number of frames are stored in the image memo 9, depending on the defect phenomenon to be detected, image data unnecessary for image quality evaluation may be stored in the image memo 9.
However, the utilization efficiency of the image memory decreases.

Although it is conceivable to provide a dedicated inspection device for each inspection item in order to improve the usage efficiency of the image memo 9, this would require a large number of inspection devices and would inevitably be expensive.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, reduce the capacity of an image memory for storing image signals over a plurality of frames, improve usage efficiency of the image memo 9, and reduce size and cost. An object of the present invention is to provide an image storage device having 'L2J' capability.

[Summary of the invention]

To achieve this objective, the present invention specifies a desired area of a projected still image and records the image signal of the specified desired area over multiple frames as an image memo. The feature of the book is that it is easy to read.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image storage device according to the present invention, in which 1 is an address data generation circuit, 2.
3.4.5 is a comparison circuit, 6,7°8.9 is a circuit,
10 is an AND gate, 11 is a flip-flop circuit, 1
2 is an AND gate, 13 is a black input terminal, 14 is an address sector, 15 is a start address setting circuit, 16
17 is a start signal input terminal, 17 is an image memory, 18 is a data selector, 19 is an address selector, 20 is an image data input terminal, 21 is a data bus, and 22 is an address bus.

In FIG. 1, a still image, that is, a test pattern, displayed on a television receiver to be tested (not shown) is captured by a television camera (not shown) to generate an image signal, and this image signal is converted into a digital signal. The converted data is supplied as image data from the input terminal 20 to the image memo 917 via the data selector 18.

The scanning of the television receiver to be inspected and the television camera are synchronized with each other, and furthermore, in synchronization with these, the address data generation circuit 1 generates address signals V and H. The address signals V and H represent the position of the picture tube projection surface of the television receiver to be tested, and the address gate V changes its value sequentially every horizontal period of the image signal, that is, in synchronization with the horizontal synchronization signal. The value of the address data H increases by 1 at each template point when the image signal is digitized. However, the address data ■ returns to the initial value at the starting point of one frame, and changes from value 0 to value 524 every frame, for example.
Refresh in the scanning direction of the projection screen that repeats
Memo 9 address data, and address data H
is returned to the initial value at each starting point of one horizontal scanning period, and repeats the horizontal direction of the projected image from, for example, the value 0 to the value N (where N is a positive integer) - 1° every horizontal period. This is nine fresh memory address data in the scanning direction.

On the other hand, the circuits 6, 7, 8, and 9 form an area setting circuit for setting a desired area on the projection surface of the test pattern. Now, as shown in Fig. 2, on the projected screen S of the television receiver to be inspected,
(') Point P1. Point P2 of at L' (H2, V+).
Point P6 of address (H2, V2) and address (H
Area A surrounded by lines sequentially connecting points P4 of
If we set yf circuit 6 (c&ma value V,
However, the latch circuit 7 has the value ■2, and the latch circuit 8 has the value Hl.
However, a positive value H2 is further set in the latch circuit 9.

Note that the values V+, V2, Hl, and H2 are hereinafter referred to as designated address data.

Comparison circuit 2, 3 + 4.5 *AND gate 10.
Fujitsubu flow circuit 11 and AND gate 12 (forming a determination circuit that determines whether the image data supplied from input terminal 20 is within the area set by the area setting circuit).

That is, the comparator circuit 2 compares the address data V and the specified address data V1 and sets the output level to a high level (hereinafter referred to as 〆1'') when V+ (V), and the comparator circuit compares the address data V and the specified address data V1. The comparison circuit 4 compares the specified address data V2 and sets the output level ν to 11'' when V2≧V, and sets the output level ν to 11″ when Ih<H by comparing the address data H and the specified address data H1. 1″,
Further, the comparison circuit 5 compares the address data H and the specified address data H2, and sets the output level ν to 11'' when H2≧H.

The AND gate 10 is supplied with the output signals of the comparison circuits 2, 3, 4.5, and sets the output level to 11'' when the levels of these signals are all 11''. The Fujitsubu flop circuit 11 is a Dm Fujitsubu flop circuit, and the output signal of the AND gate 10 is supplied to the data terminal, and the clock pulse from the input terminal 16 is supplied to the clock terminal voltage. Each time the output terminal Q is supplied, the level of the output signal of the AND gate 10 supplied to the data terminal is taken in, and the level of the output terminal Q is made to match the level of this output signal.

The clock pulse supplied from the input terminal 13 is used to obtain the image data supplied from the input terminal 20.
Fujitsubu flop circuit 1
When the level of the output terminal Q of 1 is 11'', it passes through the AND gate 12 and is supplied to the address counter 14 as a counting input.

Therefore, if the address data V and H from the address gator generation circuit 1 represent a position within the specified area A shown in FIG. be done.

The address counter 4 specifies the write address of the image memo 917, and is preset to a predetermined value every 7 frames by a preset signal button supplied from the start address setting circuit 15 for each frame of the image signal. ,
Each time a count input is supplied from the AND gate 12, the value is counted by 1.

The count data of the address counter 4 is sent through the address selector 19 and synchronized with the image data sent through the data selector 18. 117. For example, the image memo 917 is synchronized with the output signal of the AND gate 12, and all bits of the sampling points of the image data are
During the period required for the data to be read, the data is in the n-th write-enabled state, and for this reason, only the data at the sampling point of the image data immediately after the change in address sector 14 is written into the image memory 17.

Therefore, the AND gate 12 supplies the counting input to the address counter 14, and the data of the sampling point of the image data at 7t is entered into the image memo 917, and the AND gate 12 outputs the outputs of the comparison circuits 2, 3, 4.5. Since the level is all 11'', the image area A (Fig. 2 The inner V image data is inserted into the image memo 917.

A vertical synchronizing signal of the image signal or a pulse synchronized with this vertical synchronizing signal is supplied from the input terminal 16, and the start address setting circuit 15 generates a preset number 18 having a different value for each frame start point of the image signal. Then, perform the address kakunta 14 steps. For this purpose, in the image memory 17, a start address is designated for each frame. In this way, by specifying the start address of each frame, it is possible to distinguish the image data for each frame written into the image memory 17, regardless of the size of the setting area A (FIG. 2).

Figure 6 is an image memo! It shows the memory space allocated for each frame in J17, the start address of the first frame is Xl, the start address of the second frame is X2. The start address of the third frame is Xs, -
-------1). therefore,
In the first frame), address X+, (Xz
-1) In between, for the second frame, the address
Between 2 + (Xs-1), --- 1 --- image data is stored, and the size of the memory space for each frame is all equal, and there is a setting area A of at least the size necessary for image quality inspection. It is set to such an extent that the image data of the largest set area of (FIG. 2) can be stored.

Returning to FIG. 1, the image memory 17 can be accessed from a computer (not shown), the stored image data can be read out, and processing for image quality inspection can be performed.
A data bus 21 and an address bus 22 are provided, and when the writing of he data to the image memo 917 is completed, the data selector 18 and address selector 19 write the data bus 21 and the address bus 22 to the image memo! 117
join to.

In the setting area A (Fig. 2), the computer sets the address V on the finger to the latch circuit 6, 7, 8, 9 according to the inspection item.
+, V2. It is determined by setting H1 and H2, and the data selector 18 and address selector 19 are also controlled by the computer.

In this manner, in this embodiment, image data spanning a large number of frames can be stored using a relatively small capacity image memory 17. In addition, since only the image data of the necessary part of the projection screen is stored, it is possible to eliminate the waste of storing unnecessary image data, and the efficiency of using the Image Memo 9170 is improved. do.

Note that there are some defective phenomena such as moiré that appear on the entire screen, but in image quality inspection to detect such defective phenomena, it is generally not necessary to perform image quality inspection on the entire screen, but only on a part of the screen. It is sufficient to perform the inspection, and when inspecting the image quality over the entire screen, divide the entire screen into several partial screens,
Image quality inspection may be performed sequentially for each partial screen. Therefore, this embodiment can be applied to any image quality inspection.

In the above embodiment, the memory space for each frame in the image memory 17 was set in advance; Even when image quality is inspected, image data may always be stored in the entire memory space allocated for each frame; in this case, the latch circuits 7,
The designated address set in V2.9. H2 can be the sum of the finger addresses V+ and Hl set by the latch circuits 6 and 8, respectively, and a certain value.

Next, some examples of image quality inspection using the above embodiment will be explained.

FIG. 4 is an explanatory diagram when a color bar is projected as the iff K test pattern of a color television to be inspected, and the cross color that occurs at the boundary between the color bars is the subject of inspection, where GR is the gray area and Y is the gray area. Yellow part, Oy is cyan part, G is green part, M is magenta part, R is red part, B is back color part, B is black part, W is white part, ■ is the color of one of the color vectors Q is the hue part of the Q axis of the color old vector, P
is the imaging area of the color television camera.

When such a cross color is to be inspected, the inspection standard is to focus on the boundary between the colored part and the white part W (100%). Figure) is the hue part and white part W on the lower left side of the projection screen S in Figure 4.
latch circuit 6.7.8.9 (
Specified addresses V+, V2, Hl to be set in (Fig. 1)
, H2k is defined.

Then, the portions of the setting area A of the images of a large number of consecutive frames are sequentially stored in the image memo 917, and after the storage is completed, the computer detects noise components from the large number of stored partial images. to check the image quality.

Figures 5 (a) and (1') show the temporal change in luminance at a point at the boundary between the white area W and the hue area I in the cross-color inspection shown in Figure 4. Figure (a) shows a case where a cross color appears and the color television receiver to be inspected is not normal, and Figure (b) shows a case where the color television receiver to be inspected is normal. In this way, it is possible to determine whether the performance of the tested television receiver is good or bad based on the measurement results of brightness changes, and
This determination result is objective. When a measurement result such as that shown in FIG. 5(a) is obtained, it is determined that the color television receiver to be inspected is a defective product exhibiting a defective phenomenon such as a cross cut.

In a test for confirming the color killer operation of a color television receiver to be tested, a well-known circular test pattern having a wedge portion is projected onto the color television receiver to be tested. Then, setting area A (FIG. 2) is set in this wedge portion, the wedge portions of images of a large number of successive frames are sequentially stored in the image memo 917, and noise components are detected from these portions by a computer. The quality of the performance of the television receiver to be inspected is determined based on the magnitude of the detected noise component and how it changes.

In this way, it is possible to arbitrarily set the range of images to be stored according to the items to be inspected, which improves the efficiency of image memory usage and makes it possible to observe relatively small defects over a long period of time. This is possible with image memo 9 on the container lid.
Any image quality inspection can be performed accurately and easily in a short time, and the image quality storage device can be downsized.

Further, the setting area A (FIG. 2) includes specific addresses V1. Since it is determined by V2, Hl, and H2, the above embodiment can be applied to all types of television receivers to be inspected, regardless of the number of inches, type, etc. of the television receiver to be inspected.

Furthermore, in the above embodiment, the circular test pattern is projected onto the television receiver to be inspected, and when a predetermined number of wedges cannot be seen, a defective phenomenon is detected in a single image, as in the case of resolution inspection. It can also be applied to cases where analysis is performed only from

In the above embodiment, the size of the memory space allocated to each frame in the image memo 917 (FIG. 1) is fixed, but in other embodiments, settings can be made according to the inspection item. Image memo depending on the size of area A (Figure 2)! It is also possible to vary the amount of memory space allocated to each frame in 117.

In other words, in FIG. 1, the address counter 14 except for the start address setting circuit 15 is preset only at the start of the inspection operation and is not preset for each frame. , so that the image data of each frame is stored at consecutive addresses. Then, the start point of each frame, that is, the value obtained by adding the value 1 to the number of kakunts in the address counter 17 immediately after the generation of the vertical synchronization signal, is stored in the convoter as the start address of the frame in the image memo 917, and the failure phenomenon is analyzed. Used for dividing frames when

According to this embodiment, there is always no memory space that is not used for storing image data between frames in the memory space of the image memo 917, and the efficiency of use of the image memory 17 is further improved.

〔Effect of the invention〕

As explained above, according to the present invention, only the necessary parts of an image can be stored, excluding unnecessary parts, so that image signals can be stored over a large number of frames using a relatively small-capacity image memory. The image memory usage efficiency is improved, the time required for image storage is significantly shortened, the configuration is smaller and costs are reduced, and it can be applied to any image quality inspection. So,
The image quality inspection is made faster, more accurate, and simpler, and an image storage device with excellent functions can be provided without the drawbacks of the above-mentioned prior art.

[Brief explanation of the drawing]

Figure 1 is a professional diagram showing an embodiment of the image storage device according to the present invention, Figure 2 is an explanatory diagram showing the setting area on the screen stored in the image memory of Figure 1, and Figure 6 is an explanatory diagram showing an example of the image storage device according to the present invention. An explanatory diagram showing the memory space for each frame in the image memory of FIG. 2,
Figure 4 is an explanatory diagram when applied to the cross-color inspection shown in Figure 1, and Figures 5 (a) and (b) are examples of the test results of the cross-color inspection shown in Figure 4. FIG. 1...address data generation circuit, 2, 3, 4.5...
・Comparison circuit, 6. '7.8.9...Latch circuit, 10
...And Gate, 11...F9. flop circuit, 12...AND gate, 14...address counter, 15...start address setting circuit, 17...
image memory. Representative Patent Attorney Akio Takahashi Figure 7, Figure 2, Figure 4 (Hi) t 82, 5th edition. Be1 to

Claims (1)

[Claims] In an image storage device that is supplied with an image signal obtained by capturing a still image and stores the image signal in an image memory over a plurality of frames, it represents an address value that is synchronized with the image signal and repeated every frame. an address gator generation circuit that generates address data, an area setting circuit that sets a desired area in the still image, and an address signal from the address data generation circuit that is supplied to set the address value represented by the address signal to the desired area. a determination circuit that generates a pulse when the pulse is within the range of
By setting the cacunto value of the i address data as the glance address of the image memory, the image signal of the desired area set in the still image can be stored in the image memory for each frame of p1. An image storage device characterized by being configured as follows.