JPS59216260A - Memory controlling system - Google Patents

Abstract

PURPOSE:To increase a memory having a generality by assigning an address which overlaps a part of an address of the first memory, to the second memory, so that the second memory is driven preferentially. CONSTITUTION:I/O control cards 5, 6 and an RAM are overlapped and have the same address, and a memory operation inhibiting line 7 is provided between them. The memory operation inhibiting line 7 drives preferentially a memory of the I/O control cards 5, 6, when an address of the memory contained in the I/O control cards 5, 6 is brought to access, as an overlapped address space against an RAM 4. That is to say, a signal for inhibiting an operation of the RAM 4 is sent out through the memory operation inhibiting line 7 to the RAM 4 from the I/O control card 5 or 6. Usually the memory of the I/O control cards 5, 6 is mainly brought to access, and a prescribed information is written or read out.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] This invention relates to a device that is used when the mounting state of memory changes due to the addition of devices with a small capacity memory, such as an I10 control card (input/output interface circuit section). The present invention also relates to a memory control method that allows easy processing of the state and allows expansion of memory in units of predetermined memory capacity.

[Prior art and its problems]

In a computer system having a processing device such as a microprocessor, a plurality of memories are arranged on a common bus, and these memories are accessed to execute predetermined processing.

Here, these memories include a ROM that stores fixed control programs, O3, etc. as a main storage device, and a RAM that stores predetermined programs and information.
Furthermore, I as a device with a built-in small capacity memory
There are 10 control cards and other memories.

Here, these memories are optimally placed in a limited address space determined by design.

FIG. 1 is a block diagram of a typical conventional computer system mainly based on such a microprocessor, and FIG. 2 is an explanatory diagram showing an example of address space allocation in the memory implementation state.

In the figure, 2 is a processing device mainly composed of a microprocessor, which is connected to a ROM 3 and an R
AM4. And, they are connected to I10 control cars 1-5 and 6, respectively.

Here, the address space determined by common bus 1 is 3
2 kilowords (kW), and currently ROM3 is 8kW.
, two RAMs 4 with capacity of 8kW x 2 = 16kW are arranged, and memories owned by I10 control cards 5 and 6 each have capacity of 1kW and are respectively mounted.

As for the address space allocation in such a case, as shown in the example of the implementation state shown in FIG. Memory 1kW x 2 = 2kW
An area of 8 kW x 2 = 16 kW of the RAM 4 is set after that, leaving a free area of 6 kW.

Now, regarding the address space determined by the design of the common path 1, the layout shown in FIG. 2 has the following problems.

■Inability to use free space effectively. That is,
The free space in Figure 2 is 6kW, but generally the units that are easy to expand are 8kW, 16kW, which is a multiple of 8.
W, etc., and 6kW is not versatile. Moreover, I10
This free space may change due to the addition of devices with small-capacity memories such as the control cards 5 and 6, and this free space has become an area that is difficult to use.

■By the way, in computer systems, as a method for detecting abnormalities such as runaway programs, the system is designed so that an error occurs when an unimplemented area of memory (the free area in Figure 2) is accessed. is common.

In the example of FIG. 1, the I10 control cards 5 and 6 have small capacity built-in memories, but the processing device 2 always
Implementation of small capacity devices such as 0 control cards 5 and 6!
It is necessary to know (whether or not an I10 control card etc. is installed).

For example, such processing can be done by providing a data register (or status register) to recognize the I10 control card, etc., or by providing a data register (or status register) in the program (software).
It is necessary to take measures such as setting the presence/absence of the data in advance (on the table).As a result, there is a problem that the processing becomes complicated and troublesome.

[Purpose of the invention]

This invention has been made in view of these problems, and in addition to eliminating such problems, it also improves the address space allocation and implementation when installing devices with small memory capacity. The purpose of the present invention is to provide a memory control method that allows easy expansion of general-purpose memory in a free area.

[Key points of the invention]

The feature of the memory control method of the present invention for achieving such purpose is that the first
．． A computer system comprising a second memory,
Addresses that overlap with at least part of the addresses of the first memory are assigned to the second memory, and when an overlapping address is designated, the second memory is driven preferentially.

By doing this, it is possible to connect to the bus in an address overlap state regardless of the capacity of the address space determined by the common bus, and it becomes easy to allocate the address space of a device having a small capacity memory and to implement it. Moreover, since it can be mounted redundantly, general-purpose memory can be added to the free space.

[Embodiments of the invention]

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 3 is a block diagram of an embodiment of a computer system using the memory control method of the present invention, and FIG. 4 is an explanatory diagram showing the implementation state of memory in the address space. , FIG. 5 is a timing chart illustrating how the memory is accessed in the embodiment shown in FIG. In FIG. 3, the same components as in FIG. 1 are indicated with the same reference numerals.

1. The main structural differences between the embodiment shown in FIG. 1 and the embodiment shown in FIG. 3 are the I10 control cards 5 and 6 and the RAM 4.
and the same address is duplicated, and a memory operation prohibition line 7 is added between these I10 control cards 5 and 6 and the RAM 4.

This memory operation prohibition line 7 plays the role of a hash line connecting each memory, and the addresses of the memories built in the I10 control cards 5 and 6 are designated (accessed) as an overlapping address space for the RAM 4. sometimes,
This is provided to give priority to driving the memories of the I10 control cards 5 and 6, and prohibits the operation of the RAM 4 from the I10 control card 5 or 6 via this memory operation prohibition line 7. A signal will be sent out.

By doing this, the memory operation prohibition line 7 establishes a master/slave memory relationship between the memories of the I10 control cards 5 and 6 to which duplicate addresses are assigned and the RAM 4. And usually I10 control cards 5 and 6
The memory is mainly accessed and predetermined information is written to or read from the memory.

Next, an example of address space allocation in this computer system will be explained based on FIG. 4, which is shown in comparison with FIG. 2, which is a conventional one.

As shown in the example of the implementation state of the address space 32kW shown in Fig. 4, 8kW of ROM3 is installed at the beginning of the address space.
, and then a 1 kW x 2-2 kW area of memory for the I10 control cards 5 and 6. Then, in the 2kW portion of the memory owned by these I10 control cards 5 and 6, the 2kW of that address is stored.
The first 8kW of RAM4 is arranged so that the parts overlap. Then, following this, the second
The second 8kW is installed. As a result, an area of 8 kW or later is secured as a spare address space.

Here, the first area of the actual RAM 4 is 6 kW, but this is possible if an 8 kW one is installed in advance and the I10 control car 1-5 or 6 is removed.
It may be possible to use a corresponding area of RAM 4 that overlaps with this, and if the I10 control carts 5 and 6 are installed as a basic configuration, as an actual implementation,
A 6kW RAM 4 may be installed in only the first one.

Therefore, the address space after ■/○ control cards 5 and 6 is assigned to the next small-capacity device with a small-capacity memory that is added, and these addresses overlap with the first card of RAM 4. address.

In this case, it goes without saying that at least one of the I10 control cards 5 and 6 may be removed and a small capacity device having a memory capacity of 1 kW to 2 kW or more may be connected thereto.

In this way, small-capacity devices can be added to or deleted from the RAM 4 as appropriate in the M cross section, and this addition or deletion can be made without any special processing on the processing device 2.

Next, the specific operation of the memory access process of this computer system will be explained based on the timing chart of FIG.

FIG. 5(a) shows the waveform of the memory drive signal (MDV in the figure) sent by the processing device 2 onto the control line of the common lot 1, and FIG. FIG. 5 (C
) is I1 when accessing overlapping address spaces.
0 shows the operating waveforms of the 0 control card 5 or 6.

First, in FIG. 5(a), the processor 2 specifies the address of the RAM 4 that has not been allocated redundantly, lowers the memory drive signal, turns it into the "ON" state, and transfers this memory drive signal to the common bus. 1 on the control line, as shown in FIG. 5(b), after a predetermined time delay in response to this falling signal, the RAM 4 lowers the memory access signal and starts the memory access. . Then, a predetermined write or read operation is performed on the address specified by the processing device 2, and when this is completed, a REDY signal is sent as the operation completion signal.
A signal is placed on the control line of the common bus 1 and the processing device 2 is notified of this.

The processing device 2 receives this REDY signal and performs the processing in FIG. 5(a).
) and turn it off.
” state. The RAM 4, which has received this “OFF” state via the common bus 1, receives the memory access signal and the RE
The D'Y signal is raised to turn it into an "OFF" state and the operation is completed.

On the other hand, in the area where the memory of the I10 control card 5 or 6 to which duplicate addresses are assigned as shown in FIG. ” state and sends out this memory drive signal, the RAM 4 and whichever I10 control card 5 or 6 with the corresponding address to be accessed will receive it. That is, the I10 control card 5 or 6 having the memory on the main side learns that its own memory has been accessed from the address sent from the processing device 2 side, and the RAM 4 on the slave side lowers the memory access signal (black). As shown in FIG. 5(c), in response to this fall, a memory operation inhibit signal (MLK in the figure) is placed on the memory operation inhibit line 7, and via this, the RAM 4 Send to.

Upon receiving this, the RAM 4 stops its operation in response to the memory operation prohibition signal from the memory operation prohibition line 7, and when its own address is specified by the processing device 2, even if
Even if this is detected, a memory access signal (see dotted line in the figure) is not generated.

Here, (10) the control card 5 or 6 lowers the memory access signal after a predetermined time delay after the lowering of the memory drive signal, and starts memory access of the memory. Then, a predetermined write or read operation is performed on the address specified by the processing device 2, and when this is completed, a REDY signal is placed on the control line of the common lotus 1 as the operation completion signal, and the processing device 2 will be notified of this.

Similarly to the above, the processing device 2 receives this REDY signal and raises the memory drive signal shown in FIG. 5(a),
Turn this into the “OFF” state. If the I10 control card 5 or 6 receives this “OFF” state via the common lotus 1,
Raise the memory access signal and REDY signal,'
○FF” state and the operation ends.

The operation of the RAM 4 is prohibited during this time. Therefore, the REDY signal (see dotted line in the figure) is not generated either.

By doing this, in the address spaces to which duplicate addresses are assigned, the memories of the I10 control cards 5 and 6 on the master side are accessed preferentially in a master-slave relationship. As a result, even if a device with a small memory capacity is added to the address space of the overlapped area, or even if the already installed I10 control card 5 or 6 is deleted, confusion in memory access will not occur. do not have.

Furthermore, as shown in FIG. 4, in the free address space provided as a spare, it is possible to add a general-purpose memory of, for example, 8 kW.

Note that if the I10 control card 5 or 6 is not installed, the memory operation prohibition signal will not be generated from the I10 control card 5 or 6, so the RAM 4 will use the own address of the processing device 2 as in the case where the addresses do not overlap. By specifying this, this is detected and the corresponding action is performed.

Here, if it is desired to access the overlapping portion of the slave side RAM 4, the operation of the ■/○ control car 15 or 6 is prohibited in advance, and the access can be made freely.

By the way, the RAM 4 is one of the first specific examples of memory in this invention, and the memory owned by the I10 control card 5 or 6 is one of the second specific examples of memory in this invention.
It is one.

As explained above, in this embodiment, in order to preferentially access one memory, the memory operation prohibition line 7 is provided between the I10 control cards 5 and 6 and the RAM. It may be provided directly between the memory and RAM of each of the I10 control cards 5 and 6.Also, without using such a configuration, an operation prohibition signal may be sent from the processing device 2 via the common path 1 when the overlapping portion is operated. RAM
4 or I10 control card 5 or 6 to inhibit the operation of one of them.

Further, in the embodiment, the I10 control carts 5 and 6 are the main side, and the RAMA side is the slave, but it is sufficient if either one is the master and the other is the slave.

Therefore, in the present invention, it is sufficient if one of the memories is driven preferentially.

Further, the overlapping memory area does not have to be all of one memory, but may be a part of it.

In this case, it goes without saying that other portions may be allocated and used as free address space (spare area space).

Here, the free address space is not limited to 8kW and can be freely set according to the memory to be added.
Furthermore, the design of the address spaces in the overlapping portions allows even non-universal memories to be installed.

Further, although the embodiments mainly describe a processing device mainly based on a microprocessor, the present invention is not limited to such a processing device, and can be applied to a processing device in which a plurality of memories are arranged on a common bus. It can be applied to any computer system.

〔Effect of the invention〕

As can be understood from the above description, the present invention provides a first... A computer system comprising a second memory, which allocates to the second memory an address that overlaps at least a part of the addresses of the first memory, and when an overlapping address is specified, the second memory Since it is driven preferentially, it is possible to implement a device with a small capacity memory such as a 110 control card as a processing device! 3 (whether or not an I10 control card, etc. is installed) is not necessary for processing, which simplifies the processing of the processing device, etc., and facilitates the addition or deletion of devices with small capacity memory. In addition, free space can be used effectively, and in particular, versatile memory can be expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a typical conventional computer system based on a microprocessor, FIG. 2 is an explanatory diagram showing an example of the allocation of atlus space in the state of memory implementation, and FIG. 3 is an illustration of the present invention. FIG. 4 is an explanatory diagram showing the state of memory implementation in the address space, and FIG. 5 is a block diagram of an embodiment of a computer system to which the memory control method of FIG. FIG. 3 is a timing chart diagram illustrating how to access memory. 1- Common lotus 2- Processing device 3-ROM 4-RAM 5, 6-I 10 Control card 7- Memory operation prohibition line Patent applicant Fuji Electric Manufacturing Co., Ltd. Fuji Facom Control Co., Ltd. Agent Patent attorney Tetsuya Mori Patent attorney Naito Yoshiaki, Patent Attorney, Shimizu, Patent Attorney, Horide Bond Principles Diagram 1

Claims (2)

[Claims] (1) a processing device, a first memory connected to the processing device via a bus, and a first memory commonly connected to the bus and having an address that overlaps at least a part of the addresses of the first memory 1. An information processing apparatus comprising: a second memory; and a memory control method, characterized in that when the processing apparatus specifies an address of the overlapping portion, the second memory is driven preferentially. (2) The second memory is built in a small-capacity device connected to the bus, and the first memory and this small-capacity device are connected by a signal line, and the overlapping portion is When an address is designated, the small capacity device sends an operation prohibition signal to the first memory via the signal line, thereby preferentially driving the second memory. Claim 1
Memory control method described in section.