JPS59213098A - Memory protecting system - Google Patents

Abstract

PURPOSE:To supply a storage protecting power of a stable output voltage to a memory part even when an input power source is turned off, by stopping a CPU part with power-off and breaking the power supplied to the CPU part and the memory part when the input power source is turned off. CONSTITUTION:When the input power source is turned off and the input power level falls to a point A, an input voltage comparing circuit 3 raises the waveform of a power-on/off signal (c) from the high level to the low level to detect the turn-off state of the input power source, and a CPU part 8 is stopped with power-off. The power-off signal is delayed in a delay circuit 10 by a time T2 and turns off an output voltage control part 12 to break a power (j) supplied to the CPU part 8 and a memory part 9. When the input power level falls furthermore to reach a point B, the output of a power supply part 1 falls as shown by a waveform (b), and the storage protecting power falls also as shown by a waveform (g). When the power source voltage becomes lower than the voltage of a battery 7, the voltage of the battery 7 is supplied as the storage protecting power to the memory part 9 through a diode D2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory protection method for retaining the stored contents of a memory section using a battery when the input power source is turned off.

First, a conventional memory protection method will be explained using FIGS. 1 and 2. Figure 1 is a diagram showing the conventional memory protection method, and Figure 2 is a waveform diagram of each part in the conventional method. With circuit (3).

Delay circuit (4) with delay time T1 and its delay circuit (
A power ON detection circuit (5) which takes the wave-differentiation of the output of 4) and generates a power ON detection signal, and a power OFF detection circuit (5) which takes the wave-tail differentiation of the input voltage comparison circuit (3) and generates a power OFF detection signal. A memory protection control unit consisting of a circuit (6), a batch (7), a charging current limiting resistor (R), and a backflow prevention diode (IX) (D2).

(8) is the central processing unit (OentraIProces).
sing Unit 1 or less CPU section, (9)
is a memory section that holds the work contents and data contents of the CPU section (8).

Next, the operation will be explained with reference to FIG. 2, which shows the waveforms at each point in FIG. The voltage waveform in Figure 2 (a) is the input power supply (DC
When the input power level reaches point B, the output of the power supply section (1) outputs a regulated constant voltage CP.
It is supplied to the U section (8) and the memory section (9). Also, the power supply section (
The output of 1) charges the batch 71 through the diode (Dl) and the resistor (R), and also supplies the voltage of the waveform (g) to the memory section (9) through the power supply for memory protection.

When the input power level increases further and reaches point A.

The input voltage comparison circuit (31) generates the waveform (c), and its output is delayed by a time T1 in the delay circuit (4) to generate the waveform (d). The output becomes the waveform (E) in the power ON detection circuit (5) and is sent to the CPU section (8).
Turn on the power of section (8) and start it.

Next, when the input power source is turned off, when the input power source drops to point A, the input voltage comparison circuit (3) causes the waveform (c) to fall. The waveform is used to generate a power OFF detection signal (to) in the power OFF detection circuit (6), and the CPU section (8)
The CPU section (8) is powered off and stopped. When the voltage waveform level in (a) further drops to point B, the output of the power supply section f1) becomes unable to be regulated, and the output voltage of the power supply section (1) drops by ζ as shown in (b). Furthermore, as the voltage (b) drops, the memory protection power supply also drops as shown in (g). When the voltage of (C1) becomes equal to or lower than the voltage of batch January 7), the voltage of batch January 7) is supplied to the memory section (9) as a power supply for memory protection via the diode (D2).

However, when the output voltage of the power supply section (1) drops to the 0 point (0), multiple ICs mounted in the CPU section (8) and memory section (9) simultaneously change from the ON state to the OFF state. Therefore, the load current of the power supply section (1) suddenly changes,
In addition to generating noise, the memory protection power supply suddenly drops below the battery voltage as shown at point D in (g), which has the disadvantage of destroying the stored contents of the memory section (9).

The present invention has been made to improve these drawbacks, and provides a memory protection method for stably protecting the stored contents of the memory section (9) when the input power is turned off.

An embodiment of the present invention shown in FIG. 3 will be described below with reference to waveforms of various parts shown in FIG. 4.

FIG. 3 is a diagram showing a memory protection method of the present invention.

FIG. 4 is a waveform diagram of each part in this invention.

In the figure, fil~(9) is the same as in FIG. al
lI is delay time T2 17) Delay circuit, U is OR circuit,
α2 is an output voltage control unit that controls the power supply to the CPU unit (8) and memory unit (91). Here, the delay circuit α
The delay time '1'2 of [is the input voltage comparator circuit (3)
After detecting that the input power is off, the CPU section (8) turns the power off.
This is the time when the FF stops at Violet.

Next, the operation will be explained. The explanation of the process in which the input power source rises and reaches a predetermined constant voltage in Fig. 4 (a) is as follows.
The explanations are the same as those in Figures 1 and 2, except for Figures (G), (IJ), and (IJ). The output of the delay circuit aα is:

Waveform '1l-T of output (c) of input voltage comparison circuit (3)
2 It is a time-delayed waveform, and the output 4 of the OR circuit aυ is the output of the input voltage comparison circuit +31 (J and the delay circuit fi
It is the logical sum of the waveforms of 0's output Q), and the waveform of (I sword is "
At the "High" level, the output voltage control section a2 is in the ON state, and the voltage of the output (b) of the power supply section (1) is set to the CPU section (8).
) and the memory section (9). Next, when the input power is turned off, when the input power in (a) drops to point A,
The input voltage comparator circuit (3) lowers the waveform (c) from the "High" level to the "LOW" level, detects the input power off state, and turns off the power to the CPU section (8).
F Stop.

On the other hand, the waveform (c) is delayed for T2 time by the delay circuit a1M, and then the output voltage controller a2 is turned off and the CPU
(8) and the memory unit (9). The input power level of (A) further drops and B
When this point is reached, the pressure in the power supply unit (1) drops as shown in the waveform (middle), and as the power supply in (b) drops, the memory protection power supply also drops as shown in the waveform (g). When the voltage of the battery (7) becomes lower than the voltage of the battery (7), the diode (
The voltage of batch 7) is supplied to the memory unit (9) via D2) as a memory protection power source.

As described above, according to the present invention, when the input power is turned off, the c
PUN! , f power is turned off, and
By shutting off the power supply to the CPU section and the memory section, it is possible to supply a memory protection power supply with a stable output voltage to the memory section even when the input power is turned off.

Furthermore, when the input power source is turned off, a memory protection power source with a stable output voltage can be supplied to the memory section, which has the effect of stably maintaining the stored contents of the memory section.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional memory protection method, FIG. 2 is a waveform diagram of each part in the conventional method, and FIG. 3 is a diagram showing the waveforms of various parts in the conventional method. FIG. 4, which is a diagram showing the memory protection system of the present invention, is a waveform diagram of each part in the present invention. In the figure, (11 is a power supply unit, (2) is a storage control unit, (31 is an input voltage comparison circuit,
(4) is a delay circuit, and (5) is a power ON detection circuit. (6) is the power OFF detection circuit, (the power is batch lJ, +
Reference numeral 81 indicates a CPU section, (9) a memory section, 011 a delay circuit, a U-OR circuit, and 12 an output voltage control section. Note that the same or equivalent parts in the figure are indicated by the same reference numerals. Yes. Agent Masuo Oiwa Figure 1 Figure 2 (A) Figure 3 Figure 4

Claims (1)

[Scope of Claims] A power supply unit that generates a predetermined electric power, a central processing unit connected to the output end of the power supply unit and having arithmetic processing capability, and work contents and data contents of the central processing unit. The memory protection control unit includes a memory section consisting of a plurality of volatile memory elements that hold the memory, and a memory protection control section that senses the input power status and has a battery that supplies power to the memory section when the input power is turned off. In a memory protection method that retains the memory contents of the memory unit when the input power is turned off. When the input power is turned off, the memory protection control section sends a power-off signal to the central processing section to stop the power-off processing of the central processing section, while the power supply section can be regulated. Memory protection characterized in that by cutting off the power supply to the central processing unit and the memory unit, the stored contents of the memory unit are protected from noise generated when the input power is turned off. method.