JPS5921221B2 - digital to analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a converter that converts a digital signal to an analog signal, and particularly aims to obtain a converter with non-linear conversion characteristics.

A conventional digital-to-analog converter (hereinafter referred to as a D/A converter) using two capacitors is shown in FIG.

One end of the capacitor 1 is grounded through a switch 12, the other end is connected to a terminal 14 through a switch 13, and one end of a capacitor 16 through a switch 15, and the other end of the capacitor 16 is grounded.

The connection point of switch 15 and capacitor 16 is output terminal 1
Connected to 7.

As a first preparation, the switches 12, 13, and 15 are respectively turned on, the terminal 14 is brought to ground potential, and the two capacitors L16 are discharged.

This N converts the digital input into binary numbers dkdk 1...
...dl (dk is the most significant bit, dl is the lowest bit)
It is expressed as

From that state, only the switch 12 is opened, and the input voltage d1■o (dl is 1
0, vo is the reference voltage) is applied to the terminal 14.

As a result, the charge is redistributed, and the output voltage vo at terminal 17 becomes
Here, it is assumed that the capacitance values of the capacitors 11 and 16 are equal to each other.

Next, the switches 12 and 13 are closed, the switch 15 is opened, and the terminal 14 is brought to the ground potential to discharge the charge in the capacitor 11.

At this time, the charge in the capacitor 16 is held.

Next, switch 12 is opened, switch 13 is closed, and the voltage d2V corresponding to the second bit from the lowest digital input is set.
When O (d2 is 1 or O) is applied, the charge is redistributed and the voltage Vout at terminal 17 becomes ■out-1/2・d2■o+(1/2)2d1■o(
2).

If this process is repeated several times, the output voltage at terminal 17 will be Vout-Σ(2'-'/2k) d t VO+
i21 di=1 or 0(3).

In this way, bit linear D/A conversion can be performed using the 2I hard capacitors 11 and 15.

On the other hand, a communication D/A converter requires a nonlinear converter that approximates 15 polygons of the μm255 rule.

The 15-line approximation of the μm255 rule has eight segments, and each segment consists of 16 steps.

Each step divides the segment equally, but the step of the second segment is twice as large as the step of the first segment, and the step of the third segment is twice that of the second. Each step doubles as a dog.

Because of this non-linear characteristic, it is necessary to add a compandor to the linear converter shown in FIG. 1 for communication purposes.

Therefore, the number of constituent circuits increases accordingly, making it unsuitable for downsizing the converter.

This invention uses a capacitor and a group of switches to realize a digital-to-analog converter having μm255 law and 15-fold line approximation characteristics in the converter itself, and will be described in detail with reference to the drawings from FIG. 2 onwards.

One end of the capacitor 21 is grounded through a switch 22 and connected to one end of a capacitor 24 through a switch 23, and the connection point of the capacitor 24 with the switch 23 is connected to one end of the capacitor 26 through a switch 25, and the connection point with the capacitor is grounded through switch 27.

The other end of the capacitor 21 is connected via a switch 28 to a digital signal (step) input terminal 29 and the ground, and the other ends of the capacitors 24 and 26 are grounded.

On the other hand, one end of the capacitor 31 is grounded through a switch 32 and connected to one end of a capacitor 34 through a switch 33, and the connection point thereof is connected to an analog signal output terminal 36 through a buffer amplifier 35 as required.

The other end of the capacitor 31 is connected to a digital signal (segment) input terminal 39 through a switch 31 and further through a switch 38, and the connection point of the switches 37 and 38 is connected through a switch 41 to the output side of a buffer amplifier 42.
The input side of the amplifier 42 is connected to a connection point between the switches 25 and 27 and the capacitor 26.

The capacitance of capacitors 21 and 24゜26 is 1 each:
1:32, and the capacitors 31 and 34 have the same capacity.

μm255 rule, segment and step of digital input signal in 15-line approximation are each 13e2 in binary scale.
11 and rn4 m3 m2 rn 1, that is, expressed in 7 bits, and the operation will be explained in the case of a positive signal.

The same wrinkle occurs in the case of a negative input signal.

According to this notation, the digital-to-analog conversion formula using the μm255 rule and 15-fold line approximation is L-1 V = k (2L' +1+ -(,M-1))V
.

16.5 It can be expressed as

Here ■ is the analog output voltage, L-Σ#-21-',
M=Σrrz21-1, ! l=t i=1 Vo is a reference voltage, and k is a positive number.

First, the switch 25 is left open, and the charge redistribution described in FIG.
Sequentially the voltage corresponding to 2 m 1 (rnl 1)
Voy = 2Vo.

Repeat 4 cycles as rn3 V□ r rl14 V□.

At this time, the voltage (■) at one end of the capacitor 24 becomes Σ□·m i V□ ·−24 −1 at 2 i−1 (2) from equation (3).

Then switch 28 is closed and input terminal 29 is brought to ground potential, and switches 22 and 23 are alternately turned on to redistribute the charge between capacitors 21 and 24. -L+1 times (in this 5, K
2 ≧ I, -1 integer, L-Σl, 2 i-1, i.e. segment number) Opening/closing i=x and the voltage at the contact point of the capacitor 24 with the switch 25 ■1
becomes the following equation (4) using equation (3).

K21-10m.

■−Σ□Vo (replace with m1→ −・=・2゛−”+゛ □1−1) (4) 2
L-1M-1 =--Vo (5) 2K 1 to 5, M2 Σm・2 t (6)i
=1 Next, only the switch 25 is closed and the charge is transferred to the capacitor 24,
It is redistributed among 26.

The capacitance value of the capacitor 26 is 1/ that of the capacitor 24.
32, the voltage VY on the input side of the buffer amplifier 42 is as follows.

;u2 ■7-3T3■, (7) 2L-1yll =□・□・Vo(8) 2 to 16.5 The period (clock) required for the above operation is 4+(K-L+1
>+1=to -L+6.

Independently and simultaneously with the series of operations described above, the switch 38 is closed and the digital input signal 13121. A voltage corresponding to the voltage is applied to the terminal 39 to apply charge redistribution to the equal capacitance value capacitors 31 and 34.

The input signal voltage to the input terminal 39 is xi (i=1.2,
.......

K), and the charge redistribution shown in FIG. 1 is repeated periodically.

In this 5, 1; i=1.2. ......, L-1x
1-(9) O; L, L+1.・・・・・・・・・.

The output voltage ■X at the output terminal 36 after K times of charge distribution is given by equation (3), I ■X−Σ□■o00) i=1 2■ m−(2L−1))vo (102 becomes.

The period required for the above operation is K. Finally switch 41
is closed and switch 38 is opened to connect capacitors 31 and 34.
redistribute the charge between the two.

The final output voltage V at the output terminal 36 at that time is V=-(v
x+vy) (12)2L-1: (2L'-1+-(M-1))2
K +1 16.5 Vo(13).

Therefore, the output voltage is the digital signal input (segment 13
1211. Step m4 = 3 rn2 mH), the μm255 rule and the polygonal line approximation are satisfied.

L is the segment number expressed in decimal as mentioned above, M is the step number expressed in decimal as shown in equation (6), and L is set to 0, 1...8, By substituting 0.1 .

Here, K is an arbitrary integer, but is selected to be 1-max (L-1) = 7 in order to minimize the number of repetitions of charge redistribution.

Using the D/A converter described above, a feedback type analog/digital converter can be constructed as is known.

FIG. 3 shows an example of its configuration.

The input signal of the input terminal 40 is applied to the input terminal 39 of the D/A converter 42 shown in FIG. The control circuit 44 controls opening and closing of the switches of the D/A converter 42 in a predetermined order via the switch 1 drive circuit 45.

This process is repeated until the output of the D/A converter 42 becomes closest to the ground potential.

1''' of the output of the comparator 43 for each control of each switch.
or 'O'' is stored in the latch circuit 46, and finally the signal stored in the latch circuit 46 is sent out from the terminal 47 as a converted digital output.

As described above, according to the D/A converter according to the present invention, since the D/A converter itself has non-linear conversion characteristics, μm2
Since the conversion that satisfies the F.55 rule is performed, there is no need to combine a compandor in addition to the D/A converter.

Further, if a conventional feedback type A/D converter is constructed using this D/A converter, an A/D converter satisfying the μm255 rule can also be obtained.

As can be understood from the above explanation, relative accuracy of the capacitance value is required in the partial voltage generation operation because the capacitor 21
, 24.26 and between capacitors 31.34.

That is, only the relative accuracy of the capacitance values of the three and two capacitors is required.

Generally, when manufacturing capacitors on an integrated circuit board, M
Although the O8 structure is adopted, due to variations in etching, oxide film thickness distribution, etc., it is necessary to increase the area of the MOS capacitor in order to obtain high accuracy in relative capacitance value.

According to the converter of the present invention, since the number of capacitors is small, even if the area of the MOS capacitor is increased, its proportion in the converter is small.

Conversely, if there is a problem with etching accuracy, etc., the area of the MOS capacitor can be easily increased.

Furthermore, it is only necessary to consider the relative accuracy of 2 and 3, so
Layout design is easy.

Furthermore, since the capacitor holds the input signal, no input holding circuit is required.

Therefore, the design is easy and the occupied area can be reduced.

From these points, the converter of the present invention is suitable for integration into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing a conventional D/A converter, FIG. 2 is a connection diagram showing an embodiment of a D/A converter according to the present invention, and FIG.
The figure is a block diagram showing an A/D converter using the D/A converter of the present invention.

Claims (1)

[Claims] 1 One ends of the first, second, and third capacitors 21, 24, and 26 are connected in parallel via the first and second switches 23 and 25, and the first capacitor 21 and the first switch 23 are connected to the third switch 22.
is grounded through the third capacitor 26 and the second capacitor 26.
The connection point of the switch 25 is grounded through the fourth switch 27 and connected to the input terminal of the buffer amplifier 42, and the other end of the first capacitor 21 is connected to the fifth switch 2.
8 to the first input terminal 29 and ground, and the other ends of the second and third capacitors 24.26 are grounded, respectively, and the first, second and third capacitors 21.24 The ratio of the capacitance values of .26 is selected as 1:1:1732, and one ends of the fourth and fifth capacitors 31 and 34 are connected in parallel via the sixth switch 33, and The connection point of the switch 33 of 6 is the 7th
The other end of the fourth capacitor 31 is connected to the second input terminal 39 via the eighth switch 38 and to the output terminal of the buffer amplifier 42 via the ninth switch 41. The other end of the fifth capacitor 34 is grounded, and the fourth and fifth capacitors 34
The ratio of the capacitance values of the capacitors is selected to be 1:1, and the step m4 m 3 m 2 m 1 and segment 131211 (m4 + m3 + m2 Hml
) 13H12 and 11 are connected to digital input signal lines into which 1 or O) is input, an output terminal is led out from one end of the fifth capacitor 34, and when the second switch 25 is open, the 1, 3rd,
The fifth switch 23, 22, 28 is closed and the fifth switch is set to the ground side to discharge the first and second capacitors 21.24, and from that state the fifth switch is set to the first input terminal 29 side and the third Open only the switch 22 and apply the input digital signal (rnll) V□ to the first input terminal 29,
Open the first switch 23, close the third and fourth switches 22, 28, set the fifth switch to the ground side, discharge the charge in the first capacitor 21, open the third switch 22, and close the third switch 22. Set switch 5 to the first input terminal side,
Apply the input digital signal m2Vo to the first input terminal 29, and apply the same input digital signal m3V01 m4 below.
V010.0 + -・”0 (Ohani-L+1ko, K
repeat for segment numbers (larger integers),
After that, the fifth switch is set to the ground side, and then only the second switch 25 is turned on to connect the second and third capacitors 24 and 26.
In the same manner as in the supply of the input digital signals m4 to m, the ground potential is applied to the second input terminal, and the digital signals 13Vo, l! 2V□
, 111V□ are controlled in the same way by making the sixth, seventh, and eighth switches 33.32.38 correspond to the first, third, and fifth switches 23.22.28, respectively. and input digital signal x lV□ (i= 1, 2, . . . □) to the second input terminal 39.
...at L 1, xi = 1, i = L, L+
1-"K and xi=O) to perform charge redistribution in the same way, and finally close the sixth and ninth switches 33 and 41,
A digital-to-analog converter comprising control means for controlling opening of seventh and eighth switches 32 and 38.