JPS59211367A - No.5 signal processing system - Google Patents

Abstract

PURPOSE:To relieve the load of a central processing unit by providing a processor for processing signal to a line signal transmitting/receiving section and using it so as to convert line signal information into a logical signal suitable for the processing of the central processing unit. CONSTITUTION:The change point of line signal information on a line 100 is detected by using the 1st dropper 200, a line signal receiver 201 and the 1st interface 202 and it is transmitted to a processor 400 for processing signal. The processor 400 analyzes the state depending on this information and information of each line stored in an RAM402, converts the information into a logical signal representing start, response or the like and transmits the signal to the central processing unit via an inserter cue 204 and a highway 101. When the logical signal representing start, response or the like is given from the central processing unit to the processor 400 via a highway 103, the processor 400 controls a line signal transmission section 301 in response to this signal and transmits a line signal to a designated line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an N.
o. 5 Regarding signal processing systems, in particular, it relates to a signal processing system that reduces the load on the central processing unit when the central processing unit processes the reception and transmission of line signals of major channels on Digital No. 1.

Conventionally, the processing of No. 5 signals in international exchanges has been carried out by a central processing unit that scans the on/off status of earth signals.
Transmission and reception processing is performed by directly accessing a signal device provided for each line in the form of an SCN.

There is also a method in which a signal processing processor is interposed to share the load on the central processing unit, but in this case as well, the processor processes the line by combining binary signals corresponding to the presence or absence of the two types of line signals FitF2. It interfaces with the central processing unit using signal information (physical signals). Therefore, a physical signal corresponding to the presence or absence of the line signal F"u F2 is input to the central processing unit, and all analysis and judgment of input/output signals must be performed on the central processing unit side. Therefore, the load on the central processing unit is The disadvantage is that it becomes very large.

An object of the present invention is to solve the above-mentioned conventional drawbacks, and to enable a signal processing processor provided in a line signal transmitting/receiving section to convert line signal information into logical signal information suitable for processing by a central processing unit. The object of the present invention is to provide a No. 5 signal processing method that can reduce the load on a central processing unit by interfacing with the above logic signals.

The signal processing method of the present invention includes a first dropper that distributes and outputs the line signals of each channel of the receiving side digital Reno-Iway line, and a first dropper that demodulates the output signal (of the first dropper) to generate two types of line signals. A line signal receiver that detects and stores binary signals corresponding to the presence or absence of each line signal, and scans the line signal receiver to detect changing points of the line signal and sends the line signal information to the microprocessor described later. interpreting and activating the first ink 7 process circuit that supplies the ink and the line signal information output from the interface circuit;
It is converted into a logical signal indicating a response, etc., and sent as a pair with a line number to the medium heat processing unit. Based on the logical signal indicating activation, response, etc. corresponding to each line given from the central processing unit, the line signal of each line is converted. a microprocessor that controls sending, stopping, etc.; a line signal transmitter that outputs a line signal as a digital code under the control of the microprocessor;
a second interface circuit for interfacing the line signal transmitter with the microprocessor; and a first interface circuit for transmitting the line signal output from the line signal transmitter to a corresponding channel on the transmitting digital highway line.
a second inserter that inserts the line number and logic signal output from the microprocessor into a time slot for highway control information and sends it to the central processing unit; The present invention is characterized in that it includes a second dropper that extracts a logic signal indicating a line-compatible activation response, etc. supplied by the slot, and manually inputs it to the microprocessor.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention. On the digital highway line 100 on the receiving side, digital signals in which the voice signals of a plurality of lines, such as No. 1, No. 5, No. 5 signals, etc., are respectively PCM encoded are carried in time slots arranged in channels corresponding to each other.

The first drawer 200 distributes and outputs the signals of each time slot to the line signal receiver 201. The line signal receiver 201 checks the presence or absence of line 4N of each channel, and sends two types of line signals F, , F, and F to correspond to the line.
The presence or absence of is stored as a combination of binary signals. Hereinafter, this will be referred to as line signal information.

The first interface circuit 202 periodically accesses (scans) the line signal receiver 201 to detect a change point in the line signal information, and if there is a change, the line number and the 2-in signal information are updated every micrograph. Send to Nanatsusa 400. The microprocessor 400 analyzes the state of the line signal information and the information of each line stored in the access memory (RAM) 402, interprets the meaning of the received signal, and determines whether it is a start signal or not. After determining whether it is a signal or disconnection signal and checking its rationality, the above line signal information is activated.

It is converted into a logical signal indicating a response, etc., and the logical signal is sent out in combination with a line number. The logic signals and the like are sent to the inserter 203 via the inserter queue 204, and sent to the central processing unit (not shown) in the control information time slot of the highway 101.

To send line signals to each line, logic signals indicating the line number and activation response are sent from the central processing unit to Highway 103.
is sent to the control information time slot of the microprocessor 400 via the second dropper 303 and the hydrotube queue 304,
0 is the line signal transmitter 30 based on the above logic signal etc.
This is done by controlling 1 and sending a line signal to the specified line. That is, control information from the central processing unit is sent in the form of logic signals via the highway 103, and the second dropper 303 is connected to the highway 103.
The control information is extracted from the control information time slot, edited, and stored in the dropper queue 304 corresponding to the line. Dropper queue 3041d, microprocessor 40
The above information is sent in response to a read request from 0. The microprocessor 400 stores the information in a random access memo! The state of the line stored in 7402 is checked for rationality, and the control signal is converted into a control signal for sending or disconnecting a line signal, and sent to the second interface circuit 302. After performing predetermined timing processing, the second interface circuit 302 sends a line signal transmission or stop order to the line signal transmitter 301 .
1 sends the line signal as a PCM digital signal to the corresponding time slot of the transmitting way 102 via the first inserter 300, or stops the line signal being sent.

Programs required for the operation of the 71 microprocessor 400 described above are stored in a read-only memory 401. The random access memory 402 is still used as a working area for the microprocessor 400, and stores the transmission/reception sequence and current status of line signals corresponding to the line, and is used to analyze the line status and interpret and rationalize the meaning of input line signals. Used for gender checks, etc.

As described above, in the present invention, hardware detects changing points in receiving line signals that are transmitted, received, and The microprocessor is equipped with a microprocessor that controls the sending, stopping, etc. of signals, and the microprocessor converts the input line signal into a logic signal indicating a start-up response, etc., and notifies the central processing unit of the signal. Since the system is configured to control the sending, stopping, etc. of line signals in accordance with the logical control signals given, there is an effect that the load on the central processing unit can be significantly reduced.

[Brief explanation of the drawing]

The figure is a block diagram showing a simple embodiment of the present invention. In the figure, 100...receiving side digital/'t iway circuit M, 102... transmitting side digital highway line,
101, 103...highway, 200...first
dropper, 201... U-in signal receiver, 202
. . . first ink face circuit, 203 . . . second inserter, 204 .
. . . first inserter, 301 . . . line signal transmitter, 302 . . . second interface circuit, 303.
...Second dropper, 304...Dropper cue, 4
00...Microprocessor, 401...Read-only memory, 402...Random access memory. Agent Patent Attorney Toshimune Sumita

Claims (1)

[Claims] A first dropper that distributes and outputs the line signal of each channel of the digital highway line on the receiving side, and demodulates the output signal of the first dropper to detect two types of line signals and corresponds to the presence or absence of each line signal. a line signal receiver that stores the binary signal corresponding to the line; a first interface circuit that scans the line signal receiver to detect a change point in the line signal and supplies No. 24743 information to a microprocessor to be described later; Interprets the line signal information output from the interface circuit, converts it into a logical signal indicating activation, response, etc., pairs it with a line number, and sends it to the central processing unit.Activation and response corresponding to each line given from the central processing unit a microprocessor that controls sending, stopping, etc. of line signals of each line based on logic signals indicating the above, a 2-in signal transmitter that outputs line signals as digital codes under the control of the microprocessor, and a 2-in signal transmitter that outputs the line signals as digital codes; a second interface circuit that interfaces the transmitter with the microprocessor; and a first inserter that sends the in signal output from the line signal transmitter to a corresponding channel on the transmitting digital wireless line. and l1ir
A second inserter inserts the line number and logic signal output from the microprocessor into the control information slot of the highway and sends it to the central processing unit; N005 signal processing system, characterized in that it comprises a second dropper that extracts a logical signal indicating a line-compatible activation response, etc. supplied by the slot, and inputs it to the microprocessor.