JPS5921125A - Analog-digital converter - Google Patents

Analog-digital converter

Info

Publication number
JPS5921125A
JPS5921125A JP13063682A JP13063682A JPS5921125A JP S5921125 A JPS5921125 A JP S5921125A JP 13063682 A JP13063682 A JP 13063682A JP 13063682 A JP13063682 A JP 13063682A JP S5921125 A JPS5921125 A JP S5921125A
Authority
JP
Japan
Prior art keywords
voltage
converter
output
analog
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13063682A
Other languages
Japanese (ja)
Other versions
JPS6330815B2 (en
Inventor
Morikazu Itani
猪谷 盛一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kubota Corp
Original Assignee
Kubota Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kubota Corp filed Critical Kubota Corp
Priority to JP13063682A priority Critical patent/JPS5921125A/en
Publication of JPS5921125A publication Critical patent/JPS5921125A/en
Publication of JPS6330815B2 publication Critical patent/JPS6330815B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/18Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
    • H03M1/181Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To ensure a digital conversion with high resolution and a low cost, by providing a counter which counts the prescribed pulses with an over-range of an A/D converter and using the output of the counter to compensate the input of the A/D converter. CONSTITUTION:The voltage ES-E0 obtained by subtracting the compensating voltage from unknown input voltage ES to be converted by an analog subtractor 2 is applied to an unknown voltage input terminal of an A/D converter 1. When the voltage ES-E0 exceeds the full-scale voltage of the converter 1, an over-range output terminal 3 is inverted to an H level. Then a counter 6 counts pulses P, and the voltage E0 increases. The voltage ES-E0 is reduced due to an increment of voltage E0 and approximates to the full-scale input voltage. The increment of E0 continues until the terminal 3 is reset to an L level. When the terminal 3 is reset to the L level, a digital conversion output 10 of the converter 1 is turned into a lower digital output to the voltage ES. At the same time, a digital count output of the counter 6 is turned into an upper digital output to the ES. Thus it is possible to have an A/D conversion with higher resolution than a case where just a single unit of converter 1 is used.

Description

【発明の詳細な説明】 本発明はアナログ・ディジタル変換装置に関し、分H能
の小3いアナログ・ディジタル変換器に外部回路をイ」
加しC大きな分解能の変換器6Xiを構成することを1
目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter, and relates to an analog-to-digital converter that has a small H-divided power by installing an external circuit.
1 to configure a converter 6Xi with a large resolution.
purpose.

最近、マイクロウェーブオーブン、ムールエアコンテイ
ショナ等の家庭m化製品では、jlllj611+のた
めにマイクロコンビニーりが便用される傾向Iこある。
Recently, there has been a trend for household products such as microwave ovens and Mur air conditioners to use micro convenience stores.

この場合、アナログ人力(ja ljjはアナログ・デ
ィジタル変換器〔以ト、ADCと称す〕を介してテイジ
タル笈換しCから処j111される。しかし、高分解能
のA D Cは高価であるため、家庭m化製品では制御
精度を41゛a牲にして廉価な低分解能(通′帛、8ピ
ツ1へ)のAL)Cが用いられているのか3児状である
In this case, analog input (ja ljj) is processed from digital converter C via an analog-to-digital converter (hereinafter referred to as ADC). However, since high-resolution ADC is expensive, In home-use products, low-cost, low-resolution (generally 8 bits 1) AL) C is used at the expense of control accuracy of 41 mm.

本発明は、被変換未知人力市、圧から補正電圧を差引く
アナログ配算器と、このアナログ減算8:9の出力電圧
が未知[E肚入力端子)こ印加されtコA v cと、
このADCのオーバーレンジ期間に所定繰り返し周期の
パルスをd1数するカウンタと、このカウンタのディジ
タル劇数出力を・アナログ変換して耐I記補正sl圧と
するディジタル・アナログ笈換器とを設け・前記A D
 (:(D f (ゞ夕″変換111ノコをリロ記被変
換未知入力端子の下位側ディジタル変換出力とじ、Ip
’lJ記カウンタのディジタル変換出、トコを萌 □記
被艮換未知入力電圧のキ位側ディジタル変換出]、:I
 、a ’′j’る構成によつ゛C1廉価にして高分解
能のディジタル変換を行うものである。
The present invention includes an analog multiplier that subtracts a correction voltage from an unknown human power voltage to be converted, and an output voltage of this analog subtraction 8:9 applied to an unknown [E input terminal].
A counter that generates d1 pulses of a predetermined repetition period during the overrange period of this ADC, and a digital/analog switch that converts the digital output of this counter to analog and converts it into the rated I correction SL pressure are provided. Said A.D.
(:(D f
'lJ counter's digital conversion output, □key-side digital conversion output of the unknown input voltage to be changed], :I
, a''j'' enables low-cost, high-resolution digital conversion.

以下、本発明の一実施例を第1図と第2図に基づいて説
明する。
Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 and 2.

(+) fat低分解能のA I) Cで、未知電圧入
力端子には被変換未知入力電圧Esから補正電圧Eoを
アナログ減算器(2)で差引いた’(Es、−Eo)が
印加されている。なお、このA D C(+’)にはフ
ルスケールに達した時に状態が”′L″′→”t(”°
(こ反転するオーバーレンジ出力端子(3)が設りられ
ている。(4)はA D Cfl)のオーバーレンジル
」間にパルス発信器(5ンから出力されるパルスPを通
過させるアンドゲート、(6)はアンドゲート(4)出
力のパルスP′を81数するカウンタで、ここでは説明
の理解を容易にづ゛るため、先ず、このカウンタ(6)
はスタート信号(7)が″H″ルベルの期間に計数を実
行するものとして説明する。<9)はカウンタ(6)の
ゲイジタル計数出力(8)をアナログ変□ 換するディ
ジタル・アナログ変換器〔以下、DACト称す〕で、こ
のD A C<9)の変換出力が前記アナログ減算器(
2)の紙数入力に印加され’CQ(I記補正m圧Eoと
して作用する。
(+) fat low resolution AI) C, '(Es, -Eo), which is obtained by subtracting the correction voltage Eo from the unknown input voltage Es to be converted by the analog subtracter (2), is applied to the unknown voltage input terminal. There is. In addition, when this ADC(+') reaches full scale, the state changes from "'L"'→"t("°
(An overrange output terminal (3) that inverts this is provided. (4) is an AND gate that passes the pulse P output from the pulse oscillator (5) between the overrange signal of ADCfl). , (6) is a counter that counts 81 pulses P' output from the AND gate (4).In order to make the explanation easier to understand, we will first refer to this counter (6).
will be explained assuming that counting is executed while the start signal (7) is at the "H" level. <9) is a digital-to-analog converter (hereinafter referred to as DAC) that converts the gain output (8) of the counter (6) into analog, and the conversion output of this DAC <9) is the analog subtracter. (
2) is applied to the paper number input and acts as 'CQ (I correction m pressure Eo).

第2図は前記カウンタ(13)、、、の言1数が前述の
ようにスターl−伯号(7)がIt HI+レベルの期
間に実行されるとした説明上の要部波形図で、(a)は
(ES−EO)の、48号を示し、EFSはA D C
+11のフルスケール入力電圧を表わす。(Es−EO
)がA D C(1)のフルスケール入力電圧EFSを
越えると第2図(b)に示すよう〜こオーバーレンジ出
力、端子(3)が”l(nレベル1こ反転する。その後
、カウンタ(6)のスタート信号(7)が第2図(c)
のように″[(″し、ベルに反転すると、カウンタ(6
)がパルスP′の81数を実行してD A C(9)の
出力の前記抽圧電圧Eoが第2 ’w、h (d)のよ
う1こ増加する。
FIG. 2 is an illustrative waveform diagram of the main part, assuming that the counters (13), . (a) shows No. 48 of (ES-EO), EFS is ADC
+11 full-scale input voltage. (Es-EO
) exceeds the full-scale input voltage EFS of ADC (1), as shown in Figure 2 (b), the overrange output terminal (3) is inverted by 1 (n level). The start signal (7) of (6) is shown in Figure 2 (c).
``[('' and flip it to a bell, the counter (6
) executes 81 pulses P', and the extracted voltage Eo of the output of the DAC (9) increases by 1 as shown in the second 'w,h (d).

この補正電圧EOの増加によって(Es−Eo)は第2
図(a)の区間Wのように紙少してフルスケール入力電
圧Epsに近づく。補正電比Eoの増加(カウンタ(θ
)のカウントアツプ〕はA D CO,)のオーバーレ
ン・ジ出力端子(3)がL”レベルに復ヅωするまで継
続する。このようIこしてA D C(1)□σンオー
バーレンジ出□力MM 子(3)がH”レベルからL”
レベルに復帰すると、A、 D C(t)のディジタル
変換出力−がdtl記被変換未知人力逝圧ESIこ対す
る下・位ディジタル出力で、まtこ前記カウンタ(6)
のディジタル計数出□力(8)が前記被変換未知入力電
圧JEslこ対する上位ディジタル出力となり、ADC
(υ州外よりも高分解能のアナログ・テ゛イジタル変換
装置となる。
Due to this increase in correction voltage EO, (Es-Eo) becomes second
As shown in section W in Figure (a), the full-scale input voltage Eps approaches the full-scale input voltage Eps. Increase in the corrected electrical ratio Eo (counter (θ
) continues until the over range output terminal (3) of A D CO, ) returns to the L" level. In this way, the A D C (1) □σ in over range Output □ Output MM child (3) goes from H” level to L”
When the level is restored, the digital conversion outputs of A, D and C(t) are the lower digital outputs of the unknown human pressure ESI to be converted, and the counter (6)
The digital counting output (8) becomes the upper digital output for the unknown input voltage JEsl to be converted, and the ADC
(It will be an analog-to-digital converter with higher resolution than the one outside the state.

なお、カウンタ(6)のIllllラスタート信号)は
、□実際は、例えばADC(1)の変換周期(ヒ局期し
たリセット信号であって、A′DC(1)の変換開始に
際してその都度カウンタ(0)の内容を岑1こクリアす
るよう′に作用して、(Es−EO)>EFS  にな
ると力”j ”’> ”り(6)はカウントアツプして
(Es−Eo)は被変換未知入力電圧Esよりも小さく
なり、ADC(1)ではオーバーレンジ以内でディジタ
ル変換が実行さI’する。
Incidentally, the Illll raster start signal of the counter (6) is actually a reset signal at the conversion period (high phase) of the ADC (1), and the counter ( When (Es-EO)>EFS, the force ``j''> ``(6) counts up and (Es-Eo) becomes converted. It becomes smaller than the unknown input voltage Es, and ADC (1) performs digital conversion within the overrange.

以上説明のように本発明1こよると、低分解能のADC
のオーバーレンジによって所定繰り返し周期のパルスの
計数を実行するカウンタを設け、このカウンタの計数デ
ィジタル出力で前記A D Cへ   □のアナログ電
圧入力を補正すると共1こ、このADこのディジタル出
力を被変換未知入力電圧に対す   ′□る1ζ位ディ
ジタル出ノJとし、前記計数ディジタル1   ′出力
を被要換未知人力+1.圧に対ブる上位ディジタル出力
とフるため、BU8BA D CJ:蹟も高分解11i
5の変換装置を廉価な外部回路の増設で街らLるもの 
  、−である。                 
       ■:。
As explained above, according to the present invention 1, low resolution ADC
A counter is provided to count pulses of a predetermined repetition period due to the overrange of Let J be a digital output of 1ζ relative to the unknown input voltage, and convert the counting digital 1' output to the required unknown human power + 1. BU8BA D CJ: High resolution 11i
5 converter can be added to the town by adding an inexpensive external circuit.
, -.
■:.

【図面の簡単な説明】[Brief explanation of drawings]

Claims (1)

【特許請求の範囲】[Claims] 1、被変換未知人力Ya圧から補正電圧を差引くアナロ
グ減算器と、このアナログ減算器の出力電圧が未知電圧
入力端子に印加さねjこアナログ・ディジタル変換器と
、このアナログ・ディジタル変換器のオーバーレンジ期
間に所定繰り返し周期のパルスを旧敵するカウンタと、
このカウンタのディジタル変換出力をアナログ変換して
前記補正電圧とするディジタル・アナログ変換器とを設
()、nij記アナログ・ディジタル変換器のディジタ
ル変換出力を11(j記被及換未知人カフ1χ圧の下位
側ディジタル変換出力とし、目1記カウンタのディジタ
ル変換出力を1iI記被変換未知人力Yh圧の上位側デ
ィジタル変換出力としたアナログ・ディジタル変換装置
1. An analog subtracter that subtracts the correction voltage from the unknown human power pressure to be converted, an analog-to-digital converter that applies the output voltage of this analog subtracter to the unknown voltage input terminal, and this analog-to-digital converter. a counter that generates a pulse of a predetermined repetition period during an overrange period of
A digital-to-analog converter is installed to convert the digital conversion output of this counter into analog to obtain the correction voltage (), and the digital conversion output of the analog-to-digital converter is converted to 11 (j An analog-to-digital conversion device in which the digital conversion output of the counter (1) is used as the upper digital conversion output of the unknown human force Yh pressure to be converted (1iI).
JP13063682A 1982-07-26 1982-07-26 Analog-digital converter Granted JPS5921125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13063682A JPS5921125A (en) 1982-07-26 1982-07-26 Analog-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13063682A JPS5921125A (en) 1982-07-26 1982-07-26 Analog-digital converter

Publications (2)

Publication Number Publication Date
JPS5921125A true JPS5921125A (en) 1984-02-03
JPS6330815B2 JPS6330815B2 (en) 1988-06-21

Family

ID=15038985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13063682A Granted JPS5921125A (en) 1982-07-26 1982-07-26 Analog-digital converter

Country Status (1)

Country Link
JP (1) JPS5921125A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61149238U (en) * 1985-03-08 1986-09-13
JPH02216916A (en) * 1988-11-24 1990-08-29 Anarogu Debaisezu Kk Analog/digital converting circuit
US10351197B2 (en) 2016-09-26 2019-07-16 Kawasaki Jukogyo Kabushiki Kaisha Front cowling for saddle-riding type vehicle

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5440549A (en) * 1977-09-07 1979-03-30 Yasuda Denken Kk Ad converter rated range expanding system
JPS5465655U (en) * 1977-10-19 1979-05-10
JPS5597731A (en) * 1979-01-22 1980-07-25 Hitachi Ltd Analog-digital converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5440549A (en) * 1977-09-07 1979-03-30 Yasuda Denken Kk Ad converter rated range expanding system
JPS5465655U (en) * 1977-10-19 1979-05-10
JPS5597731A (en) * 1979-01-22 1980-07-25 Hitachi Ltd Analog-digital converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61149238U (en) * 1985-03-08 1986-09-13
JPH0326595Y2 (en) * 1985-03-08 1991-06-10
JPH02216916A (en) * 1988-11-24 1990-08-29 Anarogu Debaisezu Kk Analog/digital converting circuit
US10351197B2 (en) 2016-09-26 2019-07-16 Kawasaki Jukogyo Kabushiki Kaisha Front cowling for saddle-riding type vehicle

Also Published As

Publication number Publication date
JPS6330815B2 (en) 1988-06-21

Similar Documents

Publication Publication Date Title
US8350737B2 (en) Flash analog to digital converter with method and system for dynamic calibration
TW304316B (en)
EP0413271B1 (en) Electric power measuring system
JPS5921125A (en) Analog-digital converter
CN107733434B (en) Analog-to-digital converter and electronic device
WO1991003105A1 (en) Digital-to-analog converter
US6653958B1 (en) Method for compensating non-linearity of a sigma-delta analog-to-digital converter
JPS5912619A (en) Automatic correcting method of analog-digital converter
Kester et al. Fundamentals of sampled data systems
van Rijt et al. Learning control applied to a digital-to-analogue converter
US4289975A (en) Dissipating electrical charge
Eduri et al. On-line digital correction of the harmonic distortion in analog-to-digital converters
CN118740159A (en) Split dithering scheme in successive approximation analog-to-digital converter
Adsul et al. Design and Simulation of a New Reconfigurable Analog to Digital Converter based on Multisim
JPH0145254B2 (en)
JPS5952383B2 (en) RMS conversion circuit
JP2808260B2 (en) Analog-to-digital converter and thermal analyzer
SU750721A1 (en) Analogue-digital converter
SU1411978A1 (en) D-a converter
SU1695499A1 (en) Analog-to-digital converter
SU1430907A1 (en) Digital phase and frequency meter
JPS61127229A (en) Measuring device of settling time of digital-analog converter
SU1071969A1 (en) Resistance ratio to time interval converter
JPH02173576A (en) Digital watthour meter
JPS5910029A (en) Analog-digital convertion method