JPS59211141A - Interruption processing system - Google Patents

Abstract

PURPOSE:To ensure the quick service of an interruption of high priority by generating an artificial interruption factor to perform the 2nd processing action of a low level of emergency after executing the 1st processing action of a high level of emergency in case an interruption factor is generated. CONSTITUTION:When three interruptions having priorities A-C are processed. The interruption process A is executed based on the difference of emergency between interruption processes A and C. Then an interruption control circuit 8 supplies an artificial interruption command signal to a CPU1 in reply to an interruption generation request. The CPU1 executes the interruption process C. If the process B, for example, having an interruption factor of a higher level of emergency than the process C is generated before the artificial interruption factor, the higher priority is given to the process B.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interrupt processing method, and particularly to an interrupt processing method that performs a predetermined interrupt operation based on, for example, periodically occurring interrupt factors. .

Description of Prior Art Conventionally, there has been an interrupt processing method in which, when an interrupt factor occurs, all of a plurality of types of interrupt processing with different urgency are executed. Such an interrupt processing method has the following drawbacks because the interrupt processing time for one interrupt factor becomes long. In other words, even if another highly urgent interrupt factor occurs while an interrupt process is being executed, the execution of that interrupt process will take a long time until the currently executing interrupt process is completed. It turns out. Therefore, the priority order of interrupt processing may become unbalanced, causing problems in the system.

OBJECTS OF THE INVENTION Therefore, the main object of the present invention is to provide an interrupt processing method that can overcome the above-mentioned drawbacks.

Structure and Effects of the Invention To summarize, the present invention makes a predetermined interrupt processing operation, which has conventionally been performed based on the occurrence of one interrupt factor, relative to a first processing operation with high V4 acuteness. When an interrupt factor occurs, only the first processing operation is executed, and then a pseudo-vj interrupt factor is created to cause the second processing operation to be performed. occurrence, and the second processing operation is executed based on the pseudo v1-inclusive factor.

According to this invention, the interrupt processing operation for one interrupt factor is shortened, so even if another highly urgent interrupt factor occurs in the middle, the interrupt processing operation can be executed without waiting for a long time. can be done.

Therefore, other high-priority interrupts can be serviced quickly, and the efficiency of interrupt service on the system can be improved.

Hereinafter, the present invention will be described in more detail with reference to embodiments shown in the drawings.

DESCRIPTION OF EMBODIMENTS In the following, an example in which the present invention is applied to a dot printer will be described as an embodiment of the present invention, but it should be pointed out in advance that the present invention is applicable not only to dot printers but also to other devices.

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. In the figure, a ROM 2, a RAM 3, and a character generator 4 are connected to a CPU 1. , ROM
2 stores operating programs as shown in FIGS. 4 to 7, for example. Then, the CPU 1 operates according to this operation program. The RAM 3 has a storage area as shown in FIG. 2, for example. The character generator 4 stores display data for a plurality of types of characters.

CPLJl also has a display 5. A timer 6, a printer (dot printer) 7, and an interrupt control circuit 8 are connected. Timer 6 derives a display timer signal at a predetermined time. This display timer signal is given to the CPU 1 as an interrupt factor. Print data and a feed signal for feeding one line of a receipt or journal (not shown) are supplied from the CPLll to the printer 7. A dot timing signal is derived from the printer 7. This dot timing signal is given to CPLll as an interrupt factor. CPU
1 to the interrupt control circuit 8 is given an interrupt generation request signal. In response to this interrupt generation request signal, interrupt #I control circuit 8 derives a pseudo interrupt command signal and provides it to CPU 1.

FIG. 2 is an illustrative diagram showing the storage area of the RAM 3 shown in FIG. In the figure, area 31 includes a counter (DOTCNT) that indicates the dot position within the printing area of one character.
used as. As is well known, in a dot printer, one character is printed by breaking it down into a dot pattern of multiple columns and multiple rows. At that time, multiple dot bins are used to print one column at a time or one line at a time. The printing position at that time is stored in this area 31. Area 32 is used as an area (r) OTDATA) for storing data to be output to the printer 7 at each dot timing. That is, this area 32 stores one column or one row of data based on the dot pins. Area 33 is an area (DIS) for storing data corresponding to each digit of the display.
PDATA).

FIG. 3 is a time chart 1 for explaining the operation of an embodiment of the present invention.

4 to 7 are flowcharts for explaining the operation of the CPLll shown in FIG. 1. In particular, FIG. 4 shows the initial setting operation, and FIGS. The processing operations for interrupts A, B, and C are shown respectively.

The operation of one embodiment of the present invention will be described below with reference to FIGS. 3 to 7.

First, the initial m setting operation will be explained with reference to FIG. First, in step 1 (abbreviated as 6-S in the diagram), the cpui reads 1 rear 31 ([') of RAM 3.
OTCNT). Subsequently, in step 2, the data corresponding to [)OTCNT-0, that is, the pattern data in the first column (or first row) of the first character, is read out from the character generator 4 and stored in the area 32 (DOTDAT△). Then, in step 3, the pattern data of the first character to be printed is read from the character generator 4 and stored in the area 33 (D15PDATA).

Next, interrupt processing A, B, and C will be explained. Here, stiff interrupt processing A, BP) J, and C are
>It should be pointed out in advance that processing will be done with priority of C.

First, as shown in FIG. 3, CPLJl responds to the dot timing signal from the printer 7 and performs interrupt processing. This interrupt processing IJA is shown in the flowchart of FIG. That is, in step 11, the CPLll outputs one column or one row of pattern data of the characters stored in the area 32 to the printer 7. In the initial state, the pattern data of the first column or row of the first character is stored in the area 31, as explained with reference to FIG. Next, the process proceeds to step 12, where it is determined whether the numerical value stored in area 31 is 2 or not. That is, it is determined whether the column or row to be printed by the dot bin (not shown) of the printer 7 this time is the third column or row of the one-character dot pattern. If the numerical value in the area 31 is not 2, the process directly proceeds to step 14, but if the numerical value in the area 31 is 2, the process proceeds to step 13. In this step 13, an interrupt generation request signal is given to the interrupt control circuit 8. Then, proceed to step 14. In step 14, area 31 is incremented by +1. Subsequently, in step 15, it is determined whether or not the numerical value in area 31 is 10, that is, whether or not the print area for the next character has been entered. In step 15, if it is determined that the numerical value in the area 31 is not 10, the process proceeds to step 16, in which pattern data that rotates to the numerical value in the area 31 is read out from the character generator 4 and stored in the area 32. On the other hand,
If it is determined in step 15 that the 1 value of I rear 31 is 10, the process proceeds to step 17, where area 31 is cleared. As a result, the rear 31 again counts the dot positions of the next character from the first column or the first row. Subsequently, in step 18, pattern data corresponding to area 31 of the next character is read out from character generator 4 and stored in area 32.

After that, the operation ends.

Here, in response to the interrupt generation request signal derived in step 13 of FIG. 5, the interrupt control circuit 8 provides a pseudo interrupt command signal to CP (Jl). Then, CPLll performs interrupt processing C, and outputs a feed signal to the printer 7 in step 31 as shown in FIG. The interrupt processing 1!IC shown in FIG. 7 is performed, and the feed signal 9-1!IC is turned on as shown in FIG. 1 rather than what is done in printing.
It suffices if it is performed during the printing operation of any one character on the line. This is because receipt or journal feeding is done line by line.

Note that in the printer 7, a receipt and a journal are printed alternately by one print head. therefore,
What is fed in the interrupt process C in FIG. 7 is the one that is not currently being printed out of the receipt and the journal.

In the conventional interrupt processing method, the above-mentioned interrupt processing and interrupt processing C are performed together as one interrupt processing. However, in the above embodiment, the interrupt processing I
Focusing on the difference in urgency between JA and interrupt processing C,
A new interrupt factor is generated in a pseudo manner so that two interrupt processes are performed separately. As a result, if an interrupt factor that is more urgent than interrupt processing C occurs before a pseudo interrupt factor occurs, that interrupt processing is given priority.
〇-ru. For example, as shown in FIG. 3, if the display timer signal is derived from timer 6 before the pseudo interrupt command signal is derived, CPU 1 gives priority to interrupt processing B shown in FIG. 6 over interrupt processing C. Let's do it. That is, step 2 in FIG.
1, the pattern data of the character of the corresponding digit is read from the area 33 of the RAM 3, and the pattern data of the character of the corresponding digit is read out from the area 33 of the RAM 3, and
The display 5 displays the character of the corresponding digit in accordance with the C output.

Above) As per the book, v1 is more urgent than interrupt t8 logic C.
Interrupt processing B is interrupt 'I! It is executed earlier than 111IC. Therefore, the waiting time of the interrupt process B can be shortened, and the execution of the interrupt process B does not have to wait for a long time as in the conventional case.

In addition, in the above-mentioned embodiment, a case was explained in which two types of interrupt processing (A and C) with different urgency are divided and executed. FIG. 1 is a schematic block diagram showing one embodiment. FIG. 2 is an illustrative diagram showing the storage area of the RAM 3 shown in FIG. FIG. 3 is a time chart for explaining the operation of the actual journey example shown in FIG. 4 to 7 are flowcharts for explaining the operation of CPUI, in particular, FIG. 4 shows the initial setting operation, and FIG. 5, FIG. 6, and FIG. 7 respectively show the interrupt processing A, B and C are shown.

In the figure, 1 is CPU, 2 is ROM, 3 is RAM
s 6 is a timer, 8 is an interrupt control circuit, and 7 is a printer.

Patent applicant: Tateishi Electric Co., Ltd.

Claims (2)

[Claims] (1) An interrupt processing method in which a predetermined interrupt operation is performed based on interrupt factors that occur periodically. The predetermined interrupt operation is a first processing operation that is relatively urgent; and a second processing operation that is relatively less urgent, and when the urgent interrupt factor occurs, the first processing operation is executed, and then the second 12!1 processing operation is performed. An interrupt processing method characterized in that: a pseudo-interrupt factor is generated for the purpose of the interrupt processing, and the second processing operation is executed based on the pseudo-interrupt factor. (2) When another interrupt factor occurs before the pseudo interrupt factor occurs, the corresponding interrupt processing operation is performed based on the factor of the function, and the second interrupt processing operation is performed until the interrupt processing operation is completed.
2. The interrupt processing method according to claim 1, wherein the processing operation is kept on standby.