JPS59207664A - Method of producing semiconductor device - Google Patents
Method of producing semiconductor deviceInfo
- Publication number
- JPS59207664A JPS59207664A JP8606784A JP8606784A JPS59207664A JP S59207664 A JPS59207664 A JP S59207664A JP 8606784 A JP8606784 A JP 8606784A JP 8606784 A JP8606784 A JP 8606784A JP S59207664 A JPS59207664 A JP S59207664A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- metal
- manufacturing
- polysilicon element
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 28
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 229910021332 silicide Inorganic materials 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 4
- ZEVCJZRMCOYJSP-UHFFFAOYSA-N sodium;2-(dithiocarboxyamino)ethylcarbamodithioic acid Chemical compound [Na+].SC(=S)NCCNC(S)=S ZEVCJZRMCOYJSP-UHFFFAOYSA-N 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000272814 Anser sp. Species 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910021352 titanium disilicide Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は半導体装置及びその製造に関し、特にケイ化物
を用いた半導体加工に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices and their manufacture, and more particularly to semiconductor processing using silicides.
集積回路におけるゲート及び相Ｎ接続には従来ポリシリ
コン（多結晶シリコン）が用いられていた。しかし小形
高速集積回路ではケイ化物の如ぎ抵抗の低い他の材料を
用いるのが望ましい。ポリシリコンの抵抗率は高＜（１
０００μΩｃｍ）、２０μΩｃｍの抵抗率を有するニケ
イ化チタン等の幾つかのケイ化物のおよそ５０倍となる
ためボリシリコンの相互接続は微細回路では抵抗が非常
に大きい。Polysilicon (polycrystalline silicon) has traditionally been used for gate and phase N connections in integrated circuits. However, in small high speed integrated circuits it is desirable to use other materials with low resistance, such as silicides. The resistivity of polysilicon is high <(1
Polysilicon interconnects are very resistive in microcircuits, as the resistivity is approximately 50 times that of some silicides, such as titanium disilicide, which has a resistivity of 20 μΩcm) and 20 μΩcm.
かかる相互接続におりる電気信号の伝播遅延は、集中容
量と相互接続線の抵抗の積の関数である。The propagation delay of an electrical signal through such an interconnect is a function of the lumped capacitance multiplied by the resistance of the interconnect line.
記憶密度及び速度を増加させるよう装置用法を小ざくす
ると、この遅延は抵抗性部月のため顕著になるので新た
な材料を使用する必要がある。ケイ化物は、製造工程の
他の要素と完全に代替しうる材料よりなる。材料の導入
により既存の工程が大きく乱されないならば、新たな材
１１の利点は現在の技術で利用できる。As device usage is scaled down to increase storage density and speed, this delay becomes more pronounced due to resistive components and new materials must be used. Silicides consist of materials that can completely replace other elements of the manufacturing process. The advantages of the new material 11 can be exploited with current technology, provided that the introduction of the material does not significantly disrupt existing processes.
金属層（タングステン、モリブデン、チタン。Metal layers (tungsten, molybdenum, titanium.
タンタル等）を、従来のゲート及び相互接続の形成に用
いられるドーピングされたポリシリコンのシートで相互
拡散することでケイ化物を形成する方法は、従来からあ
る。この不均質な層は、装置のグー１−及び相互接続を
形成するＪ、うエツチングされる。しかしドーピングさ
れたポリシリコンに重なるケイ化物は、ポリシリコンと
は異なる速さでエツチングされるので、ゲートでは望ま
しくないアンダカッティングが生じる。Methods of forming silicides by interdiffusing tantalum (such as tantalum) with sheets of doped polysilicon used in conventional gate and interconnect formation are conventional. This inhomogeneous layer is etched to form the grooves and interconnections of the device. However, the silicide overlying the doped polysilicon etches at a different rate than the polysilicon, resulting in undesirable undercutting at the gate.
グー１〜及び拡散部分をケイ化する方法もあるが、これ
は工程が複雑である。There is also a method of silicifying Goo 1 and the diffusion portion, but this method requires a complicated process.
１番目の方法のアンダカッティングの問題及び２番目の
方法の複層１牲とににり既存の方法にケイ化物を適用す
ることは非常に困ガであった。Due to the undercutting problems of the first method and the multi-layered silicides of the second method, the application of silicides to existing methods has been very difficult.
本発明は、シリコン基板の酸化面にに少なくとも１つの
ポリシリコン素子を画成する段階と、少なくとも１つの
画成ポリシリコン素子に側壁を含めて金属被覆を設りる
段階と、金属ポリシリコンとを相方拡散させて少なくと
も１つの画成ポリシリコン素子に少なくとも１つの画成
ポリシリコン素子が配設されている上記酸化面に〒るま
で延在する金属ケイ化物層を形成する段階とからなる半
導体装置の製造方法を提供する。The present invention includes the steps of: defining at least one polysilicon element on an oxidized surface of a silicon substrate; providing a metallization on the at least one defined polysilicon element, including sidewalls; forming a metal silicide layer extending into the at least one defined polysilicon element to the oxidized surface on which the at least one defined polysilicon element is disposed. A method for manufacturing a device is provided.
第１ａ〜ＩＣ図に示した公知の方法は次の段階からなる
。シリコン基板１−トに、装置のソース。The known method shown in FIGS. 1a-IC consists of the following steps. The source of the device is placed on the silicon substrate.
ドレイン及びゲート部分が形成されるところで薄くなっ
ている酸化物層２が従来方法で設けられる。An oxide layer 2 is provided in a conventional manner, which is thinned where the drain and gate parts are to be formed.
ドーピングされた多結晶シリコン（ポリシリコン）３の
層が酸化物２上に設（プられる（第１ａ図）。A layer of doped polycrystalline silicon (polysilicon) 3 is provided on the oxide 2 (FIG. 1a).
例えばタングステン、モリブデン、チタン又はタンタル
の金属層４（第１ｂ図）がポリシリコン肋３上に成長さ
せられる。金属ケイ化物層（第１Ｃ図）が層３と４とを
相互拡散させることで形成される。次いで構成は装置の
ゲート６及び相互接続（図示せず）が形成されるようエ
ツチングされるが、ケイ化物５はドーピングされたポリ
シリコン３とは異なる速さでエツチングされるので７に
おける如きアンダカッティングが起こる。次いでソース
８及びトレイン９部分が画成され注入又は拡散される。A metal layer 4 (FIG. 1b), for example tungsten, molybdenum, titanium or tantalum, is grown on the polysilicon ribs 3. A metal silicide layer (FIG. 1C) is formed by interdiffusion of layers 3 and 4. The structure is then etched to form the device gate 6 and interconnects (not shown), but since the silicide 5 is etched at a different rate than the doped polysilicon 3, undercutting as at 7 is required. happens. Source 8 and train 9 portions are then defined and implanted or diffused.
続いて従来の酸化段階（中間酸化物）（図示せず）が行
なわれるが、ゲート６のケイ化物層での酸化は酸化■稈
へ送られる下層ポリシリコンからのシリコンの拡散によ
る。この方法を用いる商業用の加工法はポリサイド法と
よばれる。A conventional oxidation step (intermediate oxide) (not shown) follows, but the oxidation in the silicide layer of gate 6 is due to the diffusion of silicon from the underlying polysilicon which is fed into the oxidation culm. A commercial processing method using this method is called the polycide method.
ポリサイド法を採用すると、不均質な構成のエツチング
が困封になることを除けば従来のポリシリコン加工に比
べて変更する点は僅かである。When the polycide method is employed, there are few changes compared to conventional polysilicon processing, except that etching of non-uniform structures becomes difficult.
第２ａ〜２０図に示した伯の公知方法は１Ｊ−リサイド
法とＪ：ばれ、ゲート相互接続及び拡散部９双５一
方がケイ化される。この方法では、ポリシリコングー１
〜１０が基板１十の酸化物層２に従来方法により設りら
れる。ＣＶＤ（化学気相堆積法）により二酸化ケイ素の
層がグー１〜１０及び相互接続（図示せず）上に成長ざ
１！られる。この酸化物はゲート１０に隣接する酸化物
の側壁スペーサ１１を残すようにして異方的にエツチン
グされる。このエツチングにより、ソース及びドレイン
部分８゜９が従来方法にＪこり形成するのに用いられる
窓１２が開設され、接触部分及びポリシリコン１０」−
の酸化物は除去される。次いでチタン、タンタル等の金
属層が基板面−Ｆに設ｃＪられ、層の金属とシリコンと
が炉中で相互拡散して金属ケイ化物が形成される。シリ
コンが露出した領域でのみケイ化物が形成され金属が酸
化物上に成長した領域では変化はない。残った（反応し
なかった）金属は、特に拡散部のケイ化物１３．第２Ｃ
図［こ示す如きグー１〜相互接続部分及び図示しなかっ
た他の相互接続部分を残すようにエツチングされる。こ
の方法はり！Ｊ−ＩＪイド（ｓｅｌｆ−ａｌｉｇｎｅｄ
５ｉｌｉｃｉｄｅ自己整６−
合ケイ化物）どよばれ、ケイ化物が露出したシリコンに
自己整合η−る。続いて従来の酸化段階等が行なわれる
。酸化物側壁スペーサ１１のため処理が複雑となるが、
グー１〜からソース／ドレインへの短絡を防止Ｊるため
には不可欠である。The known method shown in FIGS. 2a-20 is known as the 1J-reciding method, in which the gate interconnects and the diffusions 9 and 5 are silicided. In this method, polysilicon glue 1
10 are applied to the oxide layer 2 of the substrate 10 in a conventional manner. A layer of silicon dioxide is grown by CVD (chemical vapor deposition) over the gooses 1-10 and interconnects (not shown). It will be done. The oxide is etched anisotropically leaving oxide sidewall spacers 11 adjacent gate 10. This etching opens windows 12 that are used to form the source and drain portions 8.9 in a conventional manner, contact areas and polysilicon 10''.
oxides are removed. A layer of metal, such as titanium or tantalum, is then applied to the substrate surface -F, and the metal of the layer and silicon interdiffuse in a furnace to form a metal silicide. Silicide forms only in areas where silicon is exposed; areas where metal is grown on the oxide remain unchanged. The remaining (unreacted) metal is especially the silicide 13. in the diffusion zone. 2nd C
Figure 1 is etched to leave interconnections as shown and other interconnections not shown. This method works! J-IJ ID (self-aligned)
The silicide is self-aligned to the exposed silicon. This is followed by conventional oxidation steps and the like. Although the processing is complicated due to the oxide sidewall spacer 11,
This is essential to prevent short circuits from the source/drain to the source/drain.
第３ａ〜３Ｃ図は本発明の〜実施例を示したものである
。第３ａ図はソース及びドレイン部分２１．２２が、選
択的拡散又は注入等の適当な方法で設（）られたシリコ
ン基板２０を示づ。酸化物層２３は基板２０の全表面上
に延在し、図示の如くソース、トレイン、ゲート部分で
は適当イｉ方法にＪ：り幼くされている。ドーピングさ
れた多結晶シリコン（ポリシリコン）を酸化物２３１−
に設け、エツチング１ノで、ソース及びドレイン部分２
１゜２２及び相ｎ接続（図示けず）と整合するポリシリ
コングー］〜２４を画成Ｊる。チタン、タングスデン、
タンタル、モリブデン等の金属層（第３ｂ図）をポリシ
リコングー１−２４．相互接続及び露出酸化物２３１−
に形成Ｊる。次のアニーリング工程中に、ポリシリコン
グー１へ２４及びポリシリコン相互接続上の金属はそれ
らと金属ケイ化物を形成づるよう相互拡散するが、金属
と直下の酸化物とは反応を起こさ！ｆい。残った（反応
しなかった）金属は、グー１〜２／Ｉ上及びその側壁近
くと相互接続１−及び近くの金属ケイ化物２６（第３Ｃ
図）が残るようにしてユーツチングされる。続いて、下
にあるポリシリコンをゲートにお４ｊる酸化のシリコン
源として用いる従来の中間酸化が行なわれる。Figures 3a-3c show embodiments of the invention. Figure 3a shows a silicon substrate 20 in which source and drain portions 21, 22 have been provided by any suitable method, such as selective diffusion or implantation. The oxide layer 23 extends over the entire surface of the substrate 20 and is thinned in a suitable manner at the source, train, and gate portions as shown. Doped polycrystalline silicon (polysilicon) with oxide 231-
The source and drain portions are etched 1 and the source and drain portions 2 are etched.
1° 22 and a polysilicon layer matching the phase n connections (not shown). titanium, tungsden,
A metal layer such as tantalum or molybdenum (Figure 3b) is coated with polysilicon glue 1-24. Interconnects and exposed oxide 231-
Formed in During the next annealing step, the metal on the polysilicon goo 1 and the polysilicon interconnect interdiffuses to form a metal silicide with them, but the metal and the underlying oxide do not react! F. The remaining (unreacted) metal is deposited on the goo 1-2/I and near its sidewalls and on the interconnect 1- and near the metal silicide 26 (3rd C).
(Fig.) remains. This is followed by a conventional intermediate oxidation using the underlying polysilicon as the silicon source for the gate 4j oxidation.
ポリシリコングー１へ２４及び相互接続を画成するのに
用いられるエツチング液は、拡散部分２１及び２２上の
酸化物２３を残すのに充分選択的でな（プればならず、
さもないとケイ化物はこれらの部分でグー１−がソース
／ドレインと短絡を起こすように形成されてしまう。The etchant used to define the etch 24 and interconnections to the polysilicon goo 1 must be sufficiently selective to leave the oxide 23 on the diffusion areas 21 and 22.
Otherwise, silicide will form in these areas such that the goo will short to the source/drain.
アニーリング方法と１）では、加工済シリコン基板の温
度を１０秒以内８００°Ｃまで上背させた後自然冷却さ
せる過渡（パルス）法が適当である。このアニーリング
は、窒素でパージされて酸素及び水分の濃度が２ ｒｐ
ｍ以下である室の中で行なわれる。かかるアニーリング
は、例えばアメリカ会衆（ηカリフォルニア州パロ ア
ルドのＡ、Ｇ、アソシエーツの「ビー１−パルス」の如
き商用ハロゲランプアニーリング装置を用いて行なえる
。For the annealing method 1), a transient (pulse) method is suitable in which the temperature of the processed silicon substrate is raised to 800° C. within 10 seconds and then allowed to cool naturally. This annealing is performed by purging with nitrogen to reduce the oxygen and moisture concentration to 2 rp.
It is carried out in a room with a size of less than m. Such annealing can be carried out using a commercial halogen lamp annealing device, such as the "Be 1-Pulse" manufactured by A.G. Associates of Palo Aldo, Calif., for example.
チタンの場合には、チタンは酸素と親和性が強いため通
常の炉によるアニーリングではクイ化物が形成される以
前に金属の酸化が起こってしまうから、チタンどポリシ
リコンの相Ｕ拡散にはかかるパルスアニーリング法が必
要とされる。通常の炉では不活性ガス（窒素）を使用し
ても、炉に装架する間にウェーハ間にどじこめられた空
気及び不活性ガスへの少量の酸素及び水分の混入により
顕著な酸化が起こる。In the case of titanium, since titanium has a strong affinity for oxygen, oxidation of the metal occurs before sulfide is formed during annealing in a normal furnace. An annealing method is required. Even if an inert gas (nitrogen) is used in a normal furnace, significant oxidation occurs due to the air trapped between the wafers while they are placed in the furnace and small amounts of oxygen and moisture mixed into the inert gas. .
本願ど同一の出願人にＪ：る英国特許出願第８２０３２
４２号（公開番号第２１１４８０９号）は、複数の交番
式″る層として成長させられ又は］スパッタリングされ
、パルスアニーリングされたチタン及びシリコンからケ
イ化物を形成することに関する。しかし本願は、画成ポ
リシリコン素子上の単一で分離した好ましくはチタンに
よる金属層を相互拡散することでケイ化物層を形成する
ことに関し、これ−〇−
は容易に既存の製造工程に絹み込むことができる。UK Patent Application No. 82032 filed by the same applicant as the present application
No. 42 (Publication No. 2,114,809) relates to forming silicides from titanium and silicon grown as multiple alternating layers or sputtered and pulse annealed. Regarding the formation of a silicide layer by interdiffusion of a single, separate metal layer, preferably titanium, on a silicon element, this can be easily integrated into existing manufacturing processes.
本発明の方法は、ポリサイド法に類似するが、グー［へ
及び相互接続が金属成長段階以前に画成されるためアン
ダカッティングが起こらないという点で異なる。本発明
の方法は従来のハｎ工法とともに実施することができ、
従来のポリシリコン加工の全体を顕著に乱さないまま低
い抵抗値の相互接続が得られ出来あがったケイ化物成分
の酸化可能性が保持される。The method of the present invention is similar to the polycide method, but differs in that undercutting does not occur because the goo and interconnects are defined before the metal growth step. The method of the present invention can be carried out together with the conventional Han construction method,
Low resistance interconnects are obtained without significantly disturbing the overall conventional polysilicon process, and the oxidizability of the resulting silicide components is preserved.
第１ａ図乃至第１Ｃ図は公知の半導体製造方法による連
続する段階の概略断面図、第２ａ図乃至第２Ｃ図は公知
の別の半導体製造方法による連続する段階の概略断面図
、第３ａ図乃至第３Ｃ図は本発明による半導体製造方法
の連続する段階の概略断面図である。
１．２０・・・シリコン基板、２．２３・・・酸化物層
、３・・・ポリシリコン層、４，２５・・・金属層、５
゜１３．２６・・・ケイ化物、６，１０．２４・・・ゲ
ート、７・・・アンダカッティング、８・・・ソース、
９・・・トレー１〇−
イン、１１・・・スペーサ、１２・・・窓、２１．２２
・・・ソース、ドレイン。
特許出願人 スタンダード デレフオンズアンド ケー
ブルス パブリック
１１−1a to 1C are schematic sectional views of successive steps according to a known semiconductor manufacturing method, FIGS. 2a to 2C are schematic sectional views of successive steps according to another known semiconductor manufacturing method, and FIGS. 3a to 3C are schematic sectional views of successive steps according to a known semiconductor manufacturing method. FIG. 3C is a schematic cross-sectional view of successive stages of a semiconductor manufacturing method according to the invention. 1.20... Silicon substrate, 2.23... Oxide layer, 3... Polysilicon layer, 4, 25... Metal layer, 5
゜13.26...silicide, 6,10.24...gate, 7...undercutting, 8...source,
9...Tray 1〇-in, 11...Spacer, 12...Window, 21.22
...source, drain. Patent Applicant Standard DereFons & Cables Public 11-
Claims (1)
ポリシリコン素子を画成する段階と、少なくとも１つの
画成ポリシリコン素子に側壁を含めて金属被覆を設ける
段階と、金属ポリシリコンとを相互拡散させて少なくと
も１つの画成ポリシリコン素子上に少なくとも１つの画
成ポリシリコン素子が配設されている該酸化面に至るま
で延在する金属ケイ化物層を形成する段階とからなる半
導体装置の製造方法。 ［Ｆ］ 少なくとも１つのポリシリコン素子はポリシリ
コンゲートからなることを特徴とする特許請求の範囲第
１項記載の製造方法。 （３）少なくとも１つのポリシリコン素子周囲のシリコ
ン基板の酸化面部分は金属被覆段階中に金属被覆を設け
られ、金属は相互拡散段階後に該部分から除去されるこ
とを特徴とする特許請求の範囲第１項記載の製造方法。 （７１） 基板にソース及びドレイン部を画成づる段
階は少なくとも１つのポリシリコン素子の画成に先行す
ることを特徴とする特許請求の範囲第１項記載の製造方
法。 ６）金属はヂタンであることを特徴とする特許請求の範
囲第１項記載の製造方法。 ６）相ｎ拡散は、不活１１雰囲気内でのパルスアニーリ
ングにより行なわれることを特徴とする特許請求の範囲
第５項記載の製造方法。Claims: (1) defining at least one polysilicon element on an oxidized surface of a silicon substrate; providing a metallization on the at least one defined polysilicon element, including sidewalls; interdiffusing with polysilicon to form a metal silicide layer extending over the at least one defined polysilicon element to the oxidized surface on which the at least one defined polysilicon element is disposed; A method for manufacturing a semiconductor device comprising: [F] The manufacturing method according to claim 1, wherein at least one polysilicon element is made of a polysilicon gate. (3) The oxidized surface portion of the silicon substrate surrounding the at least one polysilicon element is provided with a metallization during the metallization step, and the metal is removed from the portion after the interdiffusion step. The manufacturing method according to item 1. 71. The method of claim 1, wherein the step of defining source and drain regions in the substrate precedes defining at least one polysilicon element. 6) The manufacturing method according to claim 1, wherein the metal is dithane. 6) The manufacturing method according to claim 5, wherein the n-phase diffusion is performed by pulse annealing in an inert 11 atmosphere.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8312280 | 1983-05-05 | ||
| GB08312280A GB2139418A (en) | 1983-05-05 | 1983-05-05 | Semiconductor devices and conductors therefor |
| GB8328552 | 1983-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59207664A true JPS59207664A (en) | 1984-11-24 |
Family
ID=10542195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8606784A Pending JPS59207664A (en) | 1983-05-05 | 1984-04-27 | Method of producing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS59207664A (en) |
| GB (1) | GB2139418A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04242938A (en) * | 1991-01-08 | 1992-08-31 | Mitsubishi Electric Corp | Electrode wiring layer of semiconductor device and its manufacture |
| GB2320134A (en) * | 1996-12-04 | 1998-06-10 | United Microelectronics Corp | Salicide electrodes for semiconductor devices |
| CN1067804C (en) * | 1997-04-10 | 2001-06-27 | 联华电子股份有限公司 | Method for making self-aligning silicide |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2815605C3 (en) * | 1978-04-11 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | Semiconductor memory with control lines of high conductivity |
| NL8002609A (en) * | 1979-06-11 | 1980-12-15 | Gen Electric | COMPOSITE CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING THAT. |
| US4305200A (en) * | 1979-11-06 | 1981-12-15 | Hewlett-Packard Company | Method of forming self-registering source, drain, and gate contacts for FET transistor structures |
| JPS56134757A (en) * | 1980-03-26 | 1981-10-21 | Nec Corp | Complementary type mos semiconductor device and its manufacture |
| NL186352C (en) * | 1980-08-27 | 1990-11-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
| US4378628A (en) * | 1981-08-27 | 1983-04-05 | Bell Telephone Laboratories, Incorporated | Cobalt silicide metallization for semiconductor integrated circuits |
-
1983
- 1983-05-05 GB GB08312280A patent/GB2139418A/en not_active Withdrawn
-
1984
- 1984-04-27 JP JP8606784A patent/JPS59207664A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB8312280D0 (en) | 1983-06-08 |
| GB2139418A (en) | 1984-11-07 |
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