JPS59206882A - Image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image processing apparatus with improved display control means for image information.

2. Description of the Related Art In recent information processing, processing of image information is generally considered essential, and various image output devices have been developed. Typical input devices are COD (charge-coupled device) image sensors used in facsimile machines, etc. Output devices (recording devices) include thermal printers, inkjet printers, wire tod printers, and laser beam printers. There are printers and the like, and it is now possible to provide such excellent devices at relatively low prices.

However, compared to these image information input/output devices, display devices that display image information are technically behind in terms of resolution.

In other words, for image information processing, the resolution (linear density) of the image information handled is one of the most important characteristics from the point of view of providing high-quality information, so the resolution of the input/output device mentioned above should be of ordinary quality. There is a 7wg square), and for high-end products, If, /L
From 2 onwards/Otopel ones are also appearing. On the other hand,
Among currently available display devices, CRT (cathode ray tube) displays have the best resolution, but their resolution is still limited to 1I to 5 pels.

This means that the display device must display image information at twice the size of the input/output device t1, and in order to simultaneously display information on page l of the input/output device on the display screen. However, there is a problem in that it requires a display area approximately twice as large as that of the input/output device, making the device practically unrealizable. Therefore, in conventional display devices of this type,
Generally, one page's worth of image information is edited into several parts and displayed several times, making it difficult to grasp the layout of the entire image information.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, select a part of the storage area of a storage means in which image information is stored in units of a predetermined size, and directly display detailed image information on a display means. and a layout display function that thins out the image information of the entire area of the above-mentioned predetermined size of the storage means and displays it on the display screen of the display means at once,
The object of the present invention is to provide an image processing device that can selectively switch and use either of the above-mentioned functions in response to an external control instruction.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a schematic configuration example of the image processing apparatus of the present invention, where / is an image reader (image input means) for inputting image information (image information), and / is an image reader (RD).
Image memory (image storage means) that stores the value-coded image information output from i in units of, for example, 7 pages; 3 is an image memory (BUF) that outputs the image information stored in the image memory onto a recording medium; A printer (PR'I', image output means), a CPU (microprocessor) that performs overall control of image processing and editing of image information;
5 CRT display (image display means), 6 is CR
T display control circuit (image display control means)
, a CRT display (CRT) 5 displays image information stored in an image memory on a display screen under the control of a CRT display control circuit (0RTO) A.

Furthermore, 7 is a control panel (display switching instruction means) for inputting instructions from the operator (operator), and the control panel (KEY)
The instruction input from 7 is decoded by CPU q-.

In order to simplify the explanation below, the resolution of the CRT display j is 1/1/1/2 of the resolution of the input/output devices l and 3 both vertically and horizontally! For example, it is assumed that the resolution of the CRT display 5 is Dapel, and the resolution of the input/output device/and 3 is Gpel.

Figure 2 shows the image memory storage area and CRT in Figure 1.
An example of the relationship with the display area of the display S is shown, where ioθ is the maximum frame of the reader 1, printer 3, and image printer, and X is the maximum frame/the number of bits in the main scanning direction (horizontal direction) of θθ (number of scanning lines), Y is its maximum frame 1
00 indicates the number of bits (number of scanning lines) in the sub-scanning direction (vertical direction). 10/ is a display frame indicating the display target range of image information to be displayed on the CRT display 5, and as shown by diagonal lines, the display capacity (”/2.Y/2 ).

By operating the panning display function described below in the CRT display control circuit B through the 0PUII in response to a panning display instruction given by the operator via the keys or joystick (not shown) on the operation panel 7,
The above-mentioned display display frame 10/ is moved to a desired position within the maximum frame 100 on the image memory as shown by the broken line frame 102 in the figure, and the detailed image information in the range surrounded by the display display frame is directly displayed on the CRT display. Display on S.

Furthermore, in response to layout display instructions given by the operator via the keys on the operation panel 7,
is reduced to 1/2 bit length by thinning out the odd or even bits of Y in the vertical direction and X in the horizontal direction using the upper left corner as the point, and then the maximum frame 100 is made to have the same area as the display display frame 101. , displays the layout of the entire page of the image memory on the CRT display S.

FIG. 3 shows an example of the configuration of the CRT display control circuit B in FIG. 1, where 10 is the image memory (6). It is a latch circuit (end pointer) that indicates the end point).
Set the start point or end point in the X-axis direction of the target storage area to be displayed on the ORT display 5 to (3
Supplied and stored from PU II. /- is a scanning address counter to which a start point is supplied from the latch circuit 10 as an initial value, and addresses the image memory 2 by counting up by "/" in response to the counter clock signal OK. /3 is a comparator, which constantly compares the value of the latch circuit /l and the value of the counter saw, and when the two values match, it gives a load pass (comparison match signal) LP to the counter /2. , thereby transferring the value of the latch circuit 10 to the counter saw and initializing it.

/Hiro is a latch circuit (start pointer) that indicates the scanning start address (start point) in the Y-axis direction (sub-scanning direction, vertical axis direction) on the image memory card,
l! Similarly, r is a latch circuit (end pointer) that indicates the scanning end address (end point) in the Y-axis direction. 'Storage sourced from. 16
sb is a scanning address counter to which a start point is supplied from the latch circuit /lI as an initial value, and counts up in response to the counter clock signal OK to address the image memory. /7 is a comparator, which constantly compares the value of the latch circuit 1S and the value of the counter 16, and when the values match, it applies the load bus LP' to the counter /6, which then outputs the load bus LP' to the latch circuit /6. The value of DA is transferred to the counter 16 and initialized. Therefore, 0PU
The storage area to be displayed specified through ll is repeatedly scanned and displayed on the CRT display j.

7g and /q are shift registers that convert the parallel output bit information read from the image memory processor through multiple bit lines into serial output bit information and send it out. The bit lines are connected, and even-numbered bit lines are connected to the latter shift register /q, and shift clocks having a phase shift of 1 gθ0 are applied to both /g and /9. 20 is an AND circuit into which the gate signal G and the serial output bit information of the shift register /g are input; 2/ is an OR circuit into which the output signal of the AND circuit and the serial output bit information of the shift register /q are input; The output of / is sent to a CRT display S.

22 is an AND circuit into which the clock signal OLK/ for panning display and the gate signal G are input, and 3 is the inverted output G of clock signal OLK 2 and gate signal G for layout display.
The AND circuit 52 into which is input is an OR circuit into which the output signals of both AND circuits n and 23 are input, and this OR circuit! The output of 9 is supplied to the scanning address counter /2 in the X-axis direction as a counter clock signal OK.

J is an AND circuit to which the inverted output G of the gate signal G and the load path LP from the comparator/3 are input (9), and M is the input circuit to which the gate signal G and the load bus LP' from the comparator/7 are input. AND circuit 1.27
is a 10/circuit that adds the output of AND circuit 3 by “/”,
I is an OR circuit into which the output of the +7 circuit and AND circuit 2B is input, and the output of the OR circuit 2g is sent to the scanning address counter /6.

Furthermore, 2? is an inverter circuit that inverts the gate signal G, and the inverted signal d inverted by the inverter circuit 9 is supplied to the AND circuit 9 and 9, as described above. 30
is a flip-flop circuit (FF), and the output (gate signal) G is set to “7” or “θ” according to instructions from cpup.
At this time, the gate signal G is held at l'' when panning is displayed, and the gate signal G is held at l'' when displaying layout.
is held at 11 o ++.

Next, the operation of the apparatus shown in FIG. 3 will be explained.

First, to explain the pan display function, the operator (
When there is an instruction for pan display (arbitrary switching display of partial display) from the user, the display area instruction data from the operator is sent to the CPU Hiro (10) - A specific address point P(x/ +V
/) rQ (X col Y/ ) + R(xt ry
), and S (x2, y2), and set X/ to the X-axis start point lθ and
/ to X2, Y-axis start point /4' to yl,
Set 'J2' to the Y-axis end pointer /3, and set the flip-flop 30 to 'l' indicating pan display.

Then, the output signal G from the flip-flop 30 becomes
``'', the AND gate circuit 2 opens and the address counter/coherent clock signal OLK/ is applied through the AND circuit 22. As a result, the address counter saw and the comparator 13 start operating, and the scanning address When reaches the end point (xu) of the X axis, the values of address counter /2 and comparator /3 match, so a comparison match signal LP is sent from comparator /3 and address counter l returns to the initial value ( At the same time, the comparison match signal LP is supplied to the Y-axis address counter H through the AND circuit 26 and the OR circuit 2g, and the address counter tacho is counted up by +1.

In this way, by addressing using counter/2 and counter 16, the image information (binary image information) stored in the image memory is sequentially read out from the specified scanning start address point P (xi, yl) and shifted. Registers /g and 19 are sent. At this time, since the AND circuit 2o on the output side is open, there are two shift registers /II and /? The output is sent bit by bit to the CRT display S alternately.

The image is displayed.

In this way, the Q
Display pointer information x/, x2 by PTJ ll
.

yl and y2 as latch circuit 10, //, /+
If you reset the display frame to
i (see tgλ diagram) can be moved to any desired position in the image memory, so the image information in any storage area surrounded by the display frame 10/ can be displayed in detail on the CRT display S as it is. be able to.

Next, to explain the layout display function, when an operator instructs you to display a layout, first
U II sets the origin to the X-axis start point lθ.
oo”, the maximum value of X to the end point l/ of the X axis,
Set the origin “Oθ” to the Y-axis start point/lI, and
Axis end pointer! Set f to the maximum value Y, and set flip 70 knob 30 to "O" indicating layout display.

Then, the output signal G from the 7-lip flop 30 becomes O”
Therefore, AND circuits n, 26 and I close their gates, but since the inverter circuit 9 inverts the signal to "/", AND circuits n and J open. Therefore, the clock signal OL passes through the AND circuit n to the address counter 12.
Kλ is applied, and the address counter saw and comparator 13 start operating. Here, the clock signal OLK2 has a frequency that is times the frequency of the clock signal OLK/ used in the panning display described above.

When the address counter /λ and the value of the comparator 13 match, the comparator 13 sends out a comparison match signal LP as in the case of the panning display described above, but since the AND circuit 23 is open, the comparison match signal LP is sent out. The LP passes through the AND circuit and is added to the tenth circuit by "/" (/3) and sent to the Y-axis address counter/B, thereby causing the counter 16 to increment by a +cocount.

On the other hand, since the AND circuit is closed on the output side, only the output of the shift register 19 passes through the OR circuit -/ to the CRT.
The image is sent to the display 5 and displayed as an image.

As a result, the image information stored in the image memo IJ 2 is read out sequentially from the address point P (o, o).
The OR'I' display 5 displays only even numbered bits in the X-axis direction and only odd-numbered rasters in the Y-axis direction, resulting in an image that reduces the entire maximum frame 100 (see Figure 1) of the 5 image memory to 1/4. The following display is obtained.

Effects As explained above, according to the present invention, by selectively specifying the panning display function and the layout display function, it is possible to display detailed partial image information or display the entire page image at will. Therefore, even if a display device such as a CRT display with a low resolution, that is, a coarse linear density is used, it is possible to provide an image processing device that can sufficiently withstand the display demands of users in actual use.

(tq) Of course, the display device is not limited to the above-mentioned CRT display, but various displays such as liquid crystal, light emitting diode, laser vino, etc. can be used. As an image input device, in addition to a document image reading device, a document input device using a keyboard, a light pen, a Bentouch board, etc. can also be applied.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a schematic configuration of the image processing apparatus of the present invention, FIG. 2 is an explanatory diagram showing an example of the relationship between the maximum frame of the image memory in FIG. 1 and the display display frame of the CRT display, FIG. 3 is a circuit diagram showing an example of the configuration of the CRT display control circuit shown in FIG. 7. /...Image reader, core image memory 1,? -Image printer, q...CPU, 5-CRT display, 6-CRT display control circuit, 7...-operation panel, 100...maximum frame, 10/, 10.2-display display frame, 10,
// , /ri, 15... latch circuit, /2. /Otsu・
Address counter, /3, /'/... Comparator, 7g, /? Shift register, 20, Engineering: 13, B, , 2A AND circuit, U/, , 2/7-, M... OR circuit, -7
...10/circuit, B...inverter circuit, 30...flip-flop.

Claims (1)

[Claims] storage means for storing image information in units of a predetermined size;
In an image processing apparatus, the image processing apparatus has a display means whose display capacity is smaller than the unit, and a partial display means reads out a designated area of the storage means as it is and displays it on the display means in response to a 5-part display instruction, and a partial display means reads out the designated area of the storage means as it is and displays it on the display means in response to a whole display instruction. an entire display means for reading out the entire area of the storage area of the predetermined size of the storage means by thinning processing and displaying it on the display means.