JPS59206786A - Radio direction finder - Google Patents

Abstract

PURPOSE:To improve S/N and to obtain a stable azimuth by processing an azimuth signal component digitally, overlapping the signal component in a memory and reading out past data stored in the memory instead of input data at the time of instantaneous interruption or the like. CONSTITUTION:Non-directional antennas A1-An are arranged on a circumference at an equal interval and successively switched and scanned and a product of a radio wave arriving direction, i.e. a bearing signal, detected by the phase change of a receiving signal and an internal signal obtained by an internal signal generating circuit is outputted and stored successively in memory groups 410, 411 consisted of a memory corresponding to individual antenna. The stored values are multiplied by an adder 412 during a period of the integer times of a scanning period to control the phase of the internal signal. The product outputs are accumulated in the memory group 410 by a prescribed period and then transferred to the memory group 411 to control the phase of the internal signal, and when input of the memory group 410 is incorrect because of the instantaneous interruption of received radio wave or the like, the values of the memory group 411 are processed and inputted to the memory group 410.

Description

[Detailed description of the invention] From the phase change of the received signal obtained by arranging omnidirectional antennas at equal intervals on the circumference and switching them sequentially,
In a so-called stationary Doppler direction finder that determines the direction of arrival of received radio waves, a wave detector such as a TASCRE or PLL is used.
The phase shift component is extracted using a phase synchronization circuit (phase synchronization circuit), and the phase difference with the antenna travel reference signal is measured to determine the direction of the incoming radio wave.
M: Contains sound and has an extremely poor S/N ratio, so the above-mentioned phase difference measurement cannot be directly performed.

For this reason, the effective component in the azimuth component is extracted using a P-wave device or a separately provided phase stabilization circuit, but since this azimuth signal component has a low frequency, the response speed becomes extremely slow. Furthermore, if there is a momentary interruption or interference in the azimuth signal component, the transient phenomenon continues for a long time and the azimuth cannot be determined.

Since the direction signal component undergoes a certain delay while passing through the receiver, it is also necessary to correct the value corresponding to the phase difference measurement diameter delay between the extracted direction signal component and the antenna scanning reference signal. Keeping the value stable was also one of the difficulties.

The present invention digitally processes the azimuth signal component and superimposes it on the memory to improve the S/N ratio, and also to store past cheaters in the memory in case of instantaneous interruptions, etc. By reading this out and using it as a human catheter, a stable direction is given, and the above-mentioned yellow 11 points are eliminated, providing an excellent wireless direction measurement.

FIG. 1 is a system diagram showing an embodiment of the present invention, FIG. 2 is a system diagram showing details of a signal processing circuit, and FIG. 3 is a system diagram showing details of a signal processing circuit.

4 and 5 are detailed explanatory diagrams of each block, FIG. 6 is a waveform diagram showing the operation of the valley, and FIG. 7 is a waveform diagram showing the operation of the delay frequency division lDJ path.

1 is an antenna group, and as shown in FIG. 3, an antenna A having the same characteristics is located at the center of omnidirectional antennas A1 to An having the same characteristics arranged at equal intervals on the circumference. and send its output to receiver 3
Connect to the 10RF input terminal. 2 is an antenna switcher which sequentially switches and scans the outputs of the antennas A1 to An and connects the output to the RF input terminal of the receiver 32. 3 is composed of a main receiver 31 and a slave receiver 32 with a common local oscillator.
By adjusting the frequency of the main receiver 31 with the channel receiver, the frequency of the slave receiver 320 can also be adjusted at the same time, so that the same radio waves can be received at the same time. Note that when receiving radio waves by sequentially switching and scanning A+ to An antennas, the received signal will not undergo phase modulation due to the antenna arrangement as shown in Figure 6(a) (example of 8 antennas). 56-35828 is also already known.

The signals are amplified by the two-channel receiver 3 and then applied to the IF high-output signal processing circuit 4 where they are amplified and detected to obtain a predetermined azimuth signal. The signal processing circuit 4 separately generates a reference signal and applies this to the antenna switching signal generating circuit 6 to generate switching scanning signals for each antenna. The above-mentioned azimuth signal is subjected to average processing in an addition circuit within the signal processing circuit. This output is applied to the indicator 5 to display a 3-digit or 4-digit digital azimuth measurement value on the numerical display, and at the same time, it is displayed on the cathode ray tube as a single image or a single external line image indicating the azimuth.

FIG. 2 shows details of the signal processing circuit 4. 4
] Jll: An FM component removal circuit having a configuration as shown in FIG. Frequency converter 4
After being frequency-converted by 1a and 41b, the signals are further mixed by a separately provided frequency converter 41e and converted into one beat signal. By passing the received radio wave through the FM component removal circuit in this manner, it is possible to remove the frequency modulation component imparted to the received radio wave.

Therefore, even with radio waves such as FM (FS) and SSB, disturbances to the direction signal can be removed, making stable direction measurement possible.

It goes without saying that even if the received signal is not normally modulated with frequency changes, the phase change component caused by antenna switching can be extracted through the circuit described above. The output of the FM component removal circuit is detected by a detection circuit 43 composed of a PLL, a repeater, an integrator, etc., and the voltage changes rapidly at the phase change point as shown in FIG. 6(b).
A signal such as shown in FIG. 6(a) is obtained, and by integrating this signal, a signal shown in FIG. 6(c), which is similar to that in FIG. 6(a) due to the phase improvement caused by the switching of the antenna, is obtained. This azimuth signal has a double-wave rectified waveform as shown in FIG.

The signal 42 is added to the input through the IF high output FM component removal circuit obtained by amplifying the Ao antenna output output using the signal detection circuit. This IF large input amplitude and center frequency are detected, ANDed and applied to the detection circuit 43 and memory control circuit 413, and the detection circuit avoids unnecessary confusion in the PLL at the moment of momentary interruption of radio waves. Therefore, the operation of the PLL is temporarily stopped, and the memory control circuit uses the human power applied to the first memory circuit to switch from the output of the ADC 45 to the output of the second memory circuit. As shown in FIG. 5, the product circuit 44 is composed of a subtracter 4.4a and an SlNROM 44b.

SINROM44b ID: It has input/output of multiple bits and one period or half period of SIN wave is stored in memory, and when the output of the internal signal generation frequency dividing circuit 47 is input, the 6121 (e) A multi-bit digital value that changes as follows is recorded. The waveform diagram of this signal is SlNR
Although it changes in a stepwise SIN shape whose size is determined by the number of input/output bits of the OM, the average phase is depicted for simplicity. The -81 calculator 44a gives the product of two inputs, the analog signal of the detected output rectified waveform in FIG. 6(d) and the output of the S IN ROM in FIG. 4(e).
) with the digital signal and the phase of both signals is exactly 9.
O3lNROM with 0° difference, product output of the waveform in figure (d) and figure X in figure (e), output as shown in figure 6 (f).
The product circuit output changes as shown in the waveform diagrams (g) and (h) when the output is as shown in (e) Figure Y and (e) Figure Z.

In the embodiment of the present invention, the above-mentioned -III calculator gives exactly the same result regardless of whether one input is an analog input or a digital input, and whether both inputs are analog or digital. The output of the subtraction circuit 44 is A of the next stage.
Figure 6 (f) is added to the DC (analog digital converter).
) is input to the next first memory circuit 410 as a parallel multi-bit digital value.

The frequency dividing circuit 47 for internal signal generation mentioned above is composed of a counter and a presettable counter having input/output of multiple bits 9, and the signal inputted inversely from the reference signal oscillator 48 is frequency-divided by color/2. Then, it becomes the input of the presettable counter, and the maximum bit is divided by a predetermined frequency so that the frequency completely matches the 1f period of the detection output in Figure 6 (C).At the same time, the number required for the preset input is By precenting E, it is possible to advance or delay the phase of each output, and as a result, the above-mentioned SIN ROM 4
Is the double-wave rectified output of 4b advanced or delayed in phase in Fig. 6(e) so that the product circuit output has the waveform in Fig. 6(f)? tii
l (I'm going to allf.

The reference signal oscillator is a crystal or self-excited clock and base signal generation oscillator, and its output is an internal signal generation frequency divider circuit 47.
and becomes an input to the delay frequency divider circuit 46.

The delay frequency divider circuit 46 is a frequency divider circuit that generates an antenna scanning reference signal composed of an up-down counter.The delay frequency divider circuit 46 is a frequency divider circuit that generates an antenna scanning reference signal, and is configured by adding an output corrected for the delay time that occurs while the received signal passes through the receiver to the antenna switching signal generation circuit 6. This is to give correct directions. 49 is a delay time setting device, which is composed of a digital switch, and the digital output is connected to the delay frequency divider circuit 4-
If the preset L7 and amplifier count are applied in addition to the manual preset of the up/down counter 6, the phase of the preset value and the output of the delay frequency divider circuit will advance. In other words, the up/down counter with multi-bit output is powered by the clock! As shown in 111 m 71 kl, the content of the color/re changes from 0 to full count, and this is repeated sequentially.

Therefore, if the value P is preheated to the counter at the time point R as described in Ai+, the output level will change to ~ as shown by the dotted line in Figure 7, so the waveform of the solid line before presetting is The phase will advance by

In this way, the delay occurring in the receiver is automatically corrected, and the receiver output Q can correctly indicate the direction of the radio wave relative to the reference signal.

410 is the first memory circuit, 411 is the second memory circuit, and A
l) The output of C (analog-digital converter) 45 is the first
stored in the memory circuit.

When inputting to the first memory circuit, a memory area is provided for the output of each antenna, and IiU is inputted and stored a predetermined number of times m. . . . When the m-times of accumulation is completed, the output of the first memory circuit is transferred to the second memory circuit, and at the same time, the contents of the first memory circuit are cleared, and the accumulation as described in "Si" is repeated.

Reference numeral 413 is a control circuit which changes the input to the first memory circuit to A when the input signal reaches pt-1' according to the output of the signal detection circuit.
It handles various controls such as switching from DC (analog-to-digital converter circuit) output to second memory output, data transfer between memories, addition commands, etc.

If there is a 90° phase difference between the output of the total detection circuit 43 in Fig. 6(d) and the SlNROM output in Fig. 6(e), or the curve X in the figure, the output of the product circuit will be as shown in Fig. 6(f). )become that way. For the sake of explanation, the second memory circuit is omitted and the first
The total sum of one cycle (or m cycles) of the memory circuit is shown in Figure 6 (f
), the output of the adder circuit 412 becomes 0 because (=) cancels out and becomes 0. FIG. 6(d) and (
e) or deviates from the 90° phase difference (for example, in the case of (e) figure Y or Z), the output of the 411 calculator will be as shown in figure 6 (g) or (1).
1), so the output of the adder circuit 49 deviates from 0 (
+) or (-).

Like this K+! The average level of the output of the circuit changes from 0 to 0 or 0 depending on the phase relationship between the two inputs (Fig. 6 (d) and (e)). If the presettable counter of the frequency divider circuit 47 is preset, the phase of the output of the frequency divider circuit 47 for internal i-signal generation will be the same as the content of the adder circuit output.
Until the phase difference between the two input signals of the product circuit becomes 900±, the content of the applied force -1 street increases or decreases to control the phase of the SlNROM output signal, and an equilibrium point is reached.

Therefore, the measurement deviation of the output of the addition circuit 412 (there is a 90° phase difference with the detection output, but it is corrected internally) from the reference point allows us to know the arrival direction of the radio wave, so this can be detected by the indicator 5.
In addition, the measured direction can be displayed.

In actuality, the PLL of the detector may become unlocked due to noise or momentary interruption of radio waves in the pig receiving the signal, and a normal detection output may not be obtained1.For this reason, the contents of the adder circuit 412 are This causes unnecessary fluctuations and confusion in the control and instruction systems.
Fluctuations in orientation often occur.

In this case, a second memory circuit is provided, and after accumulating the azimuth takes in the second memory circuit for a predetermined period m, these are transferred to the corresponding second memory circuits, and the sum is added to the adder circuit 412 as described above. When the detection output is cut off, the input of the first memory circuit is immediately changed to the second memory circuit output corresponding to the ADC output. It is switched to . However, since the value of the output of the second memory circuit is calculated by the fixed period D, it is necessary to divide it by the fixed period m before inputting it to the first memory circuit.

Averaging is performed by these operations, and even if the @ wave output fluctuates considerably each time due to noise interference, etc., the average value is input to the first memory circuit, so that the sum of the second memory circuit is also stabilized.

Note that the output of the internal signal generation circuit and the output of the adder circuit are 90° since the detection output No. 6 and 1(d) is always 90° phase difference when type 1 is completed. By adding the output, for example a 3-digit numerical value, to the indicator 5, it is possible to indicate the stable direction of arrival of small waves.

Also, delay time correction is normally done using a one-shot multi, shift register, etc. However, when using a one-shot multi, the delay time varies due to the influence of the temperature characteristics of the time constant, and when using a shift register, However, in order to finely adjust the delay interval, a very large number of them are required. Since the one-hour delay correction circuit according to the present invention is of a completely digital type, the delay time can be kept stable. Receiver I
By switching the output of the delay time setter in conjunction with switching the F'bandwidth, there is no need to correct the direction due to delay at the receiver end, and the tracking operation is greatly simplified. 1SI-1 adjustment can also be made unnecessary.

In addition, each circuit within the dotted line in Figure 2 for controlling the memory control and averaging processing described above can be easily realized using a micro combinator, so everything after the detection of the force potential signal is processed digitally. Therefore, it is possible to realize a wireless direction finder that operates stably and reliably and is very easy to manufacture and set up.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing one embodiment of the present invention, and Fig. 2 is a system diagram showing an embodiment of the present invention.
Figure 3 is a detailed system diagram of the signal processing circuit 4, Figure 3 is an example of the arrangement of antenna groups, Figure 4 is a detailed system diagram of the FM component removal circuit 41,
FIG. 5 is a detailed system diagram of the product circuit 44, FIG. 6 is an hourglass diagram showing the operation of each part, and FIG. 7 is a waveform diagram showing the operation of the delay frequency divider circuit 46. 1. Antenna group, 2. Antenna switch, 3. Receiver, 4. Signal processing circuit, 5. Direction indicator, 6.
- Antenna switching signal generation circuit, 41... FM component removal circuit, 42... Signal detection circuit, 43... Detection circuit, 44
-・M circuit, 44a -= J! f HE device, 44b
-= SIN ROM (SIN READ ON'LY
MEMORY), 45...ADC (analog-digital conversion circuit E), 46...delay frequency divider circuit, 47...frequency divider circuit for internal signal generation, 48-reference signal oscillator, 49-delay time setter, 410- First memory circuit, 411, second memory circuit, 412... addition circuit, 413... fIil
] Circuit applicant'p? Figure J7 Procedure Supplementary Letter (Spontaneous) July 1981 Commissioner of the Japan Patent Office Mr.■, Patent Application for Indication of Case 1982-gO'? 9/2 Name of the invention Radio direction finder 3 Relationship with the amended person's case Patent applicant 2-10-45 Kamiosaki, Tokyo Parts Industry Ward 141 Specification/
Drawings 5 Description of the contents of the amendment / engraving of the drawings (no changes to the contents) 6. List of attached documents (1) 1 copy of the specification for the amendment (2) 1 copy of the drawings for the amendment Procedural amendment (voluntary) 1932! [May 21, 2009], Patent Application for Indication of the Case, Patent Application No. 1988-8 f) 99] 2. Name of the invention: Radio direction finder: (Relationship with the person making the amendment Patent Application 3' Person〒141 Tokyo Parts District" Niinuzaki 2-1 +,) ~
45 Specification 1 Document 5. Contents of amendments As shown in the attached amended statement 6. List of attached documents (1) 1 copy of the amended statement Contents 1. The following points in the description are amended.

Claims (1)

[Claims] (1) In a stationary Doppler direction finder, omnidirectional antennas are arranged at equal intervals on the circumference, and the antennas are sequentially switched and scanned to detect the arrival direction of smudge waves based on the phase change of the received signal. The product output of the generated azimuth signal and the internal signal obtained from the internal signal generation circuit is sequentially stored in a memory group consisting of memories corresponding to each antenna, and the memory value is integrated by an adding circuit for a period of integer multiple of the scanning period. A wireless direction finder, characterized in that the phase of the internal signal is controlled by: (2. In the wireless direction finder according to claim 1, two groups of the memories are provided, and the first memory group multiplies the product output by a predetermined period, and transfers this to the second group of memories. The memory values of this second memory group are integrated to control the phase of the internal signal, and if the input to the first memory group is incorrect due to momentary interruption of received radio waves such as AI radio waves, etc. Instead, it processes the values in the second memory group and transfers them to the first memory group.
A radio direction finder characterized by inputting into a memory group.