JPS59204334A - Parity monitoring system applied to digital transmitter put in scrambling operation - Google Patents

Abstract

PURPOSE:To monitor accurately the quality of transmission by a parity check on a scrambled input signal by ORing exclusively the parity count result of the input signal and that of a scramble signal. CONSTITUTION:A scramble period is denoted as TS and a parity check period is represented as TP; and scramble periods are represented as TP1-TPN from the initial time slot in order, and this section is regarded as the parity check section. The parity count result of the input signal in a section TPi (i=1-N) is denoted as Pi and that of the scramble signal is represented as PSi, which is calculated previously and stored in a memory M. Counted values TPi are read out of the memory M successively through a read circuit R corresponding to the periods TPi while synchronizing with a timing signal C and EXORed with a counted value Pi to output the parity check bit R'i of the scrambled signal. Consequently, the quality of transmission is monitored accurately regardless of the length and contents of the scramble signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity monitoring method for monitoring transmission quality applied to a scrambled PCM signal transmission device.

Conventionally, in general PCM signal transmission equipment, in order to monitor the quality of the signal transmission section, a pulse with a previously known code is inserted on the transmitting side, and the receiving side checks for errors in the pulse. Count the monitoring method, input signal marks, and spaces.

The resulting information is added to the signal sequence and sent.

The RIJ check method is applied in which the receiving side counts the input signals again and compares the result with the added information to check for code errors. Among these, the parity check method is more often adopted because it is more accurate in detecting false errors and has a faster detection time. Furthermore, in this type of transmission equipment, in order to smooth the spectrum of the modulated signal and to make it easy and stable to detect the clock signal on the receiving side, the thin tube 1 is preliminarily used in accordance with the above-mentioned conventional method. FIG. 2 is a block diagram showing an example of the configuration of a transmission system to which the method is applied.

In this figure, the PCM signal input to terminal 1 is
The number of marks and spaces is counted by the harrity counting circuit 2,
The result is added to the signal string as 79 +) tee. The signal string with parity added is scrambled by the scramble circuit 3.
After the scrambled signals are added together, the signal is sent to repeaters 4 and 5 as a signal SD. These repeaters output code error information EI+E2 of each quality in order to monitor the quality of the transmission section. The input signal received on the receiving side is scrambled and inputted to the parity error detection circuit 6, where code errors in the relay section are monitored, and then passed through the descrambling circuit 7 to the input signal on the transmitting side. is played. Note that a parity error detection circuit 8 is provided at the subsequent stage of the descrambling circuit 7 to detect failures that occur mainly after the parity error detection circuit 6, and the output signal D' reproduced through this circuit is It is output from terminal 9.

In this way, according to the conventional parity check method in which a scrambling operation is performed, the parity check period 'rp
and the scrambling period Ts have a quadratic relationship.

Tp ” N ’ Ts (N ”” 1 r 2 +
``' + n: integer). In this case, if the number of marks is fixed to an even number, the repeater and receiver It is possible to match the parity counting result of the scrambled signal on the transmitting side with the parity counting result of the input signal before scrambling on the transmitting side.However, in PCM transmission using a multilevel modulation method in high efficiency transmission, Smoothing the spectrum of the modulated signal is important, and it is necessary to lengthen the scrambling period and appropriately adjust the correlation between the scrambled signals.However, in this method, when the scrambling period is lengthened, the harness check period However, if the correlation of the scrambled signal is adjusted appropriately, detection errors may occur.In order to avoid this situation, we try to perform the probability counting without relying on the scrambled signal. In this case, descrambling must be performed on all repeaters, making the two circuits complicated and uneconomical.

The purpose of the present invention is to obtain the input signal that has been counted. By performing appropriate logical operations on the IJ check information, transmission quality can be accurately monitored by parity checking of scrambled input signals, regardless of the length or content of the scrambled signal, and with a simple configuration. The aim is to provide an economical parity monitoring scheme that can be used.

According to the present invention, the present invention is applied to a digital transmission device that performs a scramble operation, and includes a memory that stores parity counting results of scrambled signals, and information stored in the memory.
e includes means for reading out every IJT cycle, and an exclusive OR circuit that takes a logic between the parity count result of the input signal and the information read from the memory, and performs a parity check on the output of the exclusive OR circuit. A parity monitoring method characterized by using bits is obtained.

Next, let's talk about the parity monitoring method according to the present invention.

This will be explained with reference to the drawings.

FIG. 2 theoretically shows the features of the parity monitoring system according to the present invention. In this figure.

M is a memory element such as a flip-flop or ROM.

R is a read circuit for reading memory from memory element M, and EX and OR are exclusive OR circuits.

The operation of the circuit configured as described above will be explained with reference to the time chart in FIG.
Name it 1'rpN for Tp2#. now.

Considering the case of Ts=N-Tp (N=1.2.-, n), the parity check interval Tpi (i=1 + 2
+...

Let Pi be the result of parity counting of N), and Psi be the value of parity counting of the scrambled signal corresponding to that section, then the parity counting result Ri of the scrambled signal is as follows.

It can be expressed as Ri=Pi*Psi (1). In this equation, ■ represents an addition function modulo m, and when 2m=2, it becomes an exclusive OR.

Let's explain using m = 2 as an example.

Equation (1) becomes Ri = Pi when Psi"O and Ri = Pi when Psi = 1. Here, Pi indicates the complement logic of Pi. This means that y Ps
If i ''O, the parity count result of the scrambled signal matches the parity count result of the input signal before being scrambled, and if p Psl ``' 1, it means that the count result is inverted.

By the way, in the above, since the scramble signal is known, the parity count Psi (i=1 t
2 m..., N) is calculated as the predecessor, and this is stored in the memory element M. Then, Psi is sequentially read out from this memory element M in synchronization with the timing signal C and in correspondence with the scrambling period.

EX, between the OR circuit and the above Pi.

By performing the logical operation (2), errors due to parity can be detected not only in the relay section but also regardless of the descramble operation performed on the receiving side. By this, transmission quality can be evaluated.

FIG. 4 is a block diagram showing the configuration of the first embodiment when the logical operation according to the present invention is performed on the transmitting side. According to this example, an unscrambled PCM signal created by the transmitter on the transmitting side is applied to the terminal 11 and subjected to parity counting in the parity counting circuit 12. The result is given to the crit logic control circuit 13, where a logic operation is performed between it and the parity count result of the scramble signal stored in the memory in advance.

It is added to the input signal as a parity check bit. A scramble signal is added to the PCM signal to which the noise and litice sound pits have been added in a scramble circuit 14, and the resulting signal is sent to repeaters 15 and 16 as a signal SD. Repeaters 15 and 16 and parity error detection circuit 17 on the receiving side. The operations of the descrambling circuit 18 and the parity error detection circuit 19 have the same functions as those indicated by reference numerals 4, 5, and 6 to 8 in the conventional example of FIG. 1, so a description thereof will be omitted.

FIG. 5 is a block diagram showing the specific configuration of the transmitting side in FIG. 4. In this figure, parallel input signals D1*D2+...y DN are applied to a zf ity counting circuit 12, where a harness check bit P is obtained. On the other hand, from the memory IJ 13-1 built in the nosority logic control circuit 13, the parity count information P8 of the scramble signal stored internally is sequentially read out according to the timing signal C supplied from the scramble circuit 14. Ru. The parity check bit P from the parity counting circuit 12 and the parity count information Pa read from the memory 13-1 are the parity logic control circuit 1.
3, and a logically controlled noise check pit R' is obtained on the output side. This parity check pit is given to the parity check pit addition circuit 13-3, and among the input signal strings applied to this input side, one breast deviation of DI%DN is added for each parity check period. be done. The output signal string of the parity check bit adding circuit 13-3 is given to the scrambling circuit 14, and adders 14-1 to
14-N and scramble signal generation circuit 14-
The signal S Di is scrambled by the signal from 10
eSD2. ...becomes tsDN.

FIG. 6 is a block diagram showing the configuration of a second embodiment in which the logical operation according to the present invention is performed on the receiving side. According to this example, the unscrambled PCM signal created in the transmitting side transmission device is applied to the terminal 21 and is counted by the frequency counting circuit 22. The counting result is added to the signal string as a function. A scramble signal is added to the signal string to which the normality has been added in a scramble circuit 23, and then sent to the repeater 24, 25 and the receiving side as a signal SD. Note that the parity counting circuit 22 on the transmitting side
．． Scramble circuit 23. The operations of the repeaters 24, 26 are shown by reference numerals 2, 3, . . . in the conventional example of FIG. It should be understood that they have the same functions as those shown in 4 and 4 and 5, respectively. The signals reaching the repeater 24, 26 and the receiving side, respectively, are applied to Nokriti error detection circuits 25, 27 and 28, respectively, equipped with features according to the invention.

Then, the code error output E of the signal at each location is
1yE2 and E3 are detected. On the receiving side,
The signal SD' that has passed through the crit error detection circuit 28 is applied to a descrambling circuit 29.

Here, it is descrambled and reproduced as a signal on the transmitting side. This reproduced output is applied to a criticality error detection circuit 30 having the same configuration as the conventional one, and is checked for faulty errors mainly in order to detect faults occurring after the criticality error detection circuit 28. It is derived from terminal 31 as output signal D'.

FIG. 7 is a block diagram showing a specific configuration of the error detection circuit 28 on the receiving side of FIG. 6. In this figure, the received parallel input signal S
D'l, SD'2t..., 5DIN are given to a parity counting circuit 28-1, where an output P resulting from parity counting is obtained. On the other hand, from the memory 28-2, the parity count information pa of the scramble signal stored internally is sequentially read out according to the timing signal C supplied from the descrambling circuit 29. The output P of the parity counting circuit 28-1 and the parity counting information Ps read from the memory 28-2 are connected to an exclusive OR circuit 28-3 which together with the memory 28-2 constitutes a logic control circuit.
, and a logic-controlled a+ property check pit R' is obtained on the output side. On the other hand, the parity information detection circuit 28-4 detects the parity information added to the signal string from any one of SDI' to SD/ every parity check period. Then, the output of the exclusive OR circuit 28-3 and the output of the logic information detection circuit 28-4 are applied to a comparison circuit 28-5, where a code error output E3 is detected by comparing the two. Ru.

In addition, in FIG. 7, the explanation was given using the no-critity error detection circuit 28 as an example, but the y4 provided in the relay example
The error detection circuits 25 and 27 are similarly configured.

Needless to say, even in this case, implementation is possible as long as the scramble signal is known.

As is clear from the above description, according to the present invention, a logical operation is performed between the result obtained by parity counting the input signal and the parity counting result of the scrambled signal stored in the memory. By rubbing.

By simply rewriting the memory contents, it becomes possible to freely set the solitary period and scramble period, and change the scramble signal arbitrarily, and it can also be applied to multilevel modulated PCM transmission systems.

The advantageous effect is that the transmission quality can be economically monitored without complicating the configuration and with high detectability 7.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a transmission system to which the conventional tRity check method is applied, FIG. 2 is a block diagram showing the principle of the characteristics of the parity monitoring method according to the present invention, and FIG.
The figure is a time chart for explaining the operation of Figure 2.
FIG. 4 is a block diagram showing the configuration of the first embodiment when the logical operation according to the present invention is applied to the transmitting side, FIG. 5 is a block diagram showing the specific configuration of the transmitting side in FIG. 4,
FIG. 6 is a block diagram showing the configuration of a second embodiment when the logical operation according to the present invention is applied to the receiving side, and FIG. 7 shows a concrete example of the parity error detection circuit 28 on the receiving side of FIG. FIG. 2 is a block diagram showing a configuration. In the figure, 12.22 is a nority counting circuit. 13 is a parity logic control circuit, 14.23 is a scrample circuit, and +5.16 and 24.26 are repeaters. 17, 19. 25, 27, 28, 30 are parity detection circuits, and 18.29 are descramble circuits. 13-1.28-2 is a memory, 13-2.28-3 is an exclusive OR circuit, 13-3 is a parity check bit addition circuit, 14-1 to 14-N are addition circuits, 14-10
is a scramble signal generation circuit. Reference numeral 28-1 is a logic counting circuit, reference numeral 28-4 is a logic information detection circuit, and reference numeral 28-5 is a comparison circuit.

Claims (1)

[Scope of Claims] 1. A memory that is applied to a digital transmission device that performs a scramble operation and stores the result of a parity count of a scrambled signal, and means for reading out information stored in the memory for each parity cycle; It includes an exclusive OR circuit that performs logic between the t4 property count result of the input signal and the information read from the memory. A 4-reality monitoring system characterized in that the output of the exclusive OR circuit is an i4-reity check bit. 2. In the criticality monitoring system according to claim 1, the criticality count result of the input data signal on the transmitting side is added as one input of the exclusive OR circuit. 'Critity Monitoring Method 3' In the parity monitoring method according to claim 1, the parity counting result of the input signal on the relay side or the receiving side is added as one input of the exclusive OR circuit, and checking an input signal to which parity information is added using the output of the exclusive OR circuit as a parity check bit.