JPS59202789A - Television receiver - Google Patents

Abstract

PURPOSE:To realize a very inexpensive receiver with high performance without using an expensive reference oscillator newly by providing a storage means storing a digital chrominance signal until the next horizontal period and a pulse width modulating circuit converting an output digital chrominance signal of the storage means into a pulse width modulation chrominance signal by means of a clock signal. CONSTITUTION:A clock for A/D converting is supplied via a frequency divider 55 by a voltage controlled type oscillator (VCO) 56. Digital three primary signals being outputs of A/D converters 54R, 54G, 54B are inputted in parallel with 360 sets of memories 60a, 60b,...60n at R, G, B respectively. The memories 60a-60n are constituted of simple data latch circuits storing at R, G, B in parallel by 6-bit each. The digital three primary chrominance signals selected by switching are applied to 360 sets of pulse width modulation (PWM) circuits 70a, 70b...70n. Since a clock 2mfsc for PWM uses the identical frequency to that of the clock (ndsc) of the A/D converter, the circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver that records video signals for one horizontal scanning period and outputs and displays them using the next horizontal scanning period. It is.

Such systems include: - Flat-type video display tubes or liquid crystals that sequentially scan horizontal scanning lines in the vertical direction, EL channels, LE
It is most suitable for television receivers using flat display elements such as D panels and plasma panels.

Conventional configurations and their problems Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes are extremely long and thin compared to the screen size. It was impossible to create a shaped television receiver. In addition, although EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements, all of them are insufficient in terms of performance such as brightness, contrast, and color reproducibility of color display. , it has not yet been put into practical use.

Therefore, we aimed to achieve a device that can display color television images on a flat display device using electron beams, and we divided the screen on the screen into multiple sections in the vertical and 4 directions. An electron beam is generated for each section, each electron beam is deflected vertically for each section to display a plurality of lines, and further divided horizontally into a plurality of sections and each section is divided into R- The G, B, etc. phosphors are made to emit light in sequence, and the amount of electron beam irradiation to the R, G, B, etc. phosphors is controlled by a color video signal, thereby producing a television image as a whole. Something to display was devised.

Without further ado, a basic configuration example of the image display element used here will be described with reference to FIG.

This display element includes, in order from the back to the front, a back electrode 1, a line cathode 2 as an electron beam source, a vertical focusing electrode 3,
3', vertical deflection electrode 4, electron beam flow control electrode 5, horizontal focusing electrode 6, horizontal deflection electrode 7, electron beam acceleration electrode 8
and a screen plate 9 are arranged, and these are housed inside a flat glass bulb (not shown) which is evacuated. A line cathode 2 serving as an electron beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction. In the figure, only four wires 2-2 are shown). In this embodiment, it is assumed that 15 pieces are provided. Let's say 2i~2yo.

These wire cathodes 2 are constructed by coating an oxide cathode material on the surface of a tungsten wire having a diameter of 10 to 20 μΦ, for example.

As will be described later, the back electrode 1, which is controlled to emit an electron beam sequentially for a fixed period of time starting from the upper line cathode 2a, creates a potential gradient between it and the vertical focusing electrode 3, which will be described later. It acts to suppress the generation of electron beams from other line cathodes 2 other than the line cathode 2 which is controlled to emit electron beams for a certain period of time, and to push out the generated electron beams only in the forward direction. . This back electrode 1 may be formed by a coating of conductive material applied to the inner surface of the rear wall of the glass bulb. However, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 1o facing each of the line cathodes 2a to 2yo, and the electron beam emitted from the line cathode 2 is taken out through the slit 10, and Focus vertically.

The slits 10 may be provided with crosspieces at appropriate intervals in the middle, or may be substantially a row of through holes arranged horizontally at small intervals (nearly touching intervals). It may also be configured as a slit.

The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally at intermediate positions between the slits 10, and conductors 13 and 13' are provided on the upper and lower surfaces of the insulating substrate 12, respectively. It consists of Then, a vertical deflection voltage is applied between the opposing conductors 13 and 13',
Deflect the electron beam vertically. In this configuration example, the electron beam from one line cathode 2 is deflected to a position corresponding to 16 lines in the vertical direction by a pair of conductors 13 and 13'. The 16 vertical deflection electrodes 4 constitute 15 conductor pairs corresponding to each of the 15 line cathodes 2, and in the end, the electron beam is deflected to draw 240 horizontal lines on the fleece 9. do.

Next, each of the control electrodes 5 is composed of a conductive plate 15 having a vertically long slit 14, and a plurality of control electrodes are arranged in parallel in the horizontal direction with a predetermined interval. In this configuration example, 320 control electrode conductive plates 15a to 15n are provided (only 10 are shown in the figure). Each of the control electrodes 5 extracts the electron beam horizontally by dividing it into one picture element at a time, and controls the amount of electron beam passing therethrough in accordance with the video signal for displaying each picture element.

Therefore, by providing 320 control electrodes 5, it is possible to display 320 pixels per horizontal line. In addition, in order to display images in color, each picture element has 3 colors of R-G-B.
Display is performed using colored phosphors, and R, G, and B video signals are sequentially applied to each control electrode 5. Also, 32
320 sets of video signals for 1 line are simultaneously applied to 0 control electrodes 5, and the video for 1 line is displayed at one time.

The horizontal focusing type electrode 6 has a plurality of vertically long lines (320 lines) facing the slit 14 of the control electrode 5.
□ Consisting of a conductive plate 17 having a conductive plate 16, the electron beam for each picture element divided in the horizontal direction is focused in the horizontal direction into a narrow electron beam.

The horizontal deflection electrode γ is composed of a plurality of conductive plates 18 arranged vertically in the middle of each of the slits 16, and a horizontal deflection voltage is applied between each conductive plate 18 for each picture element. The electron beams are respectively deflected in the horizontal direction, and each of the R-G and B phosphors are sequentially irradiated on the screen 9 to cause them to emit light. In this embodiment, the deflection range is the width of one picture element for each electron beam.

The acceleration electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4.
The electron beam is accelerated to collide with the screen 9 with sufficient energy.

The screen 9 is constructed by coating the back side of a glass plate 21 with a phosphor 20 that emits light when irradiated with an electron beam, and then adding a metal back layer (not shown).

For each slit 14 of the control electrode 5, that is, for each horizontally divided electron beam, one pair of phosphors 2o is provided in three colors of R and G-8. It is applied in stripes in the vertical direction.

In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view of FIG. 2, one section partitioned by these two has two R-G-B phosphors for one picture element in the horizontal direction.
It has a width of 16 lines in the vertical direction.

The size of one section is, for example, one armpit in the horizontal direction and 16 mm in the vertical direction.

It should be noted that in FIG. 1, the length in the horizontal direction is drawn much larger than the length in the vertical direction for the sake of clarity.

Further, in this embodiment, only one pair of R-G-B phosphors 20 for one picture element is provided for one control electrode 5, that is, one electron beam, but for two or more picture elements. Of course, two or more pairs of picture elements may be provided, and in that case, R-2a-B video signals for two or more picture elements are sequentially applied to the control electrode 5, and the horizontal deflection is synchronized with the R-2a-B video signals for two or more picture elements. It will be done.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a description will be given of the driving portion that irradiates the screen 9 with an electron beam to cause the phosphor to emit light and generate a raster.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element. DC' heavy pressure of v6 is applied to the horizontal focusing electrode 6, v8 is applied to the accelerating electrode 8, and direct current '6 is applied to the screen 9.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal "2" and a horizontal synchronization signal H.

The vertical drive pulse generation circuit 25° is configured with a counter that is reset by the vertical retrace pulse and counts horizontal pulses, and is configured to cover an effective vertical scanning period (in this case, a period of 240H) excluding the vertical retrace period of the vertical period. 15 drive pulses (42 pulses, J...Y) each having a length of 16H are sequentially generated. These drive pulses (42, . . . ) are applied to the line cathode drive circuit 26, where they are inverted so that they are at a low potential only during each pulse period and at a high potential of approximately 20 volts during the rest of the pulse period. are converted into linear cathode driving pulses [412'...Y'], and each linear cathode 2, 20.・・・・・・Added to 2yo. Each line cathode 2a, -2yo is its driving pulse [a'
An electric current is applied during the high potential period of the drive pulses [A' to Y'], and the heated state is maintained so that electrons can be emitted even during the low potential period of the drive pulses [A' to Y']. As a result, electrons are emitted from the 15 line cathodes 2i to 2yo only during the 16H period when low potential drive pulses [a' to yo'] are applied to each of them. During the period when a high potential is applied, the potential at the line cathode 2 is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the applied higher potential is more positive, no electrons (d) are emitted from the line cathodes 2a-2y.Thus, at the line cathode 2, the upper line Electrons are emitted sequentially from the cathode 2 to the lower line cathode 2 for each 16H period.The emitted electrons are pushed forward to the back electrode 1, and are pushed out to the opposing slit 10 of the vertical focusing electrode 3. The beam passes through the beam and is vertically focused into a flat electron beam.

Next, the vertical deflection drive circuit 27 generates a vertical drive pulse [A~
It consists of a counter that counts the horizontal synchronizing signal re-centered by each of the vertical drive pulses [I to Y], and a conversion circuit that converts the count output to D/A. A pair of vertical deflection signals v and v' which change in 16 steps by 1H are generated.

Vertical deflection signals V and V' both have a center voltage of v4, N increases sequentially, and V' decreases sequentially.
They are designed to change in opposite directions. These vertical deflection signals V and V' are applied to the electrodes 13 and 13' of the vertical deflection electrode 4, respectively, and as a result, the electron beams generated from the respective line cathodes 2I to 2Y are unidirectional in the vertical direction.
The beam is deflected in six steps, and as described above, on the screen 9, one electron beam is deflected so that a raster of 16 lines is drawn one line at a time from the top.

As a result of the above, electron beams are emitted for each ieH period in order from the top of the 15 line cathodes 2I to 2Y, and each electron beam is sequentially emitted for one line from the top to the bottom within the 15 sections in the vertical direction. By being deflected, the screen 9
At the top, the electron beam is vertically deflected one line at a time from the 1st line at the top to the 240th line at the bottom.
A total of 240 lines of raster are drawn.

The electron beam thus vertically deflected is divided into 320 sections in the horizontal direction by the control electrode 5 and the horizontal focusing electrode 6 and extracted. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 to become one narrow electron beam. The RGB phosphors 20 on the screen 9 are
irradiate sequentially.

That is, the horizontal drive pulse generation circuit 28 is composed of three monostable multivibrators connected in cascade, and is triggered by a horizontal synchronization signal to generate three horizontal drives with equal pulse widths within one horizontal period. pulse r, g, b
occurs. Here, as an example, each pulse width is about 17 μSec, and the effective horizontal scanning period is 5
Three pulses r, q, and b are generated during 0 μsec. 6 horizontal drive pulses r, q,
b is added to two horizontal deflection drive circuits. This horizontal deflection drive circuit 29 has a horizontal drive circuit r + 'J + b.
A pair of horizontal deflection signals RI and h' which are switched in three stages are generated. Horizontal deflection.

Both h' have a center voltage of 7, and change in opposite directions, with h increasing by 11 pages and h' decreasing sequentially. These constant quotient signals, h', are applied to electrodes 18 and 18' of the horizontal deflection electrode γ, respectively.As a result, each horizontally segmented electron beam can The light is horizontally deflected so that the R, G', and B phosphors of window 9 are sequentially irradiated for 17 μSec each.

However, in the display element of FIG. 1, in the horizontal deflection electrode one conductor 18 or 18' is used for deflecting the 7E beams of two adjacent sections;
Adjacent electron beams are deflected in opposite directions, so if the electron beams in 320 sections are deflected in the odd-numbered order or in the order of R-G-8, For even-numbered sections, conversely, B-G-H
It is deflected in the opposite direction every other section, such as being deflected in the 1- direction.

3 in the horizontal direction in the raster for each line.
Electron beam or R, G for each of the 20 sections.

Each phosphor 20 of B is sequentially irradiated.

Therefore, for each horizontal section of each line, the R and G electron beams are
, B, a color television image can be displayed on the screen 9.

Next, the modulation control portion of the electron beam will be explained.

In addition to being added to the TenVision signal input terminal 23, the composite video signal is added to the color demodulation circuit 3o, where R
-Y and B-Y color difference signals are demodulated, the G-Y color difference signals are matrix-synthesized, and further, they are combined with the luminance signal Y, each of the R, G, and B primary color signals (hereinafter referred to as R, G.
A B video signal) is output. Those R, G, B
Each side image signal has 320 sample and hold circuit sets 31a.
~31n. Each sample and hold circuit group 31
8 to 31n each have three sample and hold circuits for R, G, and B. Zangle-hold outputs of these sample-and-hold circuit sets 31a-31n are applied to holding memory sets 32a-32n, respectively.

On the other hand, sampling reference clock oscillator 331.1P
It is composed of an LL (phase locked loop) circuit, etc., and generates a reference clock of approximately 6.4 MHz in this embodiment. The reference clock ' is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.

This reference clock is applied to the sampling pulse generation circuit 34, where it is delayed by one cycle by the shift register register, etc. As a result, the horizontal period (63,
The effective horizontal scanning period (approximately 5QμS)
ec), 320 sampling pulses a-n are sequentially generated, and one transfer pulse is generated six months later.

This sampling pulse a-n is one of the images to be displayed.
It corresponds to each picture element when the line is divided into 320 picture elements in the horizontal direction, and its position is controlled so that it is always constant with respect to the horizontal synchronizing signal H.

These 320 sampling pulses a-n are respectively connected to the 320 sets of sample hold circuits 1fiJ131a.
~31n, and each sample-and-hold circuit set 31a-32n is individually sampled with the R, G, and B video signals of each picture element when one line is divided into 320 picture elements. The sampled and held 320 sets of R, G, and B video signals are transferred all at once to 320 sets of memories 32a to 32n by a transfer pulse t after one line of sample and hold is completed.
1 line of R held in Nomo 1J32a to 32n is held for the next horizontal scanning period.
G and B video signals are applied to 320 switching circuits 35a to 35H, respectively. Switching circuit 35a
~35n are R and G, respectively.

Each switching circuit 35a has individual input terminals of B and a common output terminal that sequentially switches and outputs them.
The output of ~35n is used as a control signal for modulating the electron beam by the 320 conductive plates 15a of the control electrode 5 of the display element.
~15H each separately. Each switching circuit 36a to 35n is a switching pulse generation circuit 36
are simultaneously switched by a switching pulse applied from '+hl)011. The switching pulse generation circuit 36 is controlled by the pulse r+q+b from the horizontal drive pulse generation circuit 28 mentioned above, and the effective horizontal scanning period of each horizontal period is approximately 50 μsec divided into three, which is approximately 17 μS.
Switch the switching circuits 35a to 35n by ec, and R
, G, and B video signals are time-divided and output alternately and sequentially,
A switching signal r to be supplied to the control electrodes 15a to 15n,
Generate g and b. However, the switching circuit 35a~
35n, odd-numbered switching circuits 35a,
35C... is switched in the order of R→G→B,
Even-numbered switching circuits 35b, 36d-==-
35n is reversely switched in the order of 13-+G-)H.

What should be noted here is that the switching circuits 35a to 3
The supply switching of R, G, and B video signals at 5n and the horizontal deflection of the electron beam irradiation switching to the R, G, and E phosphors by the horizontal deflection drive circuit 29 are completely performed in both timing and order. They are synchronously controlled to match. As a result, when the electron beam is irradiating the R phosphor, the irradiation amount of the electron beam is controlled by the R video signal, and G and H are similarly controlled, so that the R, G, and B of each picture element are controlled in the same manner. The light emission of the phosphor is controlled by the R, G, and B video signals of each picture element, and each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously on 320 picture elements for one line to display one line of video, and then sequentially performed on 240-minute lines starting from the upper line, so that one video is displayed on the screen 9. It turns out.

The above operations are performed on one input television signal.
Each field is returned, and as a result, a moving television image is displayed on the screen 9 in the same way as on a normal television receiver.

As described above, television images are displayed on this display device.

Note that the terms horizontal direction and vertical direction in the above explanation refer to the direction in which line units are displayed when displaying an image is the horizontal direction, and the direction in which the lines are stacked is the vertical direction. Although it is used in this sense, it is not directly related to the vertical and horizontal directions on the actual screen.

However, the apparatus of the example described above had the following disadvantages. The first is variation in the output level due to variation in the capacitance of the capacitor used as the analog memory of the sample hold circuit. Second
is the stability of the sampling clock. Unless stability is increased using a PLL circuit or the like, the cause of clock instability will manifest itself in the expansion and contraction of the image in the horizontal direction. However, P.L.
The L circuit configuration requires a highly stable reference oscillator such as a crystal oscillator, resulting in an extremely expensive configuration.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a device free from such inconveniences, which uses a digital memory as a storage device for one horizontal period in which variations occur, and which can display even if there is some level variation in the output. By using only the on and off states of the elements and controlling the brightness at time intervals, a pulse width modulation method can be used, which provides extremely good uniformity.

Furthermore, by using signals of even multiples of the color subcarrier (f8o = 3.58 MH2) for both the A/D converter clock for digitization and the clock used for pulse width modulation, expensive This makes it possible to realize an extremely inexpensive and high-performance external receiver without using a new base oscillator.

Structure of the Invention The television receiver of the present invention includes a clock generating means for generating a signal having a frequency that is an even multiple of the color subcarrier in synchronization with a color subcarrier extracted from a received color television signal; an A/D converter for converting a color signal extracted from a color signal into a digital color signal using a clock signal from a clock generation means; a storage means for storing this digital color signal until the next horizontal period; a pulse width modulation circuit that converts a digital color signal output from the storage means into a pulse width modulated color signal; and an image display element that displays a color television image using the pulse width converted color signal. It is characterized by having the following.

DESCRIPTION OF EMBODIMENTS The structure and operation of an embodiment of the present invention will be described below with reference to the drawings showing an embodiment of the present invention. In this receiver, the horizontal deflection, vertical deflection, and line cathode drive are 1 d
Although they are essentially the same, the modulation control portion of the signal is completely different. A block diagram of this modulation control section is shown in FIG.

A composite video signal is inputted through an input terminal 50, demodulated by a color demodulation circuit 51, and color-demodulated R and G signals are input.

The B primary color signals are sent to A/D converters 64R, 54G via output lines 53R, 53G, and 63B, respectively.

54B. This A/D converter 54R254G
, 54B may be general-purpose ones, and 6 to 8 bits are used.

The voltage D7 for the A/i) conversion operation is supplied from a voltage controlled oscillator (■C○) 56 via a frequency divider 66.

The frequency of this operating clock is the frequency fSC of the color subcarrier supplied from the color subcarrier oscillator 57 of the color demodulation circuit 51.
(m is a natural number). On the other hand, ■C○56
The phase detector 59 compares the output of the frequency divider 58, which divides the oscillation output of It constitutes a phase-locked loop circuit (PLL circuit) that oscillates at a frequency of 2 n fsc in synchronization with the differential wave. Here, if m2n = 1, then 2mfso-7
, 16 MHz, the number of data samples that can be sampled for valid video information during one horizontal scanning period is about 360.

Therefore, the effective horizontal scanning period (50μ
sec) during the period of A/360
In addition to the D converters 54R, 54G and 54B, the three primary color signals are each converted into digital three primary color signals of 6 bits each.

The digital three primary color signals output from the A/D converters 54R, 54G, and 54B have 360 sets of memo I) for each of R, G, and B.
The signals are input in parallel to 60a, 60b, . . . 60n. These memories 60a to 60n are each R,
It is simply constituted by a data latch circuit that records 6 bits in parallel in G, B, etc., and its latch pulse is supplied by the shift register 62 via lines 61a to 61n. This shift register 62 is constructed as described above (m = n =
If it is 1, it is a 360-stage parallel output shift register, and its clock is supplied with the clock of mf8o from the frequency divider 55.
The horizontal synchronizing signal, which is a clock-width pulse (from the synchronizing separation circuit 62) and output to the line 64, is differentiated by the differentiating circuit 65, and is appropriately delayed by the D flip-flop 63 until the start time of the effective video information. An AND gate 966 generates an AND output of the signal and the mf clock and uses it. In this case, the special F
/C There is no need to delay it significantly; it is sufficient to pass through the D-flip and Pflossop 630 to stages as shown in FIG. 4 /ζ.

The differential output of the differential circuit 65 is stored in the memory 60a...
The data contents of 60n are stored in 360 sets of memories 67a...
5, this memo IJ 67a...67n corresponds to the memories 32a to 32n in FIG. ffl] The contents of the memories 60a to 60n are transferred to the memories 67a to 67n all at once during the horizontal retrace period.

Next, the three primary color digital signals of R, G, and B in the memories 67a to 67n are switched and taken out by switching circuits r', g', and b' applied via lines 69. This suisoting no ζrus r',
g' and b' are output nockle pulses r and q of a circuit similar to the switching nockle generating circuit 36 in FIG.

The switched and selected digital three primary color signals (described later) are generated using 360 sets of pulse width modulation (PWM) circuits 70a and 70.
b....Supplied to 70n. A clock for operating the PWlvi circuits 70a to 70n is supplied from a frequency divider 65 via a line 72. This PWM clock 2mf8o is the aforementioned A10 conversion clock (nf8
Since the frequency is the same as o), the circuit can be simplified.0 Also, if a 2nf6G clock is used as the PWM clock, the output of vC○56 can be appropriately inhibited.

- Can be used only by performing dance conversion.

In addition, in FIG. 4, the three primary color output signals of the color demodulation circuit 51 are
The D converters 54R and 54G perform '64B digital conversion, but the composite video signal can be converted directly to A/
Exactly the same effect can be obtained by using a configuration in which D conversion is performed and then digital demodulation is performed.

Since the outputs of the PWM circuits 70a to 7Qn are generally at a logic level, they are increased by the output terminals 73a to γ3n so that the saturation level and the cutoff level tG of the control electrodes 15a to 15n are increased. 7
4n, and this output signal is output to the control electrode 1 of the display element.
5a to 15n.

Next, we will explain the specific circuit configuration and timing of each part in sections 5 to 9.
As shown in the figure. Here, Al1) converter case 54R, 54
The following explanation assumes that the output of G and 54B is 6 bits. First, Figure 5 shows memo 1J6oa.

60b..., memories 67a, 67b... and switching circuits 68a, 68b... are circuit examples. Memory 6 o a , eo b-=・-1
67a, 67b... are data latch circuits 60aR, 60aG, 60aB-- for each bit.
, 67aR.

67aG, 67aB, etc., and an example of each is shown in FIG. Here, this circuit is composed of AND gates 75, 76, an input gate 77, and an OR gate 78, and the input signal to the data input terminal is a high-level data latch pulse applied to the gate terminal G. Output terminal Q only when
The input state at the negative edge of the data latch pulse to the gate terminal G is transferred to the output terminal Q.
is output as a storage output signal.

Memo! Latch pulse 61a of J 60a, 60b...

61b... is the output pulse of the shift register 62 as mentioned above, and 360 sets of memories 60a to 60n
1 pulse is input sequentially during one horizontal scanning period. As a result, the A/D converted digital primary color signal is 1
360 sets of horizontal scanning JtA are stored in memory 6oa, 6o
b... is stored in... The memory 60a corresponds to the leftmost picture element on the screen, and the memory 60n is the rightmost picture element.

The stored contents are outputted to the data latch output terminal Q in FIG. 6, and then connected to the input terminals of the next memories 67a, 67b, . . . . Memo 1J67a.

The memory circuits for each bit 67b, . . . are also data latch circuits having the same configuration as in FIG. The other pulses of the memories 67a, 67b, etc. are data transfer pulses, which are commonly supplied to all terminals. The data transfer pulses are simultaneously applied to the memories 67a and 67e.
It will be transferred to +7b...

The switching circuits 68a, 68b... are the sixth
In the figure, 6 bits are shown together, but in reality, one each is connected in series to the output terminal Q of each bit of the memories s7a, e7b, . . . .

A tri-state buffer circuit can be used as the switches 68a, 68b, . . . . Its control input, 'ffi switching pulse γ'+
9' and b' are generated as shown in FIG. That is, the pulse 'l'J+b is the output of the switching pulse generation circuit 36 shown in FIG. Switching pulse r', g', b'i switching pulse r,
This is generated by a mono-multi-bi break triggered by the positive edge of g and b. the result,
The data selected by the switching circuits 68a, eab, etc. are converted into switching pulses r', g',
b' PWM 70a during the nopulse period.

-rob... is supplied.

Each PWM circuit 7oa, 7ob...
As shown in FIG. 8, it is composed of a 6-bit presettable counter 79 and a reset priority R-S flip-flop 84 made up of NAND gates 80 to 82 and an inverter 83. The digital primary color signals for each picture element selected by the switching circuits 68a, 68b, . . . are sent to a presettable counter 79.
The data is preset by adding the switching noggle r+'J rb to the load terminal of the counter 79 via the OR gate 85 at the same time. Then, the counter 7 counts the '6c signal o and y signal from the frequency divider 56, and the flip-flop 84 is set by the carry output.

Therefore, the thicker the digital primary color signal, the earlier the cent point becomes. On the other hand, as shown in FIG. 9, the D-flip-flop 86 is driven by the switching pulses r, q, b and the 2mfso clock.
r, 86g, aeb, and N.

A reset pulse creation circuit composed of R gates 87r, 87g, 87b, AND gates 88r, 88g, ssb, and OR gate 89 creates a reset pulse Re with each negative edge of the switching pulse "Fq+b", and Reset Nodunlop 84.

As a result, in the PWM circuit of FIG. 8, the trailing edge of the output pulse from the output terminals Q and Q becomes the switching pulse "r'
fixed at each negative edge of J + b,
The output pulse, which has undergone pulse width conversion so that the leading edge changes according to the magnitude of each of the three digital primary color signals, is -
Digital red light, digital edge signal during approximately 50μ5ecO during the horizontal period.

Output sequentially in the order of digital green signal. The maximum pulse width of each output signal is approximately 17μ5liiC (=1/f
soX64 bit).

In this way, the PWM circuits 70a to 70n output pulse widths that correspond to the end of the digital three primary color signals, and output the ζPWM output signal, which is predetermined by the pulse amplifiers 73a to 73n. It is a good idea to amplify the electron beam to the level of the electron beam and add it to the control type beams 15a to Isn of the display element as shown in FIG. and can display color television images.

Effects of the Invention As described above, according to the present invention, by using the color subcarrier, which is essential for television receivers, as the reference for all frequencies, the subsequent signal processing circuit can be realized extremely stably and at low cost. It is possible.

[Brief explanation of the drawing]

FIG. 1 is an exploded perspective view showing the basic configuration of an example of an image display element used in a television receiver according to an embodiment of the present invention, FIG. 2 is an enlarged view of the screen, and FIG. 3 is a drive of the device. A block diagram showing the basic configuration of the circuit, Fig. 4 is an overall block diagram of a television receiver in one example of this invention, Fig. 5 is a detailed circuit diagram of a part of the memory and switch section, and Fig. 6 is the circuit diagram for one bit of that memory,
FIG. 7 is a timing diagram thereof, FIG. 8 is a circuit diagram of its PWM circuit, and FIG. 9 is a circuit diagram of its PWMIJ set pulse generation circuit. 2...Line cathode as an electron beam source, 3,3'
... Vertical M focusing electrode, 4 ... Hand deflection electrode, 6 ... Electron beam flow control electrode, 6 ...
Horizontal focusing electrode, γ...Horizontal deflection electrode, 8...
・Electron beam accelerating electrode, 9...screen, 2Q・
...Fluorescent material, 23...Input terminal, 24.
... Synchronization separation circuit, 25 ... Vertical drive pulse generation circuit, 26 ... Line cathode drive circuit, 27.
... Vertical deflection drive circuit, 28 ... Horizontal drive pulse generation circuit, 29 ... Horizontal deflection drive circuit,
3Q...Color demodulation circuit, 318-31n...mark...
Sample hold circuit group, 32a to 32n...
Memory group, 34...Sampling pulse generation circuit, 35a-35n...Switching circuit, 36
...Switching pulse generation circuit. Dai Jl! lj Person's name Patent attorney Toshi Nakao Male Haga 1 person Figure 2 1ii7'': 11 H Naga in the direction of aquatic plants Figure 3 U 1su 6 Peng Peng 0

Claims (2)

[Claims] (1) clock generation means for generating a clock signal having a frequency that is an even multiple of the color subcarrier extracted from the received color television signal in synchronization with the color subcarrier; an A10 converter for converting the digital color signal into a digital color signal using the clock signal from the clock generation means; a storage means for storing the digital color signal until the next horizontal period; A television receiver comprising: a pulse width modulation circuit that converts a digital color signal output from a storage means into a pulse width modulated color signal; and an image display element that displays a color television image using the pulse width converted color signal. . (2) A patent claim in which a phase-locked loop circuit is used as a clock generation means, and an A/D conversion clock signal and a pulse width conversion clock signal are generated by frequency-dividing the output signal of the phase-locked loop circuit. The television receiver according to item 1.