JPS59202541A - Pipeline adder - Google Patents

Abstract

PURPOSE:To speed up the pipeline addition by providing a means which decides whether or not a sign is to be inverted depending on the other input sign of a floating point adder. CONSTITUTION:When a left input 2-1 and a right input 2-2 are transferred to the 1st stage 2, a signal 2-6 designating the conditional NOT is outputted to the 1st stage by a microprogram controller 5 and an exponential part 3-13 of the right input 2-2 is selected by a selector 11. In designating the conditional NOT by a conditional NOT designating signal 2-6, an exponential part 3-13 of the right input 2-2 is selected always independently of a carry output 3-5 of a subtractor 10 and when the conditional NOT is executed by a signal 2-5, whether or not an output 3-3 of a register 15 latching the right input sign is to be inverted is decided by an output 3-2 of a register 16 latching the left input sign, thereby attaining high speed processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a floating point arithmetic circuit, and more particularly to a pie-in adder for speeding up functional operations.

[Prior art]

In the conventional pipeline adder, when a conditional branch appears in the middle of an operation, multiple processes are performed in the flow shown in FIG. As shown in the figure, the conditional branch processing procedure is as follows.

1) Judgment of conditions 11) Deciding on the process according to the judgment of the condition 111) Execution of the process FIG. 2 shows the operation of the pipe engine when the condition is judged in FIG. 1 and the process A is executed. In the figure, an example is taken in which the Viblin counter is configured with a two-stage pipeline, and the vertical axis shows the processing at each stage of the pipeline, and the horizontal axis shows the machine cycle. As shown in the figure, it was necessary to use a twice-pipeline adder due to conditional judgment and processing nature. - Furthermore, when a conditional branch is executed, operations cannot be overlumped, and parallelization, which is a feature of pipelines, cannot be performed, resulting in a reduction in calculation performance.

[Purpose of the invention]

The purpose of the present invention is to quickly realize conditional negation, which is a conditional clause branch that occurs when performing a functional operation, by determining whether to invert the sign of one sign and inverting the other sign. The goal is to provide a pipelined adder that allows

[Summary of the invention]

Provide conditional operations as operations executed by the pipeline adder. When an instruction specifying this conditional operation is issued to the pipeline adder, the pipeline adder determines the condition in the flow of the pipeline and performs processing that matches the condition.

[Embodiments of the invention]

FIG. 3 shows the IEEE Standard 70-TEG data format single precision. In the figure, l-1 is the significand sign, 1
-2 is the exponent part, and 1-3 is the mantissa part of the absolute value representation. The exponent part 1-2 has a correction value added to it and is expressed as a positive value. Since the mantissa is normalized, the first bit is always 1, so the first bit is omitted in the format. You can use this 7-oh mantle to cover your face; to your face (
-1)l'2°-BX(1,F). However, B is an exponent part correction value.

FIG. 4 shows the configuration of the pipeline adder. In the figure, 5 is a microprogram controller that controls the pipeline adder, 1 is the pipeline adder, 2 is the first stage of the pipeline adder, 3 is the second stage of the pipeline adder, and 4 is the nokube line. The third stage of the adder, 2-1 is the left input of the two-in adder, 2-2 is the right input of the pipeline adder, 2-3 is the output of the pipeline adder, and 2-4 is the input from the microprogram controller 5. Pipeline adder operation mode designation signal that is output multiple times,
2-6 is a number 46 that specifies conditional negation for the pipeline adder first stage 2, which is outputted multiple times by the microprogram controller 5, and 2-5 is a pipeline outputted multiple times from the microprogram controller 75. This signal specifies conditional negation for the adder second stage 3.

FIG. 5 shows the detailed configuration of the pipeline adder 1. In the figure, 10 is a subtracter that takes the difference between the exponent parts of the left input 2-1 and right input 2-2 of the pipeline adder 1, 3-5 is the carry output of the subtracter 10, and 3-12 is the left input 2-2. ! 3-13 is the 3-day number part of the right input 2-2, 11 is the output 2-6 of the microprogram controller 5 and the subtractor lO
A selector that selects the exponent value controlled by the carry output 3-5, 3-14 the output of the selector 11, 12 a register that latches the output of the selector 11, and 14 latches the carry output 3-5 of the subtracter 10. register, 13
is a register that latches the output of the subtracter 10, 15 is a register that latches the sign of the right input 2-2, 3-3 is the output of register 15, 16 is a register that latches the sign of the left input 2-1, 3-2 is register 16 output, 17 is register 1
5 and 16 outputs and microprogram controller 5
21 is a register that latches the output of register 12. 23 is left input 2-1 and right input 2.
A comparator that compares the magnitude of the mantissa of -2, 24 is comparator 2
3, 25 and 26 are registers that latch the mantissa parts of the left input 2-1 and right input 2-2, respectively.19 is the register 14 output 326 and the microprogram controller 5 output 2-5. A mantissa control signal generator 3-7 generates a mantissa control signal, a mantissa control signal 27 is generated by the mantissa control signal generator 19, and a mantissa control signal 27 is controlled by the mantissa control signal 3-7. 28 is a selector that shifts the output of selector 27 to the right according to the output of register 13; 29 is a selector that selects either the output of register 25 or the output of shifter 28 according to the mantissa control signal 3-7; 3
0 is a selector that selects either the output of the register 26 or the output of the shifter 28 based on the mantissa control signal 3-7, and 32 is the addition/subtraction mode creation unit 17, output and mantissa control signal 3-7.
7 and registers 13 and 24 outputs, a mantissa operation mode creation unit creates a mantissa operation mode, 3-11 is an operation mode created by the mantissa operation mode creation unit 32, and 31 is A-E.

Arithmetic logic unit (ALU) with operation modes of B-A, A+B, and B; 33 is a counter for detecting the number of shifts for normalizing the output of ALU 31; 18 is a microprogram controller output 2 -4 and register 15,
16, 24 output ROM for creating the code of the operation result;
3-1 is the ROM 18 output, 20 is a conditional sign inverter that determines the sign according to the condition when executing the conditional negation instruction based on the microprogram controller output 2-5, the register 15.16 output, and the ROM 18 output 3-1; -4 is the output of the conditional sign inverter 20, 36 is a register that latches the conditional sign inverter 3-4, 34 is a register that latches the output of the counter 33, 35 is a register that latches the output of the ALU 31, and 22 is a register that latches the output of the ALU 31. A subtracter that corrects the exponent part associated with normalization, 3-9 is the output of the subtracter 22, and 37 is the register 3.
Shifter 3 that shifts the 5 output according to the register 34 output;
-10 is the shifter 37 output, and 3-8 is the register 36 output.

The procedure for carrying out the invention will be explained below. First, stage 2
The left input 2-1 and right input 2-2 are transferred to the left input 2-1 and the right input 2-2. At this time, the microprogram controller 5 outputs a signal 2-6 specifying the negation of the condition "A" to the first stage 2, and the selector 11 outputs the signal 2-6 to the exponent part 3-1 of the right input 2-2.
3 is selected.

The configuration of the selector 11 is shown in FIG. In the figure, when conditional negation is specified by the conditional negation designation signal 2-6, the right input 2-
The exponent part 3-13 of 2 is selected, and the output 3-1 of the selector 11
It will be 14. Selector outputs 3-14 are stored in register 12. Also, at this time, the left and right input sign and mantissa data are stored in registers 16, 15, 25, and 26, respectively. The second stage 3 operates in the next machine cycle. At this time, the microgrossim controller 5 outputs a signal 2-5 specifying conditional negation. When this signal is output, the mantissa control signal generator 19 selects the output of the right input mantissa register 26 with the selector 30, and selects the output of the right input mantissa register 26.
A signal is generated to be input to LU31. FIG. 7 shows the configuration of the mantissa control signal generator 19. In the figure, when conditional negation is designated by the conditional negation designation signal 2-5, '1' is always output regardless of the output 3-6 of the register 14.

Based on the output 3-7 of the mantissa control signal generator 19, the selector 30 selects the output of the register 26. At this time,
The mode of ALU31 is determined by conditional negation designation signal 2-5.
This is a mode in which the 9B input is output as is. Also,
Based on the conditional negation signal 2-5, the code of the conditional negation instruction execution result is created in the conditional sign inverter 20. FIG. 8 shows the configuration of the conditional sign inverter 20. FIG. 9 shows the operation of the conditional sign inverter. As shown in the figure, when the conditional sign inversion unit specifies conditional negation using the conditional negation designation signal 2-5, the right input sign is output by the output 3-2 of the register 16 that latches the left input sign. It is determined whether the register 150 output 3-3 latched is inverted or not, and processing is performed accordingly. If conditional negation is not specified, the output 3-1 of the code generator ROMI 8 is used as the code of the operation result. Output 3- of conditional sign inversion unit 20
4 is stored in register 36. Further, the register 12 output and the ALU output are also stored in registers 21.35, respectively. Furthermore, in the next machine cycle, the third stage 4 operates. At this time, the output of the register 21 is not processed by the subtracter 22 and is output as is. Furthermore, the output of the register 35 is not processed by the shifter 37 and is output as is. Outputs 3-8 of register 36,
Output 3-9 of subtracter 22 and output 3-10 of shifter 37
are the sign part, exponent part, and mantissa part, respectively, and the output 2 of the pipeline adder 1 is the result of executing the conditional negation instruction.
-3. In this way, a conditional negation instruction is executed which determines whether or not to invert the sign of the right input 2-2, depending on the sign of the input 2-1 of the pie-free adder. The operation of the pipeline at this time is shown in FIG.

In the figure, the vertical axis shows processing in each stage of the pipeline adder, and the horizontal axis shows machine cycles.

As shown in the figure, when executing a conditional branch, the pipe-in adder only needs to be used once, and operations can be overlapped.

〔Effect of the invention〕

According to the present invention, it is possible to execute a conditional judgment of a conditional branch (conditional negation) that occurs during the execution of an operation and a process according to the conditional judgment by using a pipeline adder only once. It can be made faster.

[Brief explanation of the drawing]

Figure 1 is a conditional branch calculation flowchart, Figure 2 is an explanatory diagram of pipeline operation, Figure 3 is an IEEE standard single-precision data format diagram, Figure 4 is a schematic diagram of a pipeline adder, and Figure 5 is pipe-in addition. Detailed view of the vessel, Figure 6 is the 5th
7 is a block diagram of the mantissa control 1d code generator in FIG. 5, FIG. 8 is a block diagram of the conditional sign inverter in FIG. 5, and FIG. 9 is a block diagram of the The explanatory diagram, FIG. 10, is an explanatory diagram of the operation of the pipeline.

Claims (1)

[Claims] 1. Calculate the difference between the exponent parts of two floating point data11
Number part subtractor, first selector that selects all values of the pointing part, d'r
-j a second selector for selecting pseudo-block data to be shifted to align the digits with the output of the branch subtracter; a shifter for aligning the output of the first selector with the output of the exponent subtracter; A mantissa arithmetic unit that calculates the output of the shifter or the mantissa whose digits are not aligned, a counter that detects the shift number for normalizing the operation result, and a leftward shifter for the mantissa that normalizes the operation result. , in a floating-point adder consisting of a subtracter that performs exponent correction associated with normalization, a conditional code that inverts or outputs the sign of the other input as is, depending on the sign of one input of the floating-point adder. A floating point arithmetic circuit characterized by having an inversion section. 2. In claim 1, the arithmetic process is divided into a plurality of stages, and the end of these valley stages is defined as pipeline addition. vessel. 3. A pipeline adder according to claim 2, characterized in that the conditional sign inversion unit in claim 1 is provided in a second stage.