JPS59201871A - Dot printer controlling circuit - Google Patents

Abstract

PURPOSE:To prevent useless loss of data and overheating of a driving section by operating an initial resetting circuit in a certain time after any uncontrollable action of a CPU in a control circuit of a dot printer with the CPU. CONSTITUTION:Now when a CPU40 starts an uncontrollable action in a dot printer control circuit due to a noise or the like, no resetting signal S3 is sent out from the CPU40 and a division circuit 20 moves H in the (n) division output S4 after the time T1 to turn ON a transistor Tr, which causes a capacitor C to be discharged in an initial resetting circuit 30. A data reception forbidding signal A from an interface circuit 60 moves to H by an initial resetting signal S2 to stop the data transmission from a host system 70 regardless of the state of the signal D from the CPU40 thereby preventing useless loss of data. The signal S2 causes a gate 80 to be closed to cut off a solenoid drive signal E thereby preventing overheating due to continuous electric energization of a solenoid drive circuit 50.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit for an impact dot printer, and more particularly to a method for recovering from runaway when a CPU is used in the control circuit.

In conventional control circuits that use a CPU, if the CPU goes out of control due to external noise or fluctuations in the power supply voltage, it may stop operating or cause looping (the inability to remove the circuit from a single routine). If this occurs while the print solenoid is being driven or the motor is rotating, there is a risk that the print solenoid or motor will overheat and cause a flame due to continuous energization. Also, if the CPU goes out of control after issuing a signal that can receive signals from the host system while receiving signals from the host system, the CPU may be in a state where it cannot receive data. Involved RB A, I)
Since the Y signal is output continuously, the host system sends print data more and more, causing loss of important data.

The purpose of the present invention is to provide a dot printer control circuit that eliminates the above-mentioned drawbacks, and the gist thereof is as set forth in the claims above.

Next, preferred embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of the present invention, in which 10 is an oscillation circuit, 20 is a frequency dividing circuit that receives a signal from the oscillation circuit 10, and 3
D is an initial reset signal generation circuit that initializes the CPU 40 and other circuits; 40 is a frequency dividing circuit 20;
50 is a solenoid drive circuit, 60 and 80 are parts that require an initial reset signal when the power is turned on, 60 is an interface circuit, 80 is A, N I) It is a gate. 7
0 is the host system that sends print data to C1) U3O.

Next, the operation of the present invention will be described with reference to the block diagram of FIG. 1 and the time chart of FIG. 2. When all the power is turned on, the capacitor C of the initial reset circuit O is charged through the resistor I, and it remains at the initial TI level for 2 hours until this voltage S1 reaches the value of the inverter 1. Generates reset signal S2.Initial reset signal 8
2 is occurring, the CPU 40 is stopped and the state of the solenoid drive signal E is unknown (is it "H" or "L")?
80 is closed to prevent the solenoid from being driven.

Furthermore, the interface circuit 60 indicates that the CPU 40 is in a state where it cannot accept data, and sends the 5 signal A to 01-(
, 61 to the host system 70FC. When the initial reset signal S2 reaches the LI+ level, the CPU 40 starts operating and sends the signal B from the oscillation circuit 10 to the frequency dividing circuit 2.
The reset signal S is output within a period shorter than the period T1 during which the output S4 whose frequency is divided by n by 0 is output. Naturally, this signal S3 is issued while driving the solenoid or while exchanging signals with the host system 70. If the CPU 40 cannot receive data from the host system 70 while controlling the print solenoid, it sends a signal.
-1", the signal A- indicating that print data cannot be received from the 61 is sent to the host system, and when it becomes possible to receive print data, the signal A- is set to L°'. 11 J, ゛ to receive data from the host system and exchange signals with the host system.

Now, if the CPU 40 goes out of control due to some factor, for example, noise, the reset signal S6 will no longer be output from the CPU 40. Then, in the frequency dividing circuit 20, the 11 frequency divided output S4 becomes ``[10''] after T1 time after the reset signal S6 ceases to come, and the transistor Tr becomes conductive, so the initial reset is performed.
- The charge in the capacitor C of the circuit 6o is discharged to an initial state, and an initial reset signal s2 is generated. When the initial reset signal S2 is generated, data is not received from the interface circuit 60 regardless of the state of the output signal 7'1 of the CPU 40. 'No signal'
Data transmission from the post system 7° is stopped before the 1 is outputted as a river 1'' and the CPU 40 returns to normal operation, thereby preventing unnecessary loss of data.

Also, due to the runaway of the CPU 40, the solenoid is continuously energized.
Even if the solenoid is on, when the initial reset signal s2 is generated, the gate 80 is closed, so the solenoid drive signal E from the CPU 40 is cut off, and continuous energization is canceled. When the signal s4 of the frequency dividing circuit 2o becomes 'L ==' after a certain time 'I゛1 after becoming 'T('), the capacitor C is charged through the resistor R, and the voltage of sl reaches the quotient value of the inverter filter 1. Then, the initial reset signal s2 becomes ++L
++, and the cPU4o starts normal operation again.

As explained above, in the dot link control circuit according to the present invention, even if the CPU goes out of control, the initial reset circuit works after a certain period of time to prevent unnecessary loss of data and overheating due to continuous energization of the solenoid or motor. The practical effect is a dog.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a dot printer control circuit according to the present invention, and FIG. 2 is a timing chart showing the operation of FIG. 1. 10 - Oscillation circuit, 20 Frequency division circuit, O initial reset generation circuit, R resistance, C capacitor, 31 - Inverter, 4Q -, CPU, 50 - Solenoid drive circuit, 60 - Interface circuit, 70 - Host system. Ministry of Procedure and Correction (Voluntary)” 2. Display of the case 1982 Patent Application No. 0'7'723'7 2, Name of the invention Dot printer control circuit 3, Person making the amendment Relationship to the case Patent applicant Telephone: 0555-3-1231 1' 4, Amendment order date 6, "Claims" column of the specification to be amended, "Detailed Description of the Invention" column 7 of the specification, "Contents of the amendment/Claim 1 of the specification" in an attached document. to correct. - On page 2 of the specification, line 4, the phrase ``Causes a flame.'' is corrected to ``Causes a fire.''・In the 15th line of page 5 of the Memorandum, change the phrase “after a certain period of time Tl” to “
After a certain amount of time.'' Claims: An oscillator circuit, a frequency divider circuit that divides the output of the oscillation circuit by n and outputs a signal, and receives the n-divided output of the frequency divider circuit to be in an initial state, and is initial reset when the power is turned on. Sends a signal to the part that requires it - resets the initial reset generation circuit and the previous generation circuit within a certain period of time, and also controls the pudding solenoid by receiving signals from the host system A dotgusonta control circuit characterized by comprising a CPU configured as follows.

Claims (1)

[Claims] An oscillation circuit, a frequency divider circuit that divides the output of this oscillation circuit by n and outputs a signal, and a part that receives the n-divided output of the frequency divider circuit and becomes an initial state and requires an initial reset signal when the power is turned on. an initial reset oscillator circuit that sends a signal to the frequency divider circuit, and resets the frequency divider circuit within a certain period of time;
A dot printer control circuit characterized in that it is equipped with a CPU that controls a print solenoid in response to a signal from a host system.