JPS61172756A - Thermal recording apparatus - Google Patents

Abstract

PURPOSE:To protect a recording element, by stopping the supply of a current when a current is supplied to the recording element for an abnormally long time. CONSTITUTION:A protective circuit 11 is interposed between an enable signal 10 and an AND gate 3 and, when the above-mentioned enable signal 10 is a L-level, the output of a comparator 13 is a L-level and a point E comes to a L-level and no enable is applied. Next, when the signal is a H-level, the output of an inverter 14 comes to a L-level and Q1 is turned OFF and, at the same time, a current is flowed to a condenser CX through an external resistor RX to raise potential at a point B. The rising in potential is determined by the time constants of the above-mentioned resistor RX and the condenser CX. When the potential at the point B is set to VB, the comparator 13 is reversed when the potential VB became equal to the reference voltage V-comp of the comparator 13. When a time constant at this time is set to tCR, the point E comes to a L-level when the pulse width of the signal is longer than the above- mentioned time constant and an output power transistor 4 is turned OFF and the damage of a heat generating resistor element 5 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a thermal recording device such as a thermal printer or a bubble jet printer that performs recording by generating heat in a recording element.

(Prior Art) FIG. 1 shows a head circuit section of a conventional thermal printer, and components other than a heating element 5 are included in a driver IC. The head circuit section includes a serial-in/parallel-out shift register 1, latch 2. AND acting as an enable
It is composed of an output power transistor 4 that drives a gate 3 and a thermal head heating resistor element 5. The shift register l has a size of several bits, and may also have a serial output. Clock 7 and data 8 are input to shift register l, and data 8 is serially shifted by clock 7. After all data has been read, a latch signal 9 is input and the data in the shift register I is latched into the latch 2. After that, the enable signal 10 is input and the output power transistor 4 is turned on.
, OFF control.

When the enable signal 10 is at a low level, regardless of whether the latch data is low or high, the enable input on one side of the AND gate 3 is at a low level, so the output is at a low level and the output power transistor 4 is turned off. When the enable signal 10 is at a high level and the data in the latch is also at a high level, the ANDNO gate output is at a high level, and the output power transistor 4 becomes ONI, and current flows through the thermal head heating resistor element 5 to perform printing. Enable signal 10 is normally pulled down.

It becomes low level even when the input is open.

The output power transistor 4 is ONL. However, due to external factors such as the mounting board,
If the enable signal IO is short-circuited with the power supply or a high-level signal, or if the logic circuit that generates the enable signal IO malfunctions and remains at a high level, the output power transistor 4 is a 0-heating resistor in which current continues to flow through the ONL heating resistor element. The element burns out if current continues to flow for a long time (several tms). In that case, the thermal head must be replaced, but repair costs increase and it is difficult.

(Objective) It is an object of the present invention to eliminate the above-mentioned drawbacks and protect the recording element by stopping the energization when the recording element is energized for an abnormally long time.

(Embodiment) FIG. 2 shows an embodiment of the present invention, in which enable signal input 1
A protection circuit 11 is inserted between 0 and the AND gate 8, and everything other than the heating resistor element 4 is housed within the driver IC.

FIG. 3 shows details of the protection circuit 11. In FIG. 0, 13 is a comparator for comparison with a reference potential, 14 is an inverter for inverting the enable signal, and 15 is an inverter for inverting the enable signal.
16 is a power supply inside the IC, 17 is a terminal to which an external resistor RX and a capacitor Cx are attached, and 18 is a power supply terminal of the IC. Comparator 1
At one side input of 3, a reference voltage is created by R1 and R2,
The voltage V-camp is V-comp=R2/R1+R2-VCC (1).
An external resistor RX is connected to the GND side, an external capacitor Cx is connected to the GND side, and a transistor Q1 is connected as an internal circuit from the output of the inverter 14 through R3. When the enable signal 1oypt<a- level, the transistor Q1 becomes ONL, and the + side input of the comparator 13 becomes the GND level.

When the enable signal 10 is at high level, it is turned off and +
The potential of the external capacitor CX is input to the side input. In FIG. 3, the + and - of the comparator 13 are reversed, and N
The operation is the same even if the OR gate 15 is replaced with a NAND gate. Also, the gate can be bipolar or MOS, and if MOS is used, Q1 is an N-channel MOS)
Becomes a transistor.

Next, the operation of the protection circuit will be explained using FIG. 4. The alphabet ANE in FIG. 4 corresponds to the alphabet position in FIG. 3, and is the operating waveform at the point indicated by the alphabet. First, when the enable signal 10 is at a low level, the + side input of the comparator 13 is at the GND level, so the output of the comparator 13 is at a low level. Since point 0 is a low level and point D is a high level, E
= Low level due to CNORD, no enable is applied When the 9th order enable signal 10 is high level, the output of the inverter 14 is low level and Ql is O
FF. At the same time as the switch is turned off, a current flows through the external capacitor Cx through the external resistor RX, and the potential at point B rises.

The rise in potential is determined by the time constant of external resistor RX and external capacitor Cx, and if the potential at point B is VB, then VB=VCC[1-exp(-t/CX ・RX)
] (2), V-compwVB
When , the comparator 13 is inverted. If the time constant at that time is tCR, then from equation (1) = equation (2), R2
/R1+R2-VCC =VCC[1-exp(-tCR/CX IIRX)
] (3) tcR=cX11RX11in (R1
+R2/R1), and the pulse width of the enable signal 10 is longer than tcR in equation (4), the comparator 13 is inverted at the time tcR, the output is high level, and the output of the NOR gate 15 is low level, The output power transistor 4 will be turned off. Further, when the enable signal 10 is smaller than tcR, the comparator 13 is not inverted, and the enable signal 10 remains as it is at the NOR gate 15.
is output as the output of

As described above, the protection circuit 10 of the present invention can prevent damage caused by current flowing through the thermal head heating resistive element 5 for a long period of time. However, it is assumed that tcR is within the allowable time allowed by the thermal head heating resistor 5, and that the enable signal IO is pulled down.

(Other Embodiments) Another embodiment of the present invention is shown in FIG. 5.The above-mentioned embodiment was processed in an analog manner using a comparator, but in this embodiment, processing was performed digitally. In the figure, 20 is a T flip-flop with clear power, 21 is a D flip-flop with clear power, 22 is an inverter, 23 is a NOR gate, 24 is a ring oscillator with an odd number of inverters connected in series, and 25 is a clock. 24 may be used as an external input terminal.

The operation will be explained using FIG. 6. When the enable signal 1O is at a low level, the Q output becomes a low level by manual clearing of the flip-flops 20 and 21. NOR gate 2
Since the input C of 3 is low level and the input d is high level, the output is low level and is not re-enabled.When the enable signal lO becomes high level, external clock input 2
5. Alternatively, the clock of the ring oscillator 24 is divided by a T flip-flop, and after a certain time tD, the output of the T flip-flop at the final stage becomes high level. When the delay time is tD and the period of the input clock is tak, the following equation is obtained.

tD=takX2” (5)
When the output of the T flip-flop in the final stage becomes high level, the Q output of the D flip-flop also becomes high level.
Since point 0 is at high level and point D is at low level, the output of the NOR gate 23 is at low level. D until tD
NO because the output Q of the flip-flop is low level.
The output of the R gate 23 becomes high level and is enabled.

When an enable signal with a long pulse width is input, the Q output of the T flip-flop in the final stage becomes a pulse waveform with a width of tD, but because of the presence of the D flip-flop 21, the Q output of the D flip-flop Once it reaches a high level, it remains at a high level until a clear signal is input.

(Effects) As described above, in the present invention, when the energization time to the recording element becomes abnormally long, the energization is stopped, so that the recording element can be effectively protected. In addition, the stopping means is a driver IC.
This allows for more efficient implementation.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a head circuit section of a conventional thermal printer, and FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 is a block diagram of the protection circuit, FIG. 4 is an explanatory diagram of the operation of the embodiment, FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of the embodiment. l is a shift register, 2 is a latch, 3 is an AND gate 34
is an output power transistor, 5 is a heating resistor element, 6 is a head voltage, and 7 is a clock input. 8 is a data input, 9 is a latch input, 10 is an enable input, it is a protection circuit, 12 is an enable, 13 is a comparator, 14 is an in/<-51-. 15 is a NOR gate, 16 is VCC, 17 is an external terminal,
18 is the vcc terminal, 19 is the comparator voltage, 20 is T
21 is a D flip-flop, 22 is an inverter, 23 is a NOR gate, 24 is a ring oscillator, and 25 is an external clock input.

Claims (2)

[Claims] (1) A thermal recording device that performs recording by generating heat in a recording element, characterized in that the thermal recording device is equipped with a means for stopping energization to the recording element when the energization time to the recording element becomes abnormally long. Recording device. (2) The thermal recording device according to claim 1, wherein the means is incorporated into a drive IC for driving the recording element.