JPS59200910A - Device for deciding spot-like defect - Google Patents

Abstract

PURPOSE:To decide a defect on the surface of a sheet-like substance by applying non-linear quantizing processing to data taken out from an object to be tested and amplifying and integrating a fine defect to extract features including the defect appearing on the surface of the object to be tested. CONSTITUTION:Picture data in a print is fetched and sampled by using an image sensor or the like to extract K1 required data. The data of the n-th picture element in the extracted data is level Sn. A difference (Sn-Sn+1) is extracted from the extracted data and then A/D converted K2 to obtain a difference quantized signal Fn. The signal Fn is integrated and the peak is detected. Then, a signal En to be turned to H at a position detecting the peak and L at another point is formed K3. Thus, a binary-coded signal En is formed. The processing K1-K3 are executed for a reference print at first and then the signal En is written K4, K5 in a memory as a reference binary-coded data Esn. Testing binary-coded data EIn for the print to be tested is also obtained by the processing K4. The data Esn is collated K6 with the data Ein to test the print to be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for determining spot-like defects appearing on the surface of a sheet-like object, and more particularly, to an apparatus for inspecting printed matter to determine minute printing defects.

Taking printed matter as an example, visual inspection is a simple and reliable method for inspecting patterned printed matter, that is, printed matter on which an image including a picture is printed, and is widely used. However, there are limits to inspection speed, poor efficiency, and individual differences in the ability of inspection workers.
There are problems such as variations in inspection accuracy depending on the degree of fatigue of the body M's.

On the other hand, in order to inspect for stains on the original material, that is, unprinted paper or printed matter with a simple pattern, an image sensor is used to detect the peaks (mainly minimum points) in the signals captured from the surface of the object to be inspected. Yes (Japanese Patent Publication No. 46-21514). However, this is true on the condition that the signal level fluctuation in the defective part is sufficiently larger than that in other parts, and it is not possible to inspect a printed image for which this condition is not satisfied.

In addition, a method using a floating threshold value for detecting minute t peaks in image sensor output (Japanese Patent Publication No. 54-3638)
This is generally done using analog signal processing such as However, analog signal processing is easily influenced by noise and is prone to malfunction. Furthermore, analog processing cannot detect peaks in complex signals such as pictures.

The present invention has been made in consideration of the above points, and an object of the present invention is to provide an apparatus that can accurately detect minute defects in patterned printed matter or original fabric.

To achieve this objective, the present invention performs a linear quantization process on the data extracted from the inspected object, such as a patterned print or an original fabric, to amplify minute defects and suppress spike-like noise and edge components in the image. Then, by integrating within a predetermined saturation level range, features including defects appearing on the surface of the object to be inspected are extracted, and if necessary, the defects are determined by comparing them with a reference pattern. .

The present invention will now be described by way of example with reference to the accompanying drawings.

FIG. 1 is a flowchart for generally explaining the defect detection operation of patterned printed matter according to the present invention.

First, image data of printed matter is captured using an image sensor, etc., and then sampling is performed (including both standard and inspected data) to extract the required data. It is assumed that the data of the nth pixel in the extracted data is level Sn (K
1). The data extracted by sampling is the difference (s
n+ 8n-1) and further K A/D conversion (K2)
Get Fn. This is pre-processing for the next peak detection process.

Integrate Fn and detect the peak. Forms a signal Kn that becomes K1 at the position where the peak is detected and becomes L at other points (K3
). As a result, a binarized signal In is formed.

Processes □ to 3 above are first performed on the Hoshijin version,
The obtained En is written into the memory as the standard binary data Fisn' ``a * K5).The same process is then performed on the print to be inspected to obtain the inspection binary data ``In'' (K4). ). This test binarized data is stored.

FIGS. 2 to 4 are diagrams for explaining the principle of the image signal processing method according to the present invention. First, Figure 2 shows the characteristics of the difference quantization (K2) in the 70-chart in Figure 1, and shows the difference (s) extracted by sampling.
n + 5n-1) - "jl mountain 101..., N's (
2N+1).

This characteristic is a midtread type nonlinear generator characteristic, and when the difference (Sn-8n-1) is a small value, it has a value corresponding to the difference, but the difference (an-8n-1) has a value corresponding to the small value.
7. 1) becomes a large value beyond a certain level. Even if m is used, the maximum is N
or produces an output that only has a value of -N.

As a result, the input/output characteristics are such that low level fluctuations are emphasized and high level fluctuations are suppressed. This means that minute defects in printed matter that correspond to low-level fluctuations are highlighted, while spike-like noise and image edge components that correspond to high-level fluctuations are suppressed.

Next, Figures 3(a) and (b) show the image signal of the printed matter to be inspected and the integral value of the quantized output Fn obtained from the characteristics shown in Figure 2.
This is shown in comparison with rn. In the image signal in the same figure (al), Po is a spike-like noise, and Pl and P4 are peaks. This image signal is differentiated into a doji in the range of 2B++1) and is integrated with a saturation level of ±(N+1). As a result, the output shown in (1) in the same figure is obtained. A in FIG. 3(b) is a portion corresponding to the spike noise PoK in FIG. 2(IL). The spike-like noise Po takes a value of -N during quantization, but its saturation value is taken as ±(N+1)K during integration, so the integrated output is 0.
It doesn't go down to the level.

On the other hand, B and O correspond to peaks P1 to P4.

Each point of the DSE has reached the θ level. Peak detection is then performed by detecting that the signal has reached the 0 level or passed the θ level. Detecting peaks without detecting spike-like noise means detecting gradual and relatively small changes in the image signal rather than steep and large changes in the image signal. A determination is made as to whether or not it has the meaning that the pattern is to be inspected using the peak that it represents.

In order to perform peak detection using the θ level, the integral value T
When n reaches the θ level, the value is shifted to the saturation level along the direction of value change at that time. In the case of point B, the integral value is in the OK direction from the soil direction, so shift the value to -(N+1), and in the case of point 0, it increases from one direction and reaches the θ level, so +(N+1) shift until By shifting this value, the next peak detection can be performed accurately.

The reason why the shift width is set from 0 level to saturated believer (N+1) is to prevent the next pattern feature from being undetected and being overlooked.

In peak detection using this θ level, for example, 0
By setting the level to "1" and setting the saturation level to roJK, a binarized output can be obtained, which is extracted pixel by pixel.

Figure 4 shows a pattern matching method using the binarized peak detection output extracted by the method shown in Figure 3. Since only the inspection pattern ``In'' is examined (, 2 addresses before and after it, that is, IDxn+2, i-noxn+1
, Ksn for the 4th address of Fixn-1, 1xn-2
Contrast with In this way, the cardinality pattern and the test pattern are matched in a one-to-many manner, and any one of them may be set as one.

The reason why one-to-multiple matching is performed in this way is to prevent incorrect inspection results from being obtained when there is a deviation in the peak position due to misalignment of the printing position of the inspection print or the influence of noise.

Figure 5(a) to ((1) and Figure 6(a) to (d)
) shows more specifically the signal processing shown in FIGS. 2 and 3. Now, by sampling the image signal with the pixels as shown in (a) K in the same figure, and performing differential quantization and A/D conversion in the range of (2N+1) as h-2, the output shown in (1) 1K in the same figure is obtained. Fn is obtained.

This output Fn is +2. +1.0. -1. -2.

By integrating this output Fn with ±(N+1), that is, +3 as the saturation value, an integral output Tn shown in FIG. Then, when the integral value Tn becomes 0 or passes through, it becomes H (or 1), and otherwise it becomes L (or 0), and by binarizing it, the output shown in the figure ((1)) is obtained. In this case, there are peaks at the 9th, 12th, 177th, 200th, and 26th pixel positions,
The spike-like noise at the 14th pixel position is not detected.

Figures 6(a) to 6(d) show the process of sampling the image signal to be inspected as shown in Figure 5(a) with 28 pixels and detecting the peak, as in Figures 5(a) to (d). It is something that

FIG. 6(a) is an image signal to be inspected based on FIG. 5(a), and as shown in the same figure, there is a spot-like defect at the position of the fourth pixel in K-a.

Comparing Figure 6 (C1) and Figure 5 (di), Figure 6 (C1) and Figure 5 (di) are compared.
a) The positions corresponding to the spot-like defects (4th and 6th
An extra peak is detected at the pixel position).

Therefore, spot defects can be detected by comparing FIG. 5(a) and FIG. 6(1).

7 to 9 show specific configuration examples of each circuit constituting the device according to the present invention, and FIG. 7 shows the operation of differential quantization and A/D conversion (K2) in FIG. 1. In other words, Figure 8 (a) and (1)) shows the operation of peak detection (K3) in Figure 1, that is, the circuit that performs the case when N = 2 with the operation according to the characteristics shown in Figure 2. FIG. 9 shows a circuit that performs the case of N-2 in the operation according to the above and its operation, and FIG. 9 shows a circuit that performs the pattern matching (K6) in FIG. 1, that is, the operation shown in FIG. 4.

Among these, the circuit shown in FIG. 7 includes a differential amplifier 1 for detecting a difference ("n-8n-1), and a differential amplifier 117).
Four comparators 2.3.4 and 5 which obtain outputs and compare them with reference values V+2, V+, , v-, V-2, and an exclusive NOR circuit 6 and an OR circuit responsive to the outputs of these comparators. It consists of a circuit 7.

Here, the exclusive NOR circuit 6 and the OR circuit 7 constitute an encoding circuit, and in relation to this encoding circuit, the comparator 4 is of an inverting type. Also, the base value is selected so that the following holds true. Then, V+2 and V-4-1 are selected to be, for example, about 1% or 0.5% of the peak-to-peak level of the signal.

The comparators 2 to 5 in which the difference (Sn-8n-x) is determined from the differential amplifier 1 output H(1) and L by comparison with the above reference value.
(0) output is generated, and this output is passed through the exclusive NOR circuit 6 and the OR circuit 7 to the output terminals DOsDl, D
You can live to 2. As a result, the difference (Bn-8zi-□)
is 3-pit 5-valued and becomes a quantized signal Fn.

Figure 8 (al) shows a circuit that generates a peak detection output of approximately n when a quantized signal Fn is applied.The operation of this circuit is basically to integrate over a range of +(N+1), and the integral value is O level. By detecting the peak when
h-、P-ri Shukkei e・Sukei・No4i/Kome I (85
The operation of shifting the integral value when the monthly knee (h90 level) is reached is also performed.For this purpose, register 1 is used as a circuit element.
0° adder 8, data corrector 9, sign check circuit 11
, data check circuit 13, overflow processing circuit 12
A peak passage processing circuit 21 and the like are provided.

This circuit will be explained based on its operation. First, the register 10 and latch circuit 15 are reset to the initial state, and the register 10 is (0, 0, 0) and the latch circuit 15 is SW-off. In this state, the 5-valued data F
When n-1 is given to adder 8, the output of register lO'
rn-1 and the 5-valued data Fn-1 are added, but since the output of the initial register 10 is (0°0.0), the output of the adder 8 is the 5-valued data Fn-1. 1 itself. Here, the following explanation will be given assuming that the Kl/' register 10 is in a state where it produces an output Tn-1.

The output of adder 8 is given to data corrector 9.

When the adder 8 adds Fn-1 and 'I'n-i, there are six cases in which the result exceeds the saturation level ±3 by 70, as shown in the table below.

(Note) Carry to the 4th bit due to addition of 3 bits is ignored.

As mentioned above, when the saturation level of ±(N+1) is exceeded, the saturation level in this case is returned to ±3. a, b.

For C, return to 3; for d, e, f, return to -3.

This gives the integral value Tn, where Tn is -3 to +3
Since only seven values can be taken, the "-4" state is removed and the value is corrected to +3. Figure 8 (1)) shows the relationship between 'rn-1, Fn-1 and Tn for each case of a%f in the above table, and the inclination of a-f also exceeds the positive or negative saturation level. Therefore, it is revised to +3 or -3.

Up to this point, the adder 8 and data corrector 9 in FIG. 8(a) have been described, and the description will now return to the other circuit portions in FIG. 8(a).

The integral value Tn modified in 5 as described above is given to the sign check circuit 11, the overflow processing circuit 12, the data check circuit 13, and the like. Of these, the sign check circuit 11 is given the integral value 'rn, the quinarized data Fn=1, and the output Tn, 1 of the register 10, and calculates Tn and Tn-1.
, Fn-1 and Tn-1. The sign check is performed using MSE K, and it is assumed that O(0, 0, 0) has a positive sign. Regarding the relationship between Tn and 'rn-1, if the signs are different, the next check is performed, and if the signs are the same, no direction is performed.

'rn and Tn-1 have different signs, FD-1
Check the relationship between and Tn-1, and if the signs are different, it means that the θ level is crossed, so give the peak passing signal 61p to the OR circuit isK, and if the signs are the same, there is an overflow, so send the overflow signal Sof. Overflow processing circuit 13
, is applied to the AND circuit 19 via the OR circuit 14 and the inverter 16.

Next, when the overflow signal 8of is received from the sign check circuit 11, the overflow processing circuit 12 outputs -3 to the OR circuit 22 if the integral value Tn is positive, and +3 if Tn is negative.

Further, in the data check circuit 13, the integral value Tn is Ol, +
If it is 0, the peak passing signal Sp is given to the OR circuit 18, and if it is i:3, the saturated signal S3 is given to the OR circuit 14.

When the overflow signal Sof or the saturation signal S3 is output from the code check circuit 11 or the data check circuit 13, the latch circuit 15 is set via the OR circuit 14, which turns SW x ON. If the sign check circuit 11 or the data check circuit 13 outputs the peak passing signal Bp and the latch circuit 15 is sw-ON K:A, the two forces of the AND circuit 20 are applied together, so the peak passing processing circuit 21 is operated. and at the same time inverter 17
An output is given to the AND circuit 19 via the output terminal FinK.

The peak passing processing circuit 21 outputs +3 if it is positive, and -3 if it is negative, depending on the sign of the 5-valued data Fn-□, to the OR circuit 22.
Output to. The OR circuit 22 is also given the outputs of the overflow processing circuit 12 and the AND circuit 19,
+3 if overflow processing or peak passing processing is performed, data corrector 9 if neither is performed.
The output Tn of is written to the register 10.

As a result, the register 10 is set to 0 as shown in FIG. 3(b) and as shown in FIG.
), and as shown in FIG. 6(C)K, an output with a characteristic in which +3 is set as the saturation value and the value is shifted to the saturation value by reaching the 0 level or passing the O level is obtained.

Through this operation, the output terminal BnK is given a binary output corresponding to the peak passage as shown in FIG. 5(d).

FIG. 9 shows the shift register 23, which is a circuit that performs pattern matching using the binary signal extracted by the circuit in FIG. 8, and the signal (Esn) extracted from the standard printed matter.
The collation circuit 2 outputs each output of the shift register 25 to which
A counter 27 counts the number of matching failures, and a counter 26 counts the number of defects.

In this circuit, now the shift register 23K”In+
2 s ”In+1 s ”In s ”In-
1, Bxn-2 car, and shift register 25iCE
Suppose that sn-Hl"81]+1 s"8n is included. Then, when 1nsn is 1, check the pattern output POs of the shift register 23 from the LSB side, and if there is a 1, change OK, and if there are multiple 1s, change only the 1 on the LSE side.
Change K. If there is no O, it is a matching failure signal N.
Give M. When E8n is 00, the shift register 23 is not rewritten and the matching failure signal NM is not output.

Along with these operations, the counter 27 counts the matching failure signal NM output from the matching circuit U, and the counter 26 also counts the matching failure signal NM output from the matching circuit U.
counts the number of 1's in the serial output SOs of the shift register 23 to count the number of peaks on the base side Ktx, that is, the number of defects.

The failure signal NM is generated when (1) a significant positional shift occurs, and the number of matching failures is large and equal to the number of defects; this is different from a so-called defect.

(2) In the case of whitish defects occurring in highlight areas and dark defects occurring in shadow areas, if a defect occurs where a peak would be detected even if there is no defect, the peak detection point shifts. In this case, since the matching failure occurs locally, the number of matching failures is small. This is a so-called defect.

From this, it can be seen that defects can be determined by comparing the counts of the counters 26 and 27.

Fig. 10 shows the overall configuration of the device combining the circuits partially shown in Figs. This is the circuit that was used. In this circuit diagram, explanations based on the above figures [gate signals 01 to G6 not shown in 9]
, write signals Wl-W3, read signals R0-R3, clock signal 'CT-, and reset signal Re are shown, and each of these signals is given from a control circuit (not shown) to determine the operation timing of each circuit.

FIG. 11 (a3, (1)) shows the timing of generation of these signals; FIG. 11(a) shows the timing when the reference data is being read in, and FIG. 11(b) shows the timing during the inspection operation. Description will be given below based on FIGS. 10 and 11.

Input AIII of this circuit is an analog signal, and data is entered into the hold circuit path by applying gate signal G1. Before inputting data to the hold circuit 28, a gate signal is applied to save the data already input to the hold circuit 28 to the hold circuit 29 (as a result, the hold circuit 28 has Sn and the hold circuit 29 has 5n −
1 is included.

These data sn, 5n-1 are provided to an A/D converter 30 (FIG. 7) K. '/D converter encoded with 5
If time τl is required for signal processing until the digitized data Fn is formed, the peak detector 31 (FIG. 8(a)) is inputted by the gate signal 03.The gate signal G1 inputs the quinarized data Fn. It is sufficient to do this after τ1 after giving . At the same time as the quinarized data yn is input to the peak detector 31, the data is inputted from the register 10 to the peak detector 31.
Therefore, the read signal R1 is output at the same time as the gate signal G3. As a result, a binary signal In corresponding to peak detection is obtained.

This binary signal In is taken out via a selector S.

The selector is capable of selecting two positions: the reference side and the test side. The reference side is used when writing reference data, and the test side is used for test operations. Therefore, cases in which the selector S is located on the reference side and the inspection side will be explained separately.

(a) Processing time τ after data is input to the peak detector 31 when the selector S is on the reference side
2, a write signal 4w1 is issued from the peak detector 31 to write data into the register 10. At the same time, a write signal W3 is outputted to write the binary data Bn into the RAM 39, and a gate signal G6 is outputted to input the binary data l1in into the counter 32 to count the number of peaks.

If the object to be inspected is a scratch on a plain surface, the counted value directly becomes the number of defective flights. If only such a test is to be performed, the circuit shown in FIG. 8 is unnecessary.

(b) When the selector S is on the test side This is a case where the selector S is set on the reference side and the reference data is written, and then the reference data is used to test the test data.

In this case, the read signal R3 is output before the processing time τ2 has elapsed after the data is input to the peak detector 31, and the read signal R3 is output.
Data is read from AM 33, gate signal G4 is applied, and LEIB of shift register 23 is sent to counter 26 to count the number of defects. After time τ2 has elapsed, a clock signal CLK is applied to provide test data to the shift register 230MOB and reference data to the shift register 250M5BK.

Next, a read signal R2 is issued and the data in the shift register 23 is input into the collation circuit 24. After time τ4 has elapsed, verification circuit 2
When the processing is completed in step 4, a write signal W2 is applied and data is written from the collation circuit 24 to the shift register 23. At the same time, a gate signal G5 is applied to send a matching failure signal DIM to the counter 27. The inspection printed matter can be inspected using the count value of the counter 26 and the count value of the counter 27.

The time required for this test is at least the sum of the processing times of the A/D converter 30, the peak tester 31, and the pattern matching circuit U. , the time to check one bit of data is (τ1
+τ2+τ4).

For this reason, in order to shorten processing time and improve processing efficiency for practical use, A/D converter 3(), peak detector 3
1 and pattern matching circuit U are operated independently. That is, the next data is input during processing by the peak detector 31 and processed by the converter 3θ. After the processing in the peak detector 31 is completed, the pattern matching circuit U transfers the data processed in the IL A/D converter 3 (J) to the peak detection circuit 5.31. New data is entered at 30 and processed.

Such an operation is re-stretched by operating the circuit shown in FIG. 1O at the signal timing shown in FIG. 11.

In this case, if the sampling period is adjusted to the processing time τ2 of the peak detector 31, which takes the longest time, the foot can be inspected efficiently.

Prior to performing such a test, every circuit section except the counter is reset.

As described above, the present invention performs non-linear quantization processing on the image signal sampled from the printed matter to be inspected, and then integrates it within a predetermined saturation level range to detect features in the image. It is possible to perform highly efficient inspections with fewer errors than defect inspections using analog processing methods.

Further, since the characteristics of the printed matter are detected, the degree of defect can be accurately detected even for picture printed matter by comparing the reference data taken from the reference printed matter with the inspection data taken from the inspected printed matter.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the defect detection operation of pattern printed matter according to the present invention, FIG. 2 is a diagram showing the characteristics of differential quantization in the flowchart of FIG. 1, and FIGS.
) shows a comparison between the image signal and the integral value of the quantized output according to the characteristics shown in Fig. 2, and Fig. 4 shows a pattern matching method using the binarized peak detection output extracted by the method shown in Fig. 3. Explanatory diagrams of FIGS. 5(a) to (d) and FIG. 6(a)
~((1) is a diagram showing more specifically the signal processing shown in FIGS. 2 and 3, FIG. 7 is a diagram showing a circuit that operates according to the characteristics of FIG. 2, and FIG. 8 (a), (1
)) is a diagram showing a circuit that operates according to the characteristics shown in Figure 3 and its operation, Figure 9 is a diagram showing a circuit that performs pattern matching using the output of the circuit in Figure 8, and Figure 1O is a diagram showing the circuit operating according to the characteristics shown in Figure 7. A block diagram showing the configuration of the device of the present invention formed by combining the circuits shown in FIGS. It is. sn, 5n-1”・sampling value, Fn I Fn
-1''' differential quantized signal (quinarized data), En, capital -
1...Peak detection signal.

Claims (1)

[Claims] 1. A sample and hold circuit that samples an image signal extracted by optically scanning the surface of an object to be inspected and sequentially extracts a signal corresponding to each pixel in a series of pixels, and this sample and hold circuit. A digital signal is formed by obtaining the output of the circuit and non-linearly quantizing the signal corresponding to the difference between adjacent pixels in the series of pixels so as to thicken the small amplitude part and suppress the large width part. '/D conversion circuit,
A peak detection circuit that obtains the output of this '/D conversion circuit, integrates it within a predetermined saturation level range, and then determines the level, thereby producing a binarized output at the pixels showing the maximum value and minimum value in the image signal. For example, a spot-like defect determination device is configured to determine defects on the surface of an object to be inspected based on the binary output. 2. In the apparatus according to claim 1, the peak detection circuit includes a spot-like defect determination device that shifts the integral signal to a saturation level when the z(ii'j output power is generated). γe. 3. A sample and hold circuit that samples the image signal extracted by optically scanning the surface of the object to be inspected and sequentially extracts a signal corresponding to each pixel in a series of pixels, and the output of this sample and hold circuit. an A/D conversion circuit that non-linearly quantizes a signal corresponding to the difference between adjacent pixels in the series of pixels so as to enlarge small amplitude portions and suppress large black width portions to form a digital signal; ,
By obtaining the output of this A/D conversion circuit, integrating it within a predetermined saturation level range, and then determining the level, peak detection generates a binarized output at pixels showing the maximum value and minimum value in the image signal. circuit, and a first circuit for storing binarized data given from the peak detection circuit by inspecting the reference printed matter.
and a second circuit that stores the binarized data given from the peak detection circuit through the inspection of the printed matter to be inspected. Equipped with a matching circuit that produces a corresponding output,
A spot defect determination device that determines defects in patterned printed matter based on the output of this verification circuit. 4. In the device according to claim 3, when the collation circuit collates the stored data of the first and second circuits, the data of a pixel having one stored data and the other stored data A spot-like defect determination device that compares data of a corresponding pixel and pixels in its vicinity.