JPS59200595A - Contention prevention system of subscriber attended control type electronic switchboard - Google Patents
Contention prevention system of subscriber attended control type electronic switchboardInfo
- Publication number
- JPS59200595A JPS59200595A JP7328283A JP7328283A JPS59200595A JP S59200595 A JPS59200595 A JP S59200595A JP 7328283 A JP7328283 A JP 7328283A JP 7328283 A JP7328283 A JP 7328283A JP S59200595 A JPS59200595 A JP S59200595A
- Authority
- JP
- Japan
- Prior art keywords
- control
- processor
- flag
- contention
- communication path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54575—Software application
- H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は分散制御式電子交換機における競合防止方式に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a competition prevention method in a distributed control electronic exchange.
従来、この棹の電子交換機における競合防止は、各プロ
セッサから共通にアクセス可能な競合防止装置とこの競
合防止装置内に競合防止フラグを格納するメモリを設け
、通話路網に収容された端末機器からの処理要求が発生
した時点でその呼に関連するすべての端末機器の競合防
止フラグをプロセッサのテストアンドセット手段によシ
セットし、他の端末機器からの処理要求を禁止すること
により行表われている。しかしながら、このようにして
端末機器からの処理要求に対して競合防止を成すことは
、各プロセッサより共通アクセス可能な専用の競合防止
装置を配設し、さらに各プロセッサと競合防止装置との
間に特別の通信手段を設ける必要があシシステム構成の
複雑化を招く。本発明の目的は、このような問題点を解
消することができる分散制御式電子交換機の競合防止方
式を提供することにある。Conventionally, conflict prevention in electronic exchanges has been achieved by providing a conflict prevention device that can be accessed in common from each processor and a memory that stores a conflict prevention flag within this conflict prevention device. This is done by setting the contention prevention flags of all terminal equipment related to the call using the test and set means of the processor when a processing request for the call occurs, and prohibiting processing requests from other terminal equipment. There is. However, in order to prevent conflicts with respect to processing requests from terminal equipment in this way, it is necessary to provide a dedicated conflict prevention device that can be commonly accessed by each processor, and also to create a space between each processor and the conflict prevention device. It is necessary to provide a special communication means, which complicates the system configuration. SUMMARY OF THE INVENTION An object of the present invention is to provide a competition prevention method for a distributed control type electronic exchange that can eliminate such problems.
本発明は通話路網に接続された機器に外部機器から到来
する制御信号を検出する制御手段と前記通話路網に接続
された機器から外部機器へ制御信号を送出する制一手段
とを有する信号制御プロセッサを予め定めた前記通話路
網に接続された機器群に対応させて設け、且つ前記通話
路網の接続制御を行なう接続制御プロセッサを少なくと
も1つ設け、前記信号制御プロセッサと前記接続制御プ
ロセッサとこれらのプロセッサ間の情報転送を行なう伝
送手段とを設けて変換システムの制御を行なう分散制御
式電子交換機における競合防止方式であって、前記信号
制御プロセッサ毎にそれぞれが制御する前記通話路網収
容の外部機器に対応する領域に競合防止フラグを格納す
るメモリと接続状態にある前記外部機器の内状態変化の
処理を優先する外部機器であることを表示する中心端末
フラグを格納するメモリとを設け、且つ前記競合防止フ
ラグメモリへの競合防止フラグ設定を行なう手段を前記
接続料(財)プロセッサに設け、前記複数の外部機器か
らの処理要求に優先順位を与えて処理することを特徴と
する。The present invention provides a signal control device having a control means for detecting a control signal arriving from an external device to a device connected to a communication path network, and a control means for sending a control signal from the device connected to the communication path network to the external device. A control processor is provided corresponding to a predetermined group of devices connected to the communication path network, and at least one connection control processor is provided for controlling connection of the communication path network, and the signal control processor and the connection control processor are provided. and a transmission means for transferring information between these processors to control a conversion system. A memory for storing a conflict prevention flag in an area corresponding to the external device and a memory for storing a central terminal flag indicating that the external device is an external device that gives priority to processing of internal state changes of the external device in a connected state. and a means for setting a conflict prevention flag in the conflict prevention flag memory is provided in the connection fee (goods) processor, and processing requests from the plurality of external devices are given priority and processed.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
本発明による競合防止方式の一実施例を示す図を参照す
ると、通話路網60には加入者回路401〜40n、
・・・・・・、4n1〜4nnおよびトランク回路50
1〜50−e、・・・・・・、5n1〜5n、dが接続
され、これらの回路にはυ口人者回線および中継&!を
介して端末機器(図示省略)が接続される。Referring to the diagram showing an embodiment of the contention prevention method according to the present invention, the communication path network 60 includes subscriber circuits 401 to 40n,
......, 4n1 to 4nn and trunk circuit 50
1 to 50-e, . A terminal device (not shown) is connected via the terminal.
加入者回路401〜40n、・・・・・・、4n1〜4
nnおよびトランク回路501〜50.#、・・・・・
・、5n1〜5 n 、13はそれぞれ群分けされて信
号制御プロセッサ201〜20mに接続されている。ま
た、少なくとも1つの通話路網60は信号制御プロセッ
サ201〜20mに接続されている。信号制御プロセッ
サ201〜20mのそれぞれは加入者回路およびトラン
ク回路に入出力する信号の処理と通話路網の選択を成す
。さらに、信号制御プロセッサ201〜20mのそれぞ
れは競合防止フラグメモリ、211〜21mと中心端末
フラグメモリ221〜22mとを有する。これらメモリ
は各プロセッサに内蔵あるいは外部接続される。競合防
止フラグメモリ211〜21mおよび中心端末フラグメ
モリ221〜22mのそれぞれは端末機器対応つまシ端
末機器に接続される加入者回路401〜40n、)ラン
ク回路501〜50.13また加入者回路4n1〜4n
n、)ランク回路5nl〜5n−e対応にフラグ格納領
域を有する。信号制御プロセッサ201〜20mにはバ
ス30を介して接続制御プロセッサ101〜10!がい
ずれの信号制御プロセッサとも信号送受可能に接続され
ている。ここで、信号制御プロセッサ201〜20m5
−
は機能分散配置形態を成し、接続制御プロセッサ101
〜IOAは空状態にあるものが信号制御プ散制御式電子
交換機において、加入者回路401と加入者回路4nl
とにそれぞれ接続されている端末機器間が通話状態にあ
り、今加入省回路401に接続された端末機器に新たな
状態変化が生じた場合、信号制御プロセッサ201がそ
の状態変化を検出すると、競合防上フラグメモリ211
の対応領域に例えば接続開開1プ目セッサ101のテス
トアンドセット手段により競合防止フラグをセットする
。このフラグセット成功の場合は、今接続状態にある端
末機器のいずれが中心つまシ以後の処理の優先を受けら
れるかを表示するための中心端末フラグメモリ221の
内容を読出しその読出し情報を付加して接続制御プロセ
ッサ101に状態変化検出信号をバス30を介して送出
する。接続制御プロセッサ101は今回状態変化を検出
された加入者回路401接続の端末機器が中心端末6−
であるか否かを識別し、中心端末である場合は、その処
理を他の処理に比較して優先するものとして交換処理を
実行する。一方、この端末機器が中心端末でない場合は
、この端末機器に接続されている他の端末機器の中で中
心となる加入者回路4n1接続の端末機器に対する競合
防止フラグメモIJ 21 mの対応領域に接続制御プ
ロセッサ101のテストアンドセット手段にて競合防止
フラグをセットし、信号制隣プロセッサ20mに間合せ
を行なう。このセット成功の場合は中心となる優先端末
機器(加入者回路4nl接続)が処理未実行中として今
回の状態変化端末機器(加入者回路401接続)の処理
を実行する。このとき、端末機器(4n1接続)に対す
る競合防止フラグメモリ21mの対応領域がセットされ
るため、以後通話路網60により接続されている両端末
機器からの状態変化検出は排除される。また、中心とな
るべき端末機器(4n1接続)の競合防止フラグメモI
J 21 mの対応領域へのテストアンドセットの結果
が不成功の場合には、優先端末処理実行中とじて今回状
態変化のあった端末機器の状態変化検出は排除される。Subscriber circuits 401 to 40n, 4n1 to 4
nn and trunk circuits 501-50. #、・・・・・・
, 5n1 to 5n, and 13 are divided into groups and connected to the signal control processors 201 to 20m, respectively. Also, at least one communication path network 60 is connected to the signal control processors 201-20m. Each of the signal control processors 201 to 20m processes signals input to and output from subscriber circuits and trunk circuits, and selects a communication path network. Furthermore, each of the signal control processors 201-20m has a conflict prevention flag memory, 211-21m, and a central terminal flag memory 221-22m. These memories are built into each processor or connected externally. Each of the contention prevention flag memories 211-21m and the central terminal flag memories 221-22m corresponds to a terminal device. 4n
n,) has flag storage areas corresponding to rank circuits 5nl to 5ne. The control processors 101-10! are connected to the signal control processors 201-20m via the bus 30! is connected to any signal control processor so that it can send and receive signals. Here, the signal control processors 201 to 20m5
- constitutes a functionally distributed arrangement form, and the connection control processor 101
~The IOA in the empty state is the subscriber circuit 401 and the subscriber circuit 4nl in the signal-controlled distributed electronic exchange.
If the terminal devices connected to the respective terminal devices are in a communication state and a new state change occurs in the terminal device currently connected to the joining saving circuit 401, when the signal control processor 201 detects the state change, the conflicting Defense flag memory 211
For example, a conflict prevention flag is set in the corresponding area by the test and set means of the connection opening/opening first processor 101. If this flag setting is successful, the contents of the central terminal flag memory 221 for displaying which of the currently connected terminal devices can receive priority for processing after the central terminal is read out and the read information is added. and sends a state change detection signal to the connection control processor 101 via the bus 30. The connection control processor 101 identifies whether the terminal device connected to the subscriber circuit 401 whose status change has been detected this time is the central terminal 6-, and if it is the central terminal, compares its processing with other processing. The exchange process is executed with priority given to the On the other hand, if this terminal device is not the central terminal, connect to the corresponding area of the conflict prevention flag memo IJ 21 m for the terminal device connected to the main subscriber circuit 4n1 among other terminal devices connected to this terminal device. A competition prevention flag is set by the test and set means of the control processor 101, and the timing is adjusted to the signal-based neighboring processor 20m. If this set is successful, the main priority terminal device (connected to the subscriber circuit 4nl) assumes that the process is not yet executed, and executes the process for the terminal device whose status has changed this time (connected to the subscriber circuit 401). At this time, since the corresponding area of the conflict prevention flag memory 21m for the terminal device (4n1 connection) is set, the state change detection from both terminal devices connected by the communication path network 60 is excluded from now on. In addition, conflict prevention flag memo I for the terminal device (4n1 connection) that should be the center
If the result of the test and set for the corresponding area of J 21 m is unsuccessful, detection of the state change of the terminal device whose state has changed this time is excluded as the priority terminal processing is being executed.
なお、信号制御プロセッサ201において状態変化端末
機器に対応する競合防止フラグメモリ211をテストア
ンドセットにてチェックした結果不成功の場合にも該当
端末処理実行中として今回の状態変化検出が排除される
、以上説明したように本発明によれば、信号制御プロセ
ッサに競合防止フラグの格納メモリと中心端末フラグの
格納メモリを設け、且つ接続制御プロセッサに競合防止
フラグのメモリにバスを介してテストアンドセットを行
なう手段を設けることにより、個別配置の専用競合防止
装置を不要としてシステム構成の簡略化を図ることがで
きる。Note that even if the signal control processor 201 checks the contention prevention flag memory 211 corresponding to the state-changing terminal device by test and set and is unsuccessful, the current state change detection is excluded as the corresponding terminal processing is being executed. As explained above, according to the present invention, the signal control processor is provided with a storage memory for conflict prevention flags and a storage memory for central terminal flags, and the connection control processor is provided with a memory for conflict prevention flags that is tested and set via a bus. By providing a means for performing this, it is possible to simplify the system configuration by eliminating the need for a dedicated conflict prevention device that is individually arranged.
図は本発明の一実施例を示す構成図である。
101、IOJ・・・・・−接続制御プロセッサ、 2
01゜20m・・・・・・信号制御プロセッサ、211
.21m・・・・・・・・・競合防止フラグメモリ、2
21.22m・・・中心端末フラグメモリ、30・・−
・・・バス、401゜40n、4nl、4nn・・・・
・・加入者回路、5o1゜50A、5n 1,5n−8
=−−・トランク回路、6゜・・・・・・通話路網。
9−The figure is a configuration diagram showing an embodiment of the present invention. 101, IOJ...-Connection control processor, 2
01゜20m...Signal control processor, 211
.. 21m・・・・・・Conflict prevention flag memory, 2
21.22m...Central terminal flag memory, 30...-
... bus, 401°40n, 4nl, 4nn...
...Subscriber circuit, 5o1゜50A, 5n 1, 5n-8
=-- Trunk circuit, 6°... Call path network. 9-
Claims (1)
信号を検出する制御手段と前記通話路網に接続されfc
機器から外部機器へ制御信号を送出する制御手段とを有
する信号制御プロセッサを予め定めた前記通話路網に接
続された機器群に対応させて設け、且つ前記通話路網の
接続制御を行なう接続制御プロセッサを少なくとも1つ
設け、前記信号側倒プロセッサと前記接続制御プロセッ
サとこれらのプロセッサ間の情報転送を行なう伝送手段
とを設けて父換システムの制@lt−行なう分散制御式
電子父換1張において、前記信号制御プロセッサ毎にそ
れぞれが制御する前記通話路網収容の外部機器に対応す
る領域に競合防止フラグを格納するメモリと接続状態に
ある前記外部機器の内状態変化の処理を外部機器である
ことを表示する中心端末フラグを格納するメモリとを設
け、且つ前記競合防止フラグメモリへの競合防止フラグ
設定を行なう手段を前記接続制御プロセッサに設け、前
記複数の外部機器からの処理要求に優先順位を与えて処
理すること全特徴とする分散制御式電子交換機の競合防
止方式。a control means for detecting a control signal arriving from an external device to a device connected to the communication path network; and an fc connected to the communication path network.
A signal control processor having a control means for sending a control signal from a device to an external device is provided corresponding to a predetermined group of devices connected to the communication path network, and connection control is performed to control the connection of the communication path network. A distributed control type electronic father exchange system is provided in which at least one processor is provided, the signal overturning processor, the connection control processor, and a transmission means for transferring information between these processors are provided to control the father exchange system. In the step, an external device processes a change in the state of the external device connected to a memory storing a conflict prevention flag in an area corresponding to the external device accommodating the communication path network controlled by each of the signal control processors. a memory for storing a central terminal flag indicating that there is a central terminal flag, and a means for setting a conflict prevention flag in the conflict prevention flag memory is provided in the connection control processor, giving priority to processing requests from the plurality of external devices. A competition prevention method for distributed control electronic switching equipment that is characterized by processing by assigning rankings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7328283A JPS59200595A (en) | 1983-04-26 | 1983-04-26 | Contention prevention system of subscriber attended control type electronic switchboard |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7328283A JPS59200595A (en) | 1983-04-26 | 1983-04-26 | Contention prevention system of subscriber attended control type electronic switchboard |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59200595A true JPS59200595A (en) | 1984-11-13 |
Family
ID=13513629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7328283A Pending JPS59200595A (en) | 1983-04-26 | 1983-04-26 | Contention prevention system of subscriber attended control type electronic switchboard |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59200595A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6331298A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Competition preventing system for multiprocessor |
JPS6331297A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Competition preventing system for multiprocessor |
JP6408701B1 (en) * | 2016-12-28 | 2018-10-17 | 株式会社小松製作所 | Work vehicle and position adjustment method of movable part of work vehicle |
-
1983
- 1983-04-26 JP JP7328283A patent/JPS59200595A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6331298A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Competition preventing system for multiprocessor |
JPS6331297A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Competition preventing system for multiprocessor |
JP6408701B1 (en) * | 2016-12-28 | 2018-10-17 | 株式会社小松製作所 | Work vehicle and position adjustment method of movable part of work vehicle |
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