JPS5919642B2 - digital limiter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration of a digital limiter used in a digital pushbutton receiver.

An example of a circuit configuration of a digital limiter used in a conventional digital push button receiver is shown in FIG.

However, this circuit configuration has drawbacks in IJ transmitter operation when the amplitude of the input signal is close to the IJ transmitter's threshold and its frequency is the sampling frequency divided by an integer. It will be done.

The circuit configuration shown in FIG. 1 uses the input sample value sequence IN as binary data via the input terminal 8 as the A input of the full adder 1, and stores the sign of the result of addition by the full adder 1. (D type) The positive and negative limiter output values of the flip-flop 2 are controlled, and this IJ limiter output value is transferred to the full adder 1.
It is configured to feed back to the B input of.

That is, one of the Nant gates 5 and 6 is selected by the output of the flip-flop 20, and the limiter threshold value, ! Either of the outputs from the shift registers 3 and 4 in which o+(>0) and to-(--to") are stored is taken out via the Nantes gate 7.

The principle of operation of the circuit configuration shown in FIG. 1 is as follows.

That is, the input sample value at t=nt (T is the sample period) is x (nT), and the output value of the limiter is y (nT).
Then it works according to the following rules:

If x(nT)+y(nT)≧0, y((n+1)T)=,g.

If +x(nT)+y(nT)<0, then y((n+1)T)-/:.

- Therefore, y(nT) as a limiter output follows the input sample value x(nT) as shown in FIG.

This figure 2 shows a case where the sampling frequency is considerably higher than the signal frequency, but if the signal frequency becomes higher to a certain extent and there is a relationship between the sampling frequency and the sampling frequency, as shown in figure 1. Depending on the circuit configuration, the limiter may operate in an ambiguous and uncertain manner.

For example, the frequency of the input signal is 1/1 of the sampling frequency
5, and the level approaches the threshold of the limiter, depending on the phase relationship, the signal amplitude definitely exceeds the threshold as shown in Figure 3. There are cases in which the device operates as shown in a, and cases in which it does not operate as shown in FIG.

In fact, when observing the limiter output when such an input signal is applied to the limiter for a long time, it is found that since there is fluctuation in the phase relationship between the sampling frequency and the signal frequency,
J Mitter output may be output intermittently or stopped.

This means that the limiter operation is operating indeterminately with some ambiguity.

Such inconveniences actually occur in practical digital push-button receivers.

For the sampling frequency of 8 KHz, the lower limit band (-2%) of the 1633 Hz multi-frequency signal is exactly 1600 Hz, as shown in Figure 3a.

This is because case b applies.

Therefore, if this 1600 Hz frequency is input at a level near the limiter threshold level, the IJ mitter will perform an uncertain operation.

This causes a large uncertain region in the 1633 Hz emotional band level characteristics, which is not a desirable phenomenon.

In addition, since the frequency of 1333 Hz, which is equal to 8 kHz, is within the band of the channel 1336 Hz, the above-mentioned phenomenon may occur.

SUMMARY OF THE INVENTION An object of the present invention is to obtain a circuit configuration of a digital limiter with a small uncertain operating region even if a signal frequency and a sampling frequency have a special relationship.

To this end, the invention detects the sign of the input signal and
Positive depending on the positive or negative of this detected sign.

While controlling and outputting the negative limiter output value to obtain a rectangular wave output with a duty factor of 50% that follows the input signal frequency, the input signal is full-wave rectified and the obtained output is compared with the threshold level, The present invention is characterized by a configuration in which the amplitude of the input signal is detected by the OR output of the multi-point samples of the comparison output, and the rectangular wave output is gate-controlled by this detection output.

The present invention will be explained below with reference to FIGS. 4 to 6.

FIG. 4 shows a specific circuit configuration of the present invention, and FIG.
, b are diagrams showing the timing of input/output signals in the main part.

The circuit configuration shown in Fig. 4 is roughly divided into a circuit section A for determining the absolute value of an input signal, a circuit section B for comparing the determined absolute value with a threshold value, a shift register circuit section C for latching the comparison result, and a positive and negative The shift register circuit section C is configured to include an output control circuit section that selects and outputs one of the outputs of the registers storing the limiter output values in consideration of the output from the shift register circuit section C.

The operation of the circuit shown in FIG. 4 will be explained with reference to FIGS. 5a and 5b. The sample data that constitutes the input signal IN, for example, has a 16-bit configuration in two's complement format, and the sample data has a 16-bit configuration in the format shown in the figure. The clock signal CLK is sequentially stored in the shift register 10 as a shift clock.

In this storage, the LSB side is assumed to be the first, but the MSB
At the time when the sample data is stored, the sign bit of the sample data is latched into the flip-flop 2 by the timing signal BIT1.

The set output and reset output of this flip-flop 2 are used to select and control the NAND GO) 15 and 16, so that if the sample data is positive, the sample data is passed through the NAND GO (16 and 17), and if it is negative, the sample data is passed through the NAND GO) 16 and 17. The signal is converted into a code and is inputted to the circuit section B as an absolute value output A OUT via a Nandt gate 15.degree. 17.

For code conversion when the sample data is negative, the clock signal CLK and signal BIT1 via inverters 11 and 12 are used as clock input and reset input (J-
K) Performed by flip-flop 13 and exclusive OR gate 14.

After the flip-flop 13 detects the leading “■” state from the data in the shift register 10, the flip-flop 13 transfers the data to the shift register 10
The polarity of the data outputted from the gate is inverted by the exclusive OR gate 14.

The absolute value output AOUT of the sample data via the Nantes gate 17 is added to the threshold value (negative value in two's complement format) from the shift register 18 in the adder 1, and it is determined whether or not it exceeds the threshold value. Ru.

The determination result is latched in the shift register 19 by the shift signal SET, but the capacity of the shift register 19 (in the example shown, 8 samples per data) depends on the frequency of the multifrequency signal.

All the set outputs of the flip-flops constituting the shift register 19 are ORed by an OR gate 20, and based on the existence of the OR gate 20's OR gate 20, it is determined that the amplitude value of the input sine wave signal IN is greater than a threshold value. It is something.

On the other hand, the set output and reset output of the flip-flop 2 selectively control either the Nant gates 5 or 6, and either of the limiter output values of the shift registers 3 and 4 is taken out via the Nant gate 7. Therefore, if the limiter output value via the Nandt gate 7 is gate-controlled by the AND gate 21 using the above-mentioned OR output, the desired limiter output OUT can be obtained.

FIG. 6 is a waveform diagram of input/output data in an example of the digital limiter of the present invention, in which the limiter output is delayed by 16 bits and output.

When using multiple digital limiters according to the present invention, each (D type) flip-flop constituting the shift register 19 may be made as long as the number of multiplexed ones.

For example, if the number of multiplexed circuits of the push button receiver is 4, for high group,
It is sufficient to consider multiplexing for the low group and replace it with an 8-bit shift register.

As described in detail above, according to the present invention, by full-wave rectifying the input signal and detecting the amplitude, the signal frequency is an integer fraction of the sampling frequency, and the level is at the threshold level. Even when the amplitude is close to , if the amplitude truly exceeds the threshold, there is a high probability that there will be a sample exceeding the threshold in either the positive or negative half cycle, so amplitude detection is reliable. This has the effect of reducing the ambiguous operation region of the limiter.

[Brief explanation of drawings]

FIG. 1 is a specific circuit configuration diagram of a conventional digital IJ transmitter, FIGS. 2 and 3 a and b are diagrams illustrating the operation of a conventional digital limiter, and FIG. A specific circuit configuration diagram, Fig. 5a
yb is a diagram showing the operation timing of input/output signals in the main part shown in FIG. 4, and FIG. 6 is an explanatory diagram of the operation of the digital limiter according to the present invention. 1...Full adder, 2,13...Flip-flop,
3.4,18...Shift register for storing threshold value,
10.19...Shift register.

Claims (1)

[Claims] A digital limiter that compares the value of a data input configured in 12's complement format with a threshold value, and when the comparison shows that the data input exceeds the threshold value, limits the data input amplitude and outputs a constant output. , means for detecting the sign of the data input signal; means for selectively outputting either a predetermined positive or negative limiter output value depending on whether the detected sign is positive or negative; means for obtaining an absolute value, means for comparing the absolute value output with a threshold value, means for successively storing a plurality of comparison results on a time axis, and a logical OR output of the plurality of stored results. A digital limiter comprising means for gate-controlling the pressure and a selected output of a negative limiter output value.