JPS5919511B2 - Two-channel simultaneous playback system in television receivers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reproduction system for a television receiver in which two channels of television broadcast images are simultaneously reproduced on one cathode ray tube.

A television receiver with such a function can simultaneously watch two types of programs, one of which provides the minimum amount of information necessary to understand from just the image, such as a music program and a weather forecast, or a drama and sports. It is convenient for etc. The present invention takes advantage of the fact that the difference in line period between channels of actual television broadcasting is less than 1/106 of the reference period.

When playing two types of images simultaneously, the present invention doubles the horizontal and vertical deflection period of the cathode ray tube, reduces the size of each document to about 1/4 of that when playing one type of image, and By reducing the number of scanning lines to 1/4 of the normal number, it is easy to switch between one type of video and two types of video playback, and the additional circuitry required to play two types of video simultaneously is minimized, making it more convenient for general use. This made it possible to manufacture the product within the price range of a home television receiver. FIG. 1 shows a block diagram of a television receiver according to the invention.

The figure shows a case where two channels of television broadcast are played back simultaneously. If one is used for video reproduction from a surveillance camera or the like, 2, 3A, and 6A in the figure may be omitted, the antenna 1 may be directly connected to 3, and the output of the camera may be directly connected to 9 and 4A. In this case, it is necessary to use the synchronization signal of the reception channel for camera synchronization. Now, in the same figure, 1 is the antenna, 2 is the antenna reception signal splitter, and 3 is the R
F amplification - IF amplification - video detection circuit (hereinafter simply referred to as RF circuit), 4 is a synchronization signal separation circuit, 5 is a horizontal synchronization signal separation circuit, 11 is a vertical synchronization signal separation circuit, 6 is an AGC circuit, 3A, 4A ．． 5A, 11A, 6A are 3, 4, respectively.
It has the same functions as 5, 11, and 6. 3,3A0) The RF stage has a receiving channel selection function known as a so-called tuner.

Recently, an electrical selection method for reception channels has been developed, and other parts have been integrated into ICs, and the above circuit group can be easily made into a unit, and it is extremely easy to implement this into two sets of receivers. It became. Note that 4B and 5B connected to the block 10 in the figure also have the same functions as 4 and 5. 5
and horizontal synchronization signal (hereinafter referred to as H-S) separated by 5A
ync) is compared in phase by a phase discrimination circuit 7, and a clock pulse oscillation circuit 8 is detected based on the phase error voltage.
control the oscillation frequency.

Reference numeral 9 denotes a delay circuit for delaying the video signal for one horizontal period (1H) as a reference, and it is practical to construct it using a CCD.

The video signal is transferred within the CCD by the 8 clock pulses, and the delay time between the input and output of the CCD is controlled by the period of the clock pulses.
Sync is in phase with H-Sync included in the output of 3.

10 is a buffer amplifier for the output of the CCD.

The outputs of 3 and 10 are supplied to AGC circuits 6 and 6A, and at the same time, are supplied to electronic switch 12.

Further, the output of No. 3 is led to the SIF-audio detection amplification circuit 27, where the audio signal is separated and amplified. Electronic switch 12
is supplied with two sets of H-Sync, one from 5 and one from the output of 10 separated by 4B-5B;
- Switch the video signals supplied from 3 and 10 every Syuc.

That is, the following 3 video signals are switched by H-Sync 5, and the 10 video signals are switched by the next 5B0) H-Sync. The video signals, which are switched line by line in this way, pass through the color difference signal separation and demodulation circuit 13 and the luminance signal separation and amplification circuit 14, are added by 15, and are guided to the cathode ray tube. As described above, since the two video signals are switched by H-Syncs separated from each other, even if there is a slight phase difference between H-Syncs 3 and 10, each burst The signal is completely switched and supplied to the circuit 13, and stable demodulation of the color difference signal is performed. The phases of the burst signals switched line by line in this way generally do not match.

Therefore, the phase of the subcarrier generated in the circuit 13 becomes phase synchronized with the intermediate phase of the two burst signals.
Therefore, in order to obtain the correct hue, it is also necessary to switch the hue adjuster for each line. Reference numeral 16 in FIG. 1 indicates two sets of hue adjusters, which are also switched line by line by an electronic switch 12 and connected to the circuit 13. The maximum phase difference between the two burst signals is π.

In this case, since the phase of the subcarrier has a larger phase angle than the normal phase with respect to the primary color difference signal, each hue adjuster must also change the phase of the color difference signal. That is, the hue control width of each hue adjuster may be π.
If only one burst signal is transmitted to the circuit 13 and the subcarrier is phase-locked to it, the hue of the other color difference signal needs to be changed by a maximum of ±π by the hue adjuster, and the hue of the hue adjuster is A control width of 2π is required.
Such a hue adjuster has an inverting amplifier within itself, making the configuration and operation complicated. Note that in order to synchronize the phase of the subcarrier with the intermediate phase of the two burst signals, the phase error voltage obtained by comparing the phases of the subcarrier and the burst signal that is switched for each line in a phase discrimination circuit is set to a time constant of several H. The phase of the subcarrier oscillator may be controlled by time integration using a long smoothing circuit. In this case, it is safer to avoid the so-called ringing synchronization method in which the phase of the subcarrier oscillator is directly synchronized using a burst signal. Now, when playing two types of video simultaneously, the horizontal and vertical oscillation period is set to twice the normal period.

The switch SW in the figure is a switch for changing between one type of video playback mode (mode 1) and two types of video simultaneous playback mode (mode 2), and the state of mode 2 is shown in the figure. 17 is an H-Sync 1/2 frequency dividing circuit which divides the H-Sync output from 5 into 1/2.

18 is an AFC circuit, 19 is a horizontal oscillation circuit, 20 is a horizontal output circuit, 21 is a high voltage rectifier circuit, and 22 is a horizontal convergence circuit.
The integral time constants of both are switched to approximately twice the value of mode 1.

Therefore, the AFC circuit 18 controls the horizontal oscillation circuit so that the synchronizing pulse supplied once every 2H is located at the center of the retrace period of the horizontal oscillation whose period has been switched to 2H.
In this case, the overall horizontal amplitude and high pressure are set to mode 1.
The B voltage of the horizontal output circuit is switched to about 1/2 of that in mode 1 in order to keep it approximately the same as in the case of mode 1.

Further, 23 is output from the vertical synchronization signal separation circuit 11.
Divide Sync into 1/2. 24 is a vertical oscillation circuit, 2
5 is a vertical output circuit, 26 is a vertical convergence circuit, and the oscillation time constant 24 and the integration time constant 26 are switched to approximately twice the value in mode 1 in mode 2.

In this way, in mode 2, the vertical oscillation is synchronized with the synchronization pulse that is supplied once every two times, and the trace (Retrace)
race). As a result of the above, the screen reproduced on the cathode ray tube in the case of mode 2 is as shown in FIG. In FIG. 2, A and N are videos of channels selectively received by the RF circuit 3, B and BS+B4 are videos of channels selectively received by the RF circuit 3A,
The vertical black band in the center of the screen is horizontal blanking, A.
l5NsB and B,B. The horizontal black band between 15B4 is the vertical blanking.

As mentioned above, H-Sync of the two channels is connected to circuit 7.
, 8, and 9 are in phase. The horizontal oscillation period is twice the normal period,
In addition, since the images of each channel are switched and reproduced line by line, the images of the two channels are divided into left and right halves by horizontal blanking and reproduced. However, the -Sync of the two channels are not in phase, and the vertical oscillation, which has a period twice the normal one, is synchronized with and traced to the -Sync of the video selectively received by the RF circuit 3. , the image of the RF circuit 3 is divided into two parts, one field at a time, vertically, with vertical blanking as the border, and reproduced.
The vertical blanking of the 10 images of the other channels is at a different position from that of the 3 images, resulting in the appearance shown in the figure. For video No. 10 as well, B and BS+B'2 are reproduced one field at a time.

This N and BS+B4 part is an eyesore, so it is desirable to erase it, and the control function for this is also the electronic switch 1.
It can be included in 2. As mentioned above, parts A and B are reproduced by extracting one field from each channel's video, and both are switched and reproduced every l line, so the number of scanning lines is 1/4 of the normal number. . However, at the same time, the size of the playback screen is reduced to 1/4 of the normal size, so the roughness of the playback image is not as noticeable as on the left. As described above, according to the present invention, two types of video signals can be simultaneously reproduced on one cathode ray tube relatively easily. The oscillation period T of the general television receiver used in the present invention must be controlled as follows.

H T here.

=-Now, if we set ΔT=T-TO, ΔEn=Idan-± (the two components can be rewritten as V.2 as follows.

Unless the frequency of the clock pulse (f=1/T) is three times or more that of the subcarrier, the fidelity of the transferred video signal will be lost.

Therefore, it is necessary to satisfy n≧1024=2L0.

When n=1024, 0.031μSec<(T≦0.0
It becomes 93μSec. FIG. 6 shows a specific example of an oscillation circuit having voltage control characteristics expressed by equation (2) or (3).

Q1 and Q2 and Q3 and Q4 in FIG. 6 constitute differential amplifiers, respectively, and Q1-Q2-Q and C. -LO-RO
It oscillates through a closed loop consisting of a tuned circuit of Q, and the oscillation output is taken out from the collector of Q. The base of Q3 is the average value E of the Q output of RS-FF76 in FIG.

However, the average value of the Q output of RS-FF76 is 100 for the base of Q4. is applied. - E when 1e1 and E are in phase.

= EO = -2E, so the emitter current of Q and Q4 is 1
,,14 are equally I/2. Nowadays Q3, Q
If the equivalent mutual conductance of 4 is Gm', then 13-
1/2+Gm'ΔEle. ~However, I takes the direction shown in the figure as positive.

Then, the collector current 1,' of Q3 is ＾〒〜蟲′1龜〜 Here, R is the collector resistance of Q3 and Q4, and j×2 is Q3,
This is the reactance connected between the collector of Q4.

Now, if the base input signal voltage of Q1 is el, here is R
el is the common emitter resistance of Q, , Q2.

Z here again.

is the impedance of the tuned circuit connected between the collector of Q3 and the base of Q1, and R1 is the base resistance of Q1.
(7), (8), (From equation 9, ZO = RO + JXO, and the condition for the j part of the right side of the Qω equation to be zero, 2R
2》×22, △《If 1, then.

Then, the oscillation angular frequency w can be obtained from the equation as follows.

a? Rewriting , the oscillation period T is set aside as A, and substituting equation (6) for △ in the equation gives △E=E・△e, so (3), (from equation 3, this oscillation circuit can perform the desired control. It will have characteristics.

Actually, it is the standard oscillation frequency F of the oscillation circuit.

'F. = n times 1/TO at the same time, and a separate oscillation circuit that oscillates at the frequency of f'o-FO is provided to remove both beads.

The larger n is, the better the linearity of ΔT and △e is, but n〉
If it is set to 5, there will be no practical problem. C2=IOCI, R=
R1, RO《It is very practical to set R1, E=5V) If I=2mA, Gm' for n=5
=0.8×10-3, the emitter resistance of Q3 and Q4 is Re
2, then Gm'Σ1/Re2, so Re2=1
．． 25KΩ, and at this time the collector voltage of Q2 is -2
E-0.6-i-Re2=0.65V, which is maintained at a higher potential than the base voltage in FIG. 6, and the circuit operates normally.

The above description has been made assuming that the CCD constituting the delay circuit 9 is one system, but due to the relationship between the signal amplitude that can be transferred by the CCD and the S/N ratio, two systems of CCD with the same number of bits are actually provided, and the input side The signal is separated into Y (luminance signal) and C (color difference signal) and transferred to the husband's CCD, and the buffer amplifier 1
It is desirable to add these again at 0.

As described above, if the periods of el and E2 are the same and the phases are simply different, the output of the delay circuit 9 will correctly output two H -Syne is controlled to be in phase. However, in reality, the periods of el and E2 are generally slightly different, and the difference is about 1/106 at most.
(The standard stipulates that the horizontal period error is 1/107 or less of the standard period.) Figure 4-A shows the operating state of RS-FFT6 when the period of E2 is shorter than the period of el, and its behavior. This figure shows the second H-Sync2' which is controlled by the output and applied to the output of the delay circuit 9, where A is el, the mouth is the output of 0S73 triggered by el, and C is E2, 2nd is the Q output of RS-FF76, and E is E2'
It is.

The time axis of E is shown preceded by H. As shown in the figure, the period of E2' is disturbed at the point where θ changes from 1π to +π, but in other ranges E2' and C1 are controlled to be in phase. The video that is switched and reproduced line by line by the electronic switch 12 is, for example, the shaded area in the same figure, and in the part where the period of E2' is disturbed, there is a horizontal retrace line in the middle of the scanning line of the second video. Become something. 4th-
Fig. B shows the case where the period of E2 is longer than the period of e1, and each symbol corresponds to Fig. 4-A.

In this case, the period of E2' is disturbed at the point where θ changes from π to 1 π, and for example, the shaded part in the same figure is switched and played, and the first and second images are changed at the part where the period of E2' is disturbed. They become embedded in each other. However, such chances occur less than once every 106 scan lines, or less than once every approximately 60 seconds.
Moreover, the period during which the period of E2' is disturbed can be set to about 3H, and it is visually felt as if a minute noise has been mixed in. The fact that the phase of E2' is periodically disturbed as described above indicates that the integrated value of the periodic error of e1 and E2 over a long period of time remains as it is in the output of the delay circuit 9, ie, 10.

That is, the position in FIG. 2B where the second video is played moves very slightly upward or downward at a rate of less than one field every approximately 262 minutes. (2) Regarding the electronic switch (circuits 12, 17, 23) FIG. 7 shows a specific example of the circuit of the electronic switch 12.

This circuit also includes a 1/2 frequency dividing function for H-Sync and -Sync, and a function for erasing the reproduced video of the portions A' and B1'+B,' in FIG. In FIG. 7, mode 2 is entered when the switch SW is in the position shown.

H-Syncel output from the horizontal synchronizing signal separation circuit 5 is applied to the terminal 1201 to trigger the JK type flip-flop (JK-FF) 1201.

The Q output is differentially amplified by the transistor circuit 1202 and divided into 1/2 by the H-Syncpu-1see
1′. In FIG. 8, A shows C1, mouth shows the Q output of 1201, and C shows E,'. The inversion period is 1 due to e1'
αHO) 0S1203, which is shorter than H, is triggered, and the negative pulse generated at this return triggers the second 0S1
204 is triggered.

The inversion period of 0S1204 is βH.

Figure 8 2 shows the output of 0S-1203, and E shows the output of 0S-120.
The output of 4 is shown. α and β are set in the relationship β=2(1−α), for example, α=0.9 and β−0.2. On the other hand, H-Sync2d of the other video, which is controlled to have almost the same phase as E, is applied to the terminal 1205, and this is applied to the inverter 1.
206, the polarity is inverted to positive. FIG. 8C shows E2d which has become positive polarity. Only E2d that arrives during the positive period of the output of 0S 1204 passes through the NAND gate 1207 and appears at its output as a negative polarity pulse E2d'.

RS-FFl2O8 is set by E,' and E2d
', and its Q output becomes as shown in FIG. 1208-Q. Positive period transistor 12
09 becomes ON, and transmits the first video signal from the RF circuit 3 applied to its collector to the output terminal 1213.

At the same time, transistor 1210 also goes ON, connecting first hue regulator 1214 to output terminal 1216. 120
8-Q is negative, that is, 1208-σ is positive, transistor 1
211 becomes ON and transmits the second video signal from 10 applied to its collector to the output terminal 1213.

At the same time, transistor 1212 also becomes ON, connecting second hue adjuster 1215 to output terminal 1216. terminal 1
213 is connected to the video input terminals 13 and 14, and a terminal 1216 is connected to the hue adjustment input terminal 16. Also, e1' and E
2d' is inverted and amplified by a transistor 1217, delayed by about 5 μSec by a delay reduction circuit 1218, and then guided to the circuit 13 as a burst sampling pulse.

As described above, the first and second video signals each have their own H
- circuit 13 switched line by line by Syne;
.
The pulse is delayed by about 5 μSec from nc, and the color difference components of each image are normally demodulated by the circuit 13, and the luminance components are also normally amplified by the circuit 14.

e1', which is obtained by dividing the H-Sync of the first video signal by 1/2
At this time, AF is sent from terminal 1219 as a horizontal oscillation synchronization signal.
C circuit 18. e1' at the center of the retrace period of horizontal oscillation whose period is set to 2H by the control action of the AFC circuit.
The first image is played on the left half of the cathode ray tube, and the second image is played on the right half of the cathode ray tube, resulting in the screen arrangement shown in FIG. In the above Mode 2 state, the input potential of the inverter 1220 is high, the output potential thereof is low, and the transistor 1221 is kept at 0FF.

Therefore, the first H-Sync applied to the terminal 1200
l is blocked from terminal 1219. Further, since the output of 1220 is connected to one input terminal of NAND 1222, the output potential of 1222 is kept high in this state and has no effect on RS-FFl2O8. Now S
When W is switched to the opposite position from that shown, the inverter 122
0 input is grounded, its output potential becomes high, transistor 1221 becomes 0N, and the first H-Sync
, to the terminal 1219. At the same time, since K of JK-FFl2Ol is grounded, its Q potential is clamped to high. Since the inputs of the NAND 1222 are the output of the inverter 1220 and the Q output of JK-FFl2Ol, at this time, both of the two inputs of the NAND 1222 become high and its output becomes low. At this time, the output of NAND 1222 is diode 12
1208 is clamped to the set state. That is, its Q output is clamped high and transistor 120
9 and 1210 are clamped to ON, the first video signal is continuously supplied to the circuits 13 and 14, and the first hue adjuster is continuously connected to the circuit 13. Also JK-F
With Fl2Ol's K being grounded, its Q output is clamped high, and thereafter transistor 1202 does not output pulse E,'.

Therefore, 0S1203-1204 are not triggered and 12
The output of 04 is held low and the NAND gate 1207 with this as one input no longer passes the H-Sync of the second video provided by 1205-1206.

Therefore, the input pulse to transistor 1217 is only e1 which passes through transistor 1221, and the burst extraction pulse is also switched to only a pulse delayed by about 5 μSec. That is, by switching the SW to a position opposite to that shown in the figure, mode 1 is applied and the first video is continuously reproduced.
Next, the terminal 1224 receives the first image v-Sy from the circuit 11.
nce3 is supplied.

In mode 2, both JK and JK of JK-FF1225 are at high level, so this is triggered by E3, and its Q output is differentially inverted and amplified by a transistor circuit 1226 and sent to a terminal 1227 as a negative polarity whose frequency is divided by 2. sexual v-
Generates SyncpuIsee3'. The 9th diagram is E3
, Nu shows the Q output of 1225, and Le shows E3' obtained by differentially inverting and amplifying this.

While 1225-Q is high, that is, 1225-Q is low, the output of NAND 1228, which has 1208-Q and 1225-Q as two inputs, is kept high.

The output of 1228 passes through diode 1235 to terminal 123.
As long as diode 1235 is kept high, diode 1235 remains cut off and has no effect on circuit 14.

When 1225-Q is inverted to high by V-Sync of the next first video, 1208-Q is a high line, that is, the period during which the first video signal is supplied to the circuit 14 is NAND 1228
The output of 1228 becomes low, making the diode 1235 conductive and clamping the base of a suitable brightness signal amplification transistor (not shown) included in the circuit 14 to the low level of the output of 1228, turning it 0FF and cutting off the image. .

That is, the image of the part N in FIG. 2 is erased. Also, terminal 12
29 is supplied with the second video V-Sync4 from the circuit 11A.

Originally, E4 should be used separately from the 10 video outputs, but since the delay circuit 9 does not have the ability to correct the difference in the period of the two video signals over one field, the 11
The -Sync separated by A occurs almost simultaneously with the V-Sync included in the 10 video outputs, and is separated by 1 as E4.
There is no practical problem in using the one separated by 1A.

E4 is inverted to positive polarity by inverter 1230;
The signal becomes the signal I4 shown in FIG. NAND 1231 passes through I4, which comes while the Q of JK-FF1 225 is high, and sets RS-FF1 233. Also, Nando 1232 is E4 which arrives during the period when 1225-Q is high.
RS-FF1233 is reset. R.S.
-While FFl233 is being reset, its Q is high, and the Q of RS-FFl2O8 is high, that is, the second image is supplied to the circuits 13 and 14, and is stabilized at a phase 90 degrees behind the interphase, and Eb2 is set to Ebl. If it is assumed that Exl is behind θ, then Exl is (Jin +
? ) It will be delayed (age - ta) for Eb2. For simplicity, let Ex,, Eb, and Eb2 be square waves, 1ex11=1, 1ex21=1, :Ebl:=b
1, 1eb21=B2, bl, b2>1. 11th
Figure A shows Ebl, mouth shows Eb, C shows Exl, and 2 shows Ex2.

Charge amount Q during one cycle of C1 due to Ebl-Exl,
, ρ, as shown in Fig. 11E.

Charge amount Q2 of C2 during one cycle due to Ebl-Ex2
l becomes as shown in FIG.

The result is as shown in Figure 11.

Charge amount Q during one cycle of C1 due to Eb2-Exl,
2 becomes as shown in FIG.

Charge amount Q2 of C2 during one cycle due to Eb2-Ex2
2 becomes next to each other as shown in the 11th diagram.

! Otori b1'b&1V The result is as shown in FIG.

Therefore, the phase discriminator does not output a phase error voltage, proving that the phase of Ex is stable under the above assumption.

FIG. 12 is an example of a filter connected to the output of the phase discriminator shown in FIG. 10.

As can be seen from the constants shown in the figure, the three pole frequencies of this filter are, and between [F2, f3], the output of the phase discriminator is one convex L - one 0.32 times, and for frequencies above 2kHz R
7 kR,°), it decreases with a slope of 20 db/Dec.

R in the diagram. The inductance L connected in series with the inductance L prevents the transmission of the pulse-like phase error voltage generated at the time of mode switching. The filter shown in FIG. 12 has a configuration in which a terminal 121 is connected to the output of a phase discriminator, and a terminal 122 is connected to a phase control terminal of a subcarrier oscillation circuit.

(4) Regarding the mode switch circuit: B voltage of horizontal output circuit E1 Total amplitude of deflection current 11 Deflection coil inductance L1 Deflection period T1 Deflection retrace period Trl High voltage pulse generated during retrace period EHT
There is a relationship between

Since Tr is defined by the free vibration of the deflection coil,
In mode 2, when T is twice the normal value, E is 1/1/2 the normal value.
If you set it to 2, then 1. Both EHTs are in normal condition (mode 1)
) will be kept at the value. If we now add a suffix to the above symbol to correspond to the mode number, when switching from mode 1 to mode 2, E will be 1.
After T becomes T1, T is switched to 2T1, and when switching from mode 2 to mode 1, it is necessary to switch E to E1 after T becomes T1. Otherwise, abnormally high pressure will occur when switching modes, causing sparks, etc. FIG. 13 shows a specific example of a switching circuit that satisfies the above sequence.

The switch 201 in the figure is the same as the mode changeover switch in FIG. 7, and the illustrated state provides mode 2.

The sequence when switching from mode 1 to mode 2 is as follows. First, the switching contact voltage of switch 201 goes high, so transistor 202 goes ON, which energizes relay 203. 203 is excited and 1E1 on E2 is supplied to the horizontal output circuit from the terminal 214.

At the same time, the Zener diode 207 becomes 0FF, and therefore the transistor 208 also becomes 0FF, making its collector potential high. A NAND 20 that receives the switching contact voltage of the switch 201 and the collector voltage of the transistor 208 as input.
Since both inputs of 9 go high, its output goes low, which is inverted by inverter 209A, making transistor 210 ON.

Therefore, the relay 211 connected to the collector also becomes ON, and the time constants of the horizontal oscillation circuit, vertical oscillation circuit, and convergence circuit are switched to the mode 2 state. In this manner, the oscillation cycle is switched to mode 2 on the condition that E2 is supplied to the horizontal output circuit. When mode 2 is set as described above, additional contact 2 of relay 211
13 is open, the transistor 202 and relay 203 are connected to their contacts, resistor 205, and diode 206.
It is self-held by the circuit.

Therefore, when switching from mode 2 to mode 1 next time, even if the switching contact voltage of switch 201 becomes low, transistor 202 and relay 203 are held for a while, supplying E2 to the horizontal output circuit. When the switching contact voltage of the switch 201 becomes low, the output of the NAND 209 changes to high, the transistor 210 becomes 0FF1, and therefore the relay 211 becomes 0FF, and the time constants of the horizontal oscillation, vertical oscillation, and convergence circuits return to the mode 1 state. do. At the same time, the additional contact 213 of the relay 211 is closed and the connection point between the resistor 205 and the diode 206 is grounded, so that the hold of the transistor 202 and the relay 203 is released, and E1 is supplied to the horizontal output circuit. In this manner, E1 is supplied to the horizontal output circuit 1y on the condition that the time constant of the oscillation circuit becomes mode 1.

When mode 1 is established, the Zener diode 207,
Transistor 208 goes ON, its collector voltage goes low, and both inputs of NAND 209 go low. In the above circuit, when the relay 203 is disconnected and E is supplied to the horizontal output circuit while operating in mode 2, the Zener 207 and the transistor 208 immediately become 0N, and their collector voltage becomes low, so the NAND The output of 209 goes high, turns transistor 210 and relay 211 OFF, and has the function of automatically returning to mode 1.

Also, if relay 211 is disconnected while operating in mode 2,
The oscillation cycle is in mode 1, the additional contact 213 of the relay 211 is closed, and the transistor 202 and the relay 203 are closed.
However, these are kept in the ON state by the voltage supplied from the switching contact of the switch 201, and E2 continues to be supplied to the horizontal output circuit.

Therefore, the high pressure will drop and the cathode ray tube will no longer glow. If the switch 201 is switched to the mode 1 side in this state, the transistor 202 and the relay 203 become OFF, E1 is supplied to the horizontal output circuit, and the circuit operates normally in the mode 1 again. That is, even if mode 2 cannot be obtained, mode 1 can be obtained normally, and the receiver does not have to completely lose its functions. Also, when the power is turned on in mode 2, the horizontal oscillation period is T2 after the voltage supplied to the horizontal output circuit reaches E.
= 2T1, and no abnormal high pressure occurs. (5) About the AGC circuit (circuits 6 and 6A) The horizontal synchronization signals of the video signals applied to the circuits 6 and 6A in FIG. 1 are controlled to be substantially in phase.

Therefore, the phase of the horizontal synchronizing signal of the video signal applied to the circuit 6 is controlled so that it is located at the center of the retrace period. The horizontal synchronization signal of the signal becomes located. Therefore, the 6,6A0) AGC circuit operates normally in both mode 1 and mode 2. However, in mode 2, the number of times the AGC circuit discriminates the horizontal synchronizing signal amplitude is half of that in mode 1. As is clear from the above detailed explanation, when the present invention is used, normal image reception is performed for only one channel, and the difference in line period between channels is 1/106 or more of the standard period. Taking advantage of this, it is possible to simultaneously play two channels of video on one CRT screen by switching only when necessary, allowing you to watch the video and audio on one channel and only the video on the other channel. It is possible to change the state to such a state that it is enough to just watch it, and at this time, it is possible to erase unnecessary images using a special circuit so that only the necessary images are played. A convenient television reception system can be obtained.

[Brief explanation of the drawing]

The drawings all relate to the embodiments of the present invention; FIG. 1 is a program diagram of a television receiver, FIG. 2 is a diagram showing the relationship between the reproduced video screens of each channel that appear on the cathode ray tube surface when receiving a two-channel image, Fig. 3 is a circuit diagram of a phase discrimination circuit for horizontal synchronizing signals of two channels, Fig. 4 is a diagram showing voltage waveforms of various parts when the periods of horizontal synchronizing signals of two channels are exactly equal in Fig. 3, and Fig. 4- Figures A and 4-B show each part of the phase discrimination circuit shown in Figure 3 when the periods of the horizontal synchronizing signals of the two channels are slightly different and when one period is slightly longer and shorter than the other, respectively. Figure 5 shows the relationship between the phase difference between the horizontal synchronizing signals and the output voltage when the periods of the two channels are exactly equal in Figure 3. 6 is a circuit diagram of an oscillation circuit for clock pulses inserted into a delay circuit, FIG. 7 is a circuit diagram of an electronic switch, and FIG. 8 is a circuit diagram of an oscillation circuit for clock pulses inserted into a delay circuit. Diagram 9 showing the relationship between the video signal and the hue adjuster.
The figure shows the relationship in which unnecessary images in each channel are erased by the two-channel vertical synchronization signal in Fig. 7, Fig. 10 is a circuit diagram of a phase discrimination circuit for synchronizing the phase of subcarriers, and Fig. 11 The figure shows that the subcarrier is stabilized at a phase 90 degrees behind the intermediate phase of the two burst signals, Figure 12 is a circuit diagram of the filter connected to the output of the phase discrimination circuit in Figure 10, and Figure 13 is A circuit diagram of a switching circuit that satisfies the mode switching sequence is shown. The main symbols used in the drawings indicate the following. 1...Antenna, 2.
...Distributor, 3...Video amplification and detection circuit,
4... Synchronization signal separation circuit, 5... Horizontal synchronization signal separation circuit, 6... AGC circuit, 7...
... Phase discrimination circuit, 8 ... Clock pulse oscillation circuit, 9 ... 1H delay circuit, 10 ...
... Buffer amplifier, 11 ... Vertical synchronization signal separation circuit, 12 ... Electronic switch, 13 ...
... Color difference signal separation and demodulation circuit, 14 ... Luminance signal separation and amplification circuit, 15 ... Adder, 16 ...
...Hue adjuster, 17...Horizontal synchronization signal 1/
2 frequency divider circuit, 18...AFC circuit, 19...
...Horizontal oscillation circuit, 20...Horizontal output circuit,
21...High voltage rectifier circuit, 22...Horizontal convergence circuit, 23...Vertical synchronization signal separation circuit, 24...Vertical oscillation circuit, 25...・
... Vertical output circuit, 26 ... Vertical convergence circuit, 27 ... Audio detection amplification circuit.

Claims (1)

[Claims] 1. First and second video signals are obtained by simultaneously receiving two channels of television broadcasting, and first and second horizontal synchronization signals are extracted from the first and second video signals. A control voltage is obtained by discriminating the phase difference between the first and second video signals, a third video signal is obtained by delaying the first video signal, and a third video signal is extracted from the third video signal by controlling the amount of delay using the control voltage. The horizontal synchronizing signal of No. 3 is made to be approximately in phase with the second horizontal synchronizing signal, and the second and third horizontal synchronizing signals
, the third video signal is switched every horizontal period to obtain a two-channel video signal, and the horizontal and vertical deflection periods of the second and third video signals are set to regular periods in synchronization with the second horizontal synchronization signal. A two-channel simultaneous playback system in a television receiver, characterized in that two-channel video signals are played back at the same time on one cathode ray tube surface by playing back the two-channel video signals at twice the original value. 2. A normal reception state (mode 1) in which the second video signal is reproduced at a normal size on the cathode ray tube surface;
2 in the television receiver according to claim 1, characterized in that the television receiver can be switched by a switch to a two-channel reception state (mode 2) in which channel video signals are simultaneously reproduced on the same cathode ray tube surface. Channel simultaneous playback method. 3. A patent characterized in that the phase of the subcarrier is synchronized with the intermediate phase of the first and third burst signals that are switched for each line of the two-channel video signal, and the hue adjuster is switched for each line. Claim 1
A two-channel simultaneous reproduction method in a television receiver according to item 1 or 2. 4 Among the two sets of reproduced video screens based on the second video signal, the luminance signal component of the video reproduced on the lower half of the cathode ray tube surface and the two sets of reproduced video screens based on the third video signal. Claims 1 or 2, characterized in that the luminance signal component of the video that is reproduced after being divided into upper and lower parts is erased, but the color difference signal component is not erased.
2-channel simultaneous playback method in the television receiver described in 2. 5 When the horizontal deflection period is twice the normal period when reproducing the two-channel video signal on the cathode ray tube surface,
The DC power supply voltage of the horizontal output circuit is approximately 1/1 of the normal periodic deflection.
3. A two-channel simultaneous reproduction system in a television receiver according to claim 1 or 2, characterized in that the television receiver is configured to switch over to two channels. 6 When switching from the normal reception state (mode 1) to the 2-channel reception state (mode 2), the condition is that the DC power supply voltage of the horizontal output circuit is switched to about 1/2 of the normal period deflection. , when switching the horizontal deflection period to twice the normal period, or switching from mode 2 to mode 1, the DC power supply voltage of the horizontal output circuit is changed to the normal period on the condition that the horizontal deflection period is switched to the normal period. A two-channel simultaneous reproduction system in a television receiver according to claim 2, 3, 4, or 5, characterized in that the voltage value is switched to the voltage value at the time of deflection.