JPS59194236A - Information transfer device - Google Patents

Abstract

PURPOSE:To improve transmission efficiency by storing in a memory temporarily a frame which contains data transmitted without any error among transmitted data, between information transmission paths in which a data having error check bits is transfered in frame unit. CONSTITUTION:Addresses are assigned cyclically to the address space of the memory 10 stored temporarily with data in frame unit to be transferred. A write address register 30 and a read address register 60 are used for writing to and reading from the memory 10. An address buffer 40 holds an address indicated by the address register 30 newly when the frame-by-frame writing of the data is completed and no error is detected. A comparator 70 compares the contents of the address register 30 with those of the address register 60 to decide on whether data is readable or not. The data are read out in storage order and the transmission efficiency of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information transfer device that improves the data transfer efficiency of a WK that transfers data having an error check mark.

[Technical background of the invention and its problems]

Digital Data Communication System 2 For example, in a computer system, an input device that takes in data and a CPU that processes the taken data are operated in parallel. This is to improve the efficiency of the system by correcting the decline in processing efficiency caused by the imbalance in operating speed between the input device and the CPU. L required to be installed in the equipment Generally, the data being transferred is subject to a parity check, two cyclic code checks (
Contains error check pits such as CRC). The transmitted data is checked by the error check pit, and the CPU processes only error-free data.

For this reason, when the above data error check is performed on the CPU side for each data frame of serial data, if an error is detected in the data.

Since the data of the frame is discarded, the time spent transferring data from the input device to the CPU is wasted.

Therefore, data error checking is not done on the CP[J side (it is processed by the input device, and only the data for which no errors are detected is sent to the CPU side).
One possible method is to transfer the data to the other side. In this case, one method for transferring the data from the input device to the CPU after checking for errors is to use the interrupt function of the CPU.

DMA requires time to transfer data directly to the CPU's memory, and in the latter DMA method, the CPU
is in the standby HOLD state (such as C
PU can be used efficiently (there are still problems that prevent it from being used).

Therefore, a possible method is to provide an information transfer device between the input device and the CPU 0, which has a first-in-first-out (FIFO) memory in which input data is stored sequentially from the empty area closest to the output side. The method uses FIF to transfer data from the input device to the CPU.
By storing this FI in O memory and setting aside a sufficiently large memory capacity, the CPU can access this FI at any time.
Data can be read from the FO memory in the order in which it was input to the FIFO memory. Now FI
Suppose that frame data 1, 2, etc. in serial format with check pits in F(5 memory) are transferred. P I F when the signal shown in FIG. 1 is transmitted to the input device ' The state of the 0 memory will be shown to the second prisoner and the system using this FIFO memory will be explained.

The signals shown in FIG.
1if @ field in 1 frame, frame check case (FC5).

It has a flag sequence (F), etc. The shaded area in the figure is the flag sequence (F
), and it is assumed that frame E, frame 2, and frame 4 are now being transmitted, and that an error has occurred in frame 3 during transmission. To the above series 1 °・
FIG. 2 shows a state in which frames 1 to 4 are serially and parallel-converted by an input device via two communication lines and stored in a FIFO memory.

At this time, it is unknown whether or not there is an error in frame 3 when the input device sends a signal to the FIFO memory until time t2, so C1) U can read data from the FIFO memory. .

This is until time t1. However, with this FIFO method,
The concept of a frame, which is a unit of data for a group of processes, is ignored, and the data from 9 time t1 is read at time t2 regardless of data inspection.

Next, when the signal is sent until 9 time t4, it is 1 time t3 in 1 prefecture.
Assuming that a data error occurs in frame 3, following this frame 3.

Assume that error-free frame 4 is written into the FIFO memory. Since frame 3 containing the above-mentioned error exists in the FIFO memory, in order for the CPU to read frame 4, it must read out all unnecessary frames 3. Additionally, in this case, determine the erroneous frame.

A device for discarding the data of the frame is required, and the nine circuits inevitably become complicated.

As mentioned above (even in the method using FIFO memory, there is a risk of reading frames for which error checking has not been completed, and there are also problems with data transfer efficiency such as frames with errors being stored in FIFO memory). There were various problems.

[Purpose of the invention]

The present invention improves transmission efficiency by providing a memory between information transmission paths that transfers data having error check bits in units of frames, and which temporarily stores only frames containing data transmitted without errors among the transmitted data. An object of the present invention is to provide an information transfer device that performs improved data transfer.

[Summary of the invention]

This invention provides a memory for temporarily storing frame-by-frame data to be transferred, a write or read address register that determines the address of data to be written to or read from this memory, and a In order to prevent frames containing data from being stored, the last address of the last frame in which no error is detected is held, and this address is used when an error is detected in the frame containing data written immediately after the above-mentioned frame. and an address buffer that stores in the address register.

A means for comparing the contents of the write address register and the read address register to determine whether the data can be read; and a means for comparing the contents of the address buffer and the read address register to determine whether the data can be read. This constitutes an information transfer device that transfers data with improved transmission efficiency.

[Embodiments of the invention]

An embodiment in which the present invention is applied between a human-powered device (not shown) and a CPU (not shown) will be described below with reference to nine drawings. However, the input device.

There is a circuit that detects errors using error check bits included in the transmitted data, and a circuit that converts serial data into parallel data. The address space of the memory 10, which temporarily stores frame-by-frame data to be transferred, is addressed sequentially from the lowest address to the highest address, and the address next to the highest address occupying the last address space is the first address. So that it is the lowest address that occupies the address space.

Addressed cyclically. As means for controlling data written to and read from the memory 10, a tri-state switch 20 for write control and a tri-state switch 50 for readout control are interposed in the data bus 100.

Alternatively, it is used to determine the address of data to be read, and sequentially specifies addresses from the lowest address to the highest address in the memory 10.

The address buffer 40 newly holds the address indicated by the write address register 30 when writing of data in units of one frame is completed and no error is detected, and holds the address indicated by the write address register 30 when an error is detected. The current address is stored in the write address register 30.

Further, the comparator 70 is connected to the write address register 30.
The contents of the read address register 60 are compared with the contents of the read address register 60, and it is determined whether the data can be stored;
0 compares the contents of the address buffer 40 and the read address register 60.

Identify whether data is readable.

The address selection means 90 uses the comparators 70 and 80 to designate the contents of either the write address register 30 or the read address register as the access address of the memory 10 and is connected to the memory 10 via the address bus 110. has been done.

FIG. 4 is a circuit diagram showing details of FIG. 3, and the respective functions will be explained below.

In this embodiment, it is assumed that serial data is converted to 4-bit parallel data by a two-manpower device, so
The memory 10 is mainly composed of a data memory 11 of, for example, 1024 x 4 bits. In other words, it has an address space from address 0 to address 1023. In addition, in order to clearly demarcate each frame of data transmitted in units of frames, a 1024 x 1 bit flag memory 12 is arranged in parallel, which inserts 1'' into the address indicating the end of the frame. A data memory 11 of this memory 10 is connected to a data bus 100.

Further, data is transferred to the flag memory 12 from the input device through the signal line 111, respectively.

The read address register 30, which determines the address of data to be written into the memory 10, is mostly composed of a counter 31. This counter 31 receives the signal ii
,! Addition counting is performed from 0 to 1023 by the fall of the tarlock signal from 130 to terminal CK3. The address of the data to be stored in the memory 10 is determined by this count value.

Further, since the address value next to the highest I address 1023 in the memory 10 is 04F.

When this counter 31 ignores the most significant carry,
A clock signal is input to terminal CK3.
The value input from step 3 becomes the count value of the rice counter 31. This counter 31 always supplies the count value from the terminal 03 to the address line 131.

The address of the data to be written to the memo IJIO is determined.

An address buffer 40 composed of a D5 flip-flop latches a signal to the terminal D4 at the falling edge of the clock signal from the signal line x4o to the terminal CK4.
The counted value of the counter 31 is inputted to the terminal Q4.
This input value is then supplied to the address line 141. This address bar/future 40 is the memo IJI mentioned above.
When no error is detected in the frame written to O, the count value of the counter 31, which is the signal to the terminal D4, that is, the address 11Il of the last data of the written frame, is latched. In other words, this address buffer 4o holds the last address of the last frame in which no error was detected. therefore.

When an error is detected in the frame in which this value is written to the memory 10 at the address line 9 which connects the address line 41 which supplies the value held by the address buffer 40 to the terminal I3 of the counter 31, To.

If the count of the counter 31 is 111'l, the second frame will be written again from the same address as the previous frame, and the frame containing the error will be erased.

On the other hand, when reading data, the read address register 60, which determines the address of data to be read from the memory 10, performs 1. From cool wire 160 to terminal CK
0 to 102 by the fall of the clock signal to 6
3 * for addition counting, f now.

This count 1 designates the address of the data to be read from the memo IJIO. Like the counter 31, this read address register 60 is configured to ignore all carry of the third place, and the count value of σ( of 1023 is O. Therefore, this read address register 60 is configured to count 11 is supplied from the terminal 06 to the address line 161 at '(5'), and the address of the data to be read from the memo IJIO is determined.

Next, when writing data to the memory W.

A comparator 7 that determines whether an address space 18 into which data is written exists in the memory IJIO and whether data can be written.
0 will be explained. Comparator 70 connects address line 131
When ill:j A7' inputted manually from address line 161 to terminal A7 and B7' inputted manually from address line 161 to terminal B7 are A7' + 1 = 87', terminal C7 &
” is output.The value to be input is A7.
' is the last address of the written data at terminal B.
ill L37' input from 7 indicates the last address of the read data, so A7' +1
=B,' means that there is no address space to write the next data. Therefore, signal line 17 from terminal C7
A signal is output that prohibits writing data to 0 in the double layer 4a, thereby preventing erasure of useful data. -Brim A7/ When +1\B7', from terminal C7 °'1
■''' is output to permit writing of data.

Further, the comparator 8°, which determines whether or not there is data to be read out in the address space of the memory 10 when reading data from the memory 10, will be explained. The comparator 80 outputs "" to the terminal C8 when the value A8' inputted from the address line 141 to the terminal A8 and '1illBB' inputted from the address line 161 to the terminal B8 are equal.
Outputs "L".From A8 to A8, A is manually output, / is,
The last address of the last frame in which no error was detected, ie, the last readable address, is sent to terminal B.
Since the F* value B8' input from 8 indicates the last address of the generated data, A8'-B8'
When , it means that there is no address space in the memory 10 from which data should be continued next. Therefore, terminal C
8 to the 1-bar line 180 to prevent reading of data containing errors.

When A8'\B8', H++ is output from terminal C8 to permit continued data output. Furthermore.

The address value of the write address register 50 is used when writing, and the address value of the read address register 60 is used when reading.
The address selection means 90+c for specifying the address 1 of the address 1 as the access address of the main 10 will be explained.

The address selection means 90 is mostly composed of a data selector 91 that outputs either a write address or a read address, and a D register 92 that indicates a sorting or reading operation. Terminal A9 of data selector 91
The address line 131 value A9' is input to the terminal B9, and jM B g' from the address line 161 is input to the terminal B9. When the value S9' input from the signal line 190 to the terminal S9 is "H", the value B9' is output from the terminal Y?
, 11M59' is “L”, the value A is output from terminal Y9.
9' is output and supplied to address bus 110. This data selector 9j selects the write address register 3 or the read address register 6.
0 is supplied to the address bus 110, and the address of the memory 10 is accessed. D
The D register 92-, which is a type flip-flop, is connected to the terminal C.
When 'L' is input to L, 'L' is output from terminal Q9 to indicate - easy access mode +1i1
When the rising edge of the clock signal is input to the 1i child CK9, it outputs "H" from the terminal Q9 to indicate that it is in the read mode. As a result, the D register 92 allows the data selector 91 to select an address for writing or reading.

After determining whether or not there is an error in the frame from the human-powered device, the operation of inputting a frame-by-frame signal and reading the signal to the CPU will be further described with reference to FIG.

FIG. 5 is a time chart showing waveforms at various parts of the circuit diagram shown in FIG. Note that the replacement and read address register before 1 non-operation: total of 30.60 a iil t
Furthermore.

Initialize the value of the address buffer 40 to ``0'' (
. Error detection is performed by the input device as previously described, and the results are provided along with the final data of the frame.

The operation when writing data from the two-man powered device side is shown in section T1 in FIG. 4 and will be explained. This section T1
Now assume that only a write request is occurring. To write data from the input device side, in order to prevent reading from the CPU side at the same time, the signal b (- means L'' level and active) that inhibits reading from the CPU side is set to ``L''. Next, the data signal d is outputted to the data bus 100, and a write signal C is outputted to write data into the data memory 11. At this time,
The count value f of the write address register 30 is "1"
Because it is.

Data D1 is written to address 1 of data memo January 1. Similarly, a series of data during interval T1 is
They are sequentially written to the memo IJIO. Here, the address buffer 40 is given the contents of the write address register 30 when it is determined that there is no error in the data, so simply writing the data from the input device to the data memory 11 will not cause the address buffer 40 The count value i remains at "0" without changing. Therefore, it is still impossible to read out the data on the CPU side.

Then, the operation when the frame ends at time T2 while continuing to send data will be explained. When the input device side determines that the frame has ended, it sends a signal indicating that the frame has ended together with the last data signal d of the frame. Also.

When no errors are detected in the frame, the above
- At the same time, a signal g indicating that there is no error in the frame is also transmitted. This signal g makes it clear that the data D2o is the most recent data of this frame, and that this frame is correct and valid. The above signal g causes the address buffer 40 to write into the write address register.
:30 count value f-"2Q' is latched and count value l-"
io''. With this operation, the comparator J98Q permits reading and outputs a signal J indicating that reading is possible.

At the same time as data D2o is loaded into the data memory 11, a signal g-"l" is inserted into the flag memory 12 to indicate a frame break at the time of reading, and the signal g-"l" is inserted into the flag memory 12 to indicate the frame break at address 20. Show that.

Next, the operation when reading data from the CPU side is shown in section T.
3 will be shown and explained. In this Ward Iij T3,
Not just a write request (a read request has occurred, and an access conflict has occurred.While readable data is stored in the memory 10, the input device does not perform a data write operation. 1 person, that is, signal b =
As long as it is “H”.

Staring 1-iJ function signal j-Since it is “H”, the CPU
It is the IR function that reads the data from the side.

First, the CPU outputs the +iz'9 output signal 2 and supplies data No. 16 t read from the data memory 11 to the data bus 100. At this time, the count value m of the read address register 60 is 1'', so the data D1 at address 1 of the data memory 11 is read out. A series of valid frames of data can be read.

Then, the operation when data continues to be read and data of all valid frames are read out at time 9'r4 will be explained. At time 'r4, the value i of the address buffer 40, which indicates the last address of the valid frame, indicates '20.'

The count value nl of the read address register 60 when reading the last data D2o becomes "20'".

Therefore, by comparing the value of the address buffer 40 and the if1 failure value of the read address register 60, it is found that valid frame data has been read out simultaneously by the rule & register 80. After the 21st date, the result of data error detection is 'f'i'.
is output to notify the CPU that i-scanning is not possible hM.

Next, the operation when an error has occurred in the written data is shown at time T5 and explained. Jj-' do.

When the frame ends on the input device side, a signal indicating that the frame has ended is sent along with the last data No. 16 d of the frame. Shijp L.

Since an error has been detected in the frame, the signal g indicating that there is no error in the frame is not transmitted.
send to As a result, the scheduled address register 30
Based on the value D52 of the data signal d, the gate circuit 93 sets the tri-state switch 2° in a floating state,
Disable data writing. With the above operation,
The frame in which the error occurred appears to have disappeared.

That is, a secondary frame can be written again on top of the frame in which the error occurred. The following interval 'r6
A is written into or read from the memory W at .

Finally, CI) U measurement temporarily stops reading the data,
The operation when the input device cannot read data into the memory 10 will be explained with reference to time T7. Since the address space of the memory 10 in this embodiment is 1024, more data cannot be written. Time T
7, ji of the read address register 60
m indicates "20", indicating that data has been read up to address 20.

Here, the value f of the write at/in register 50 is u,
, ”, the comparator 70 determines that writing is not possible. Therefore, the comparator 70 determines that writing is impossible.

When data D19 is read in from the input device, data cannot be read in after the HaO address. Therefore, the state of the memo 'Jll of the non-implementation bIj configured to stop outputting the penetration tolerance code a will be explained by comparing with the above-mentioned Figures 11 and 2 and Figure 6. do. Figure 1 shows lJ (Z1ro issue).

This signal is based on the assumption that an error occurs during transmission in frame 3 of frames 1 to 4.

At the time when the input device sends the signal to the memory 11 up to time t2, it is unknown whether or not there is an error in frame 3, so that only data up to time L1 can be read from the memory 11 as described above. In other words, the concept of a frame in which processing is done in units of 7 frames is widely accepted.

Next, at the four points where signals were sent up to 2 time t4, frame 4 is written on the memory 11 from tl -t3' directly above frame 3, which was detected to have an error at 9 time t3. I know that there is. That is,
Frames containing errors are erased from memory 10.

As mentioned above, in this embodiment, all data read from the CPU side can be treated as valid.
Unlike the FIFO memory method, there is no need to read frames containing errors.

Furthermore, even when a plurality of frames are stored in the data memory 11, the flag memory 12 makes the division between frames clear, and data other than one information field can be easily distinguished. Therefore, on the input device side,
It is possible to provide an information transfer device that transfers data with improved system transmission efficiency.

In addition, in the above-mentioned embodiment, it is applied between the input device and the CPU, but it may be applied between the input devices or between the CPUs. Further, the format of the transmission signal is not limited to HDLC, and may be a signal format having error check bits such as parity candidate.

〔Effect of the invention〕

As detailed above, according to the present invention, only error-free data is stored on the main IJ, so all read data can be treated as valid. , the data can be read in the order in which it is stored without specifying the memory address.
'It is possible to provide an information ifJ:λL device designed to improve the IJJ rate.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of a transmission signal used in the present invention, Figure 2 is a diagram showing an example of a transmission signal used in the present invention.
3 is a block diagram showing an overview of an embodiment of an information transfer device according to the present invention, and 4 (4 is a circuit diagram showing details of FIG. 3). Figure, 5th
i:, (: is a time chart showing the operation of the embodiment of misfire 1shij, and 61st is 14 showing the state of the memory of this embodiment. 10...... Memory 20.50... Tri-state switch 30.
......Write address register 40
・・・・・・・・・Address buffer 60...
...Read address register 70, 8
0... Comparator 90... Address selection means (73
17) Representative patent attorney Kensuke Chika (and 1 other person) Figure 1 t+ b t:i t4 Figure 2 Figure 6 Figure 3 2-

Claims (1)

[Claims] 1. A memory for temporarily storing frame-by-frame data to be transferred. Means for writing data to be written into the memory into the memory. A write address for determining the address of the data to be written. an address buffer that holds the last address of the last frame in which no error is detected and stores this address in the write address register when an error is detected in a frame containing data written immediately after said frame; Means for reading data to be read from the memory from the memory. A read address register for determining an address of the data to be read. Comparing the contents of the read address register and the write address register to determine whether data can be written. Means for determining. Means for comparing the contents of the address buffer and the read address register to determine whether data can be read. The means for determining readability and the means for determining writability. , the read address register or the write address register. An information transfer device characterized in that the memory stores only error-free data to improve the data transfer efficiency of the data transfer system. 2. Claim 1, wherein the memory has a portion for temporarily storing frame-by-frame data to be transferred and a portion for storing frame delimiters of the frame-by-frame data. Information transfer device as described in section.