JPS59193043A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59193043A
JPS59193043A JP6641283A JP6641283A JPS59193043A JP S59193043 A JPS59193043 A JP S59193043A JP 6641283 A JP6641283 A JP 6641283A JP 6641283 A JP6641283 A JP 6641283A JP S59193043 A JPS59193043 A JP S59193043A
Authority
JP
Japan
Prior art keywords
substrate
film
oxide film
region
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6641283A
Other languages
Japanese (ja)
Inventor
Masanori Yamamoto
山本　正徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6641283A priority Critical patent/JPS59193043A/en
Publication of JPS59193043A publication Critical patent/JPS59193043A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain an FET of a large gate strength by a method wherein heat treatment is performed after implanting O2 ions to the surface of the semiconductor substrate, thus forming a semiconductor region surrounded by SiO2 in the substrate, where a protection element such as a Zener diode is then provided, when a vertical type MOS-FET is manufactured. CONSTITUTION:An SiO2 film 2 is adhered on the N type Si substrate 1 and covered with a resist film 11 having a required window, and the O2 ions 12 are implanted with said film as a mask. Thereafter, an SiO2 film 13 surrounding the semiconductor layer 14 composed of the substrate 1 is generated in the surface layer part of the substrate 1. Next, an oxide film 15 is provided at the center of the surface of this layer 14, and regions 16 are formed by diffusing a P type impurity in the layer 14 on both sides of said film with the film as a mask, one of which regions is used as the source region and the other as the gate region. Thus, the regions 16 are isolated from the substrate 1 by the oxide film 13, obtaining the Zener diode without the generation of parasitic capacitance between the substrate 1, resulting in the increase of the gate strength of the FET.

Description

【発明の詳細な説明】 本発明はソース電極およびゲート電極を上面に、ドレイ
ン電極を裏面に持つ縦型ＭＯ８−ＦＥＴの構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a vertical MO8-FET having a source electrode and a gate electrode on the top surface and a drain electrode on the bottom surface.

従来、縦型ＭＯ８−ＦＥＴを形成する場合、ゲート酸化
膜保診の為、第１図に示すように保睦ダイオードとして
のツェナーダイオード（Ａ部）を入れることが望ましい
。すなわち、−導電、型の半導体基板１の裏面にはドレ
イン電極１０が形成されており、表面には反対導電型の
第１の不純物領域４が複数個設けられている。この第１
の不純物領域４中にソース領域となる一導電型の第２の
不純物領域５とが設けられ、第１の不純物領域４間の基
板１の表面には、内部にゲート電極となるポリシリコン
層３を有する酸化膜２が形成されている。Conventionally, when forming a vertical MO8-FET, it is desirable to insert a Zener diode (section A) as a protection diode as shown in FIG. 1 to check the gate oxide film. That is, a drain electrode 10 is formed on the back surface of the - conductivity type semiconductor substrate 1, and a plurality of first impurity regions 4 of the opposite conductivity type are provided on the front surface. This first
A second impurity region 5 of one conductivity type, which becomes a source region, is provided in the impurity region 4, and a polysilicon layer 3, which becomes a gate electrode, is formed on the surface of the substrate 1 between the first impurity regions 4. An oxide film 2 is formed.

第１および第２の不純物領域４，５の露出部はソース電
極８と接触している。Exposed portions of the first and second impurity regions 4 and 5 are in contact with the source electrode 8.

ツェナーダイオードは第１の不純物領域４の１つに形成
されており、この不純物領域４中には一導電型の第３の
不純物領域６とこれと接している反対導電型の第４の不
純物領域７がダイオード接合を形成するように形成され
ている。表面の酸化膜２中にはやはりポリシリコン層３
を鳴し、ゲート電極９は真中に位置する第４の不純物領
域７に接触している。The Zener diode is formed in one of the first impurity regions 4, which includes a third impurity region 6 of one conductivity type and a fourth impurity region of the opposite conductivity type that is in contact with the third impurity region 6. 7 is formed to form a diode junction. There is also a polysilicon layer 3 in the oxide film 2 on the surface.
The gate electrode 9 is in contact with the fourth impurity region 7 located in the middle.

このように保護ダイオード（Ａ部）を入れると、ＰＮＰ
Ｎのサイリスクが、ゲート電極９と、ドレイン電極１０
間でできてしまう（以後、サイリスタ・アクションと鉢
ぶ）。このため、保護ダイオードを縦型ＭＯ８−ＦＥＴ
に入れることができず、ゲ−ト耐量の小さい、縦型ＭＯ
８−ＦＥＴしか製作することができなかった。When a protection diode (A part) is inserted like this, PNP
The N silica is connected to the gate electrode 9 and the drain electrode 10.
(hereinafter referred to as thyristor action). For this reason, the protection diode is replaced with a vertical MO8-FET.
Vertical MO with low gate resistance and cannot be inserted into
Only 8-FETs could be manufactured.

本発明の目的は、サイリスタ・アクションしない保護ダ
イオードを持つ即ち、ゲート耐量の大きい縦型ＭＯ８−
ＦＥＴを提供することである。It is an object of the present invention to provide a vertical MO8-type MO8-1 having a protection diode without thyristor action, that is, having a large gate withstand capability.
The purpose of this invention is to provide an FET.

本発明の特徴は、縦型ＭＯ８，ＦＥＴにおいで、表面に
酸素のイオン注入（例えは、１００ｋｅＶ〜２００ｋｅ
Ｖ１１ＸＩＯ”−１−１０”ｄのｉ件）ヲ行ｆｘイ、そ
の後熱処理して、半導体基板中にｓｉｏ、で囲まれた半
導体領域を形成し、この５ｉｎ２によシ囲まれた半導体
領域に、ツェナー・ダイオード等の保護素子を拡散もし
くは、イオン注入にて形成することにある。The feature of the present invention is that oxygen ion implantation (for example, 100keV to 200keV
V11 The purpose is to form protective elements such as Zener diodes by diffusion or ion implantation.

本発明によれは、サイリスタ・アクシロンしない保護ダ
イオード（ツェナー・ダイオード）を持つ縦型ＭＯ８−
ＦＨＴを作ることができ、ゲート酸化膜の保護に役立て
ることができる。According to the invention, a vertical MO8-
FHT can be created and can be used to protect the gate oxide film.

本発明を図面を用いてよシ眸細に説明する。The present invention will be explained in detail using the drawings.

第２図（ａ）〜（ｄ）に保論ダイオード部の形成方法を
示す。まず、第２図（ａ）に示すように、−導電型（例
えばＮ型）半導体基板１に酸化膜２ｆｃ成長させ、さら
に、７オトリングラフイ技術により窓あけを行ない、フ
ォトリングラフィのレジストｋｍりだまま、酸素のイオ
ン注入を、例えは１００ｋｅ’Ｖ〜２００ｋｅ■、注入
搦ＩＸＩ　Ｏ”−ＩＸＩ　Ｏ”ｃｒｄで注入する。レジ
ストを除去し、これを熱処理し、例えば、１０００’０
．　Ｎ２．１０分して、酸化膜１３を半導体基板１中に
形成する（（ｂ）図）。この酸化膜１３により、囲まれ
た半導体基板ｌの部分１４中に酸化膜を形成し、それを
フォト・リンクラフィ技術により、窓ありを行なってマ
スクとしての酸化膜１５を形成する（（Ｃ）図）。その
後、拡散もしくは、イオン注入に：す、反対４電型の鴇
域１６を部分的に形成する（（ｄ）図）。FIGS. 2(a) to 2(d) show a method of forming the logic diode section. First, as shown in FIG. 2(a), an oxide film of 2 fc is grown on a -conductivity type (for example, N type) semiconductor substrate 1, and then a window is opened using the 7-otrinography technique to form a photolithography resist with a length of km. Then, oxygen ions are implanted, for example, at a voltage of 100 ke'V to 200 ke and an implantation rate of IXI O"-IXI O" crd. Remove the resist and heat treat it, for example, 1000'0
．． After N2.10 minutes, an oxide film 13 is formed in the semiconductor substrate 1 (Figure (b)). An oxide film is formed in the surrounded portion 14 of the semiconductor substrate l by this oxide film 13, and a window is formed on it by photo-linkage technology to form an oxide film 15 as a mask ((C) figure). Thereafter, by diffusion or ion implantation, a region 16 of the opposite 4-electrode type is partially formed (Figure (d)).

マスクとしての酸化膜１５を除去したものが第３図であ
る。ンースを極は領域１８に、ゲート電極は領域１７に
形成してツェナー・ダイオードを形成する。従って、酸
化膜１３により半導体基板１から分離されている為、半
導体基板１との間に寄生素子を生じないツェナー・タイ
オードができあがる。もちろんＰＮＰ、ＮＰＮどちらの
ツェナー・ダイオードを形成してもよい。FIG. 3 shows the structure with the oxide film 15 as a mask removed. A gate electrode is formed in region 18 and a gate electrode in region 17 to form a Zener diode. Therefore, since it is separated from the semiconductor substrate 1 by the oxide film 13, a Zener diode that does not generate parasitic elements between it and the semiconductor substrate 1 is completed. Of course, either a PNP or NPN Zener diode may be formed.

本発明を用いた縦型ＭＯ８−ＦＥＴ４第４図に示す。A vertical MO8-FET 4 according to the present invention is shown in FIG.

第１図のものと同じものには同じ参照番号を付しである
。相違は保設素子としてのツェナー・ダイオード部にあ
ｐ１第１の不純物領域４甲に酸化膜１３で分離された領
域１４．１６を有している。Components that are the same as those in FIG. 1 are given the same reference numerals. The difference is that the Zener diode portion as a storage element has regions 14 and 16 separated by an oxide film 13 in the first impurity region 4A.

領域１４は第１の不純物領域４と同じ導電型であυ、領
域１６は反対導電型で、これらでツェナー・ダイオード
を構成している。ゲート電極９は領域１６に形成されて
いる。The region 14 is of the same conductivity type as the first impurity region 4, and the region 16 is of the opposite conductivity type, forming a Zener diode. Gate electrode 9 is formed in region 16 .

このように、本発明によれば、酸素のイオン注入により
、酸化膜１３をシリコン中に形成し、その酸化膜１３に
より囲まれた領域にツェナー・ダイオードを形成するこ
とにより、サイリスク・アクシ１ンの及ない。縦型ＭＯ
８−ＦＥＴを製作することができる。また、酸化膜１３
によって他の部分から絶縁分離した領域中に電子的素子
が他の部分との寄生効果を生じる仁となく形成できるの
で、ツェナー・ダイオードに限らず、一般の半導体素子
中に他の素子を作る時きわめて有効である。As described above, according to the present invention, the oxide film 13 is formed in silicon by oxygen ion implantation, and the zener diode is formed in the region surrounded by the oxide film 13. Out of reach. Vertical MO
8-FET can be fabricated. In addition, the oxide film 13
This makes it possible to form electronic devices in a region that is insulated from other parts without causing parasitic effects with other parts. Extremely effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の構造を示す断面図でおる。 第２図（ａ）〜（ｄ）は本発明の数を作る製造工程を示
しだ断面図である。 第３図は本発明の一実施例によるツェナー・ダイオード
の断面図でるる。 第４図は本発明を用いた、縦型ＭＯ８・ｌ”　Ｅ　Ｔの
構造の一例を示す断面図である。 ｌ・・・・・・−導電型半導体基板、２・・・・・・酸
化膜、３・・・・・・ポリ・シリコン（ゲート’＝＆）
、４・・・・・・反対導電型の第１の不純物領域、５・
・・・・・−漕、電型の第２の不純物領域（ソース領域
）、６・・・・・・−２４電型の第３の不純物領域、７
・・・・・・反対導電鮭の第４の不純物領域、８・・・
・・・ソース電極、９・・・・・・ゲートπＩ：極、ｌ
Ｏ・・・・・・ドレイン電４Ｌ　　１ｘ・・・・・・レ
ジスト、１２・・・・・・酸素イオン注入、１３・・・
・・・酸化膜、１４・・・・・・半導体基板の一部、１
５・・・・・・酸化膜、１６・・・・・反対導電型の領
域、１７・・・・・・ゲート領域（ツェナー・ダイオー
ドにおりる）、１８・・・・・・ソース領域（ツェナー
・ダイオードにおける）。 箔３閉FIG. 1 is a sectional view showing a conventional structure. FIGS. 2(a) to 2(d) are sectional views showing the manufacturing process for manufacturing the number of the present invention. FIG. 3 is a cross-sectional view of a Zener diode according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing an example of the structure of a vertical MO8・l"ET using the present invention. l...--conductive semiconductor substrate, 2...-oxidation Film, 3...Polysilicon (gate'=&)
, 4...first impurity region of opposite conductivity type, 5.
. . . - row, second impurity region (source region) of electric type, 6 .....-24 third impurity region of electric type, 7
・・・・・・Fourth impurity region of opposite conductivity salmon, 8...
...Source electrode, 9...Gate πI: pole, l
O...Drain voltage 4L 1x...Resist, 12...Oxygen ion implantation, 13...
... Oxide film, 14 ... Part of semiconductor substrate, 1
5...Oxide film, 16...Region of opposite conductivity type, 17...Gate region (falls into Zener diode), 18...Source region ( (in Zener diodes). Foil 3 close

Claims (1)

【特許請求の範囲】[Claims] 半導体基板中に絶縁Ｍを形成してその一部を他から分離
し、この絶縁膜に囲まれた領域中に半導体素子を形成し
たことを特徴とする半導体装置。1. A semiconductor device characterized in that an insulating film M is formed in a semiconductor substrate to separate a part of the insulating film from the rest, and a semiconductor element is formed in a region surrounded by this insulating film.
JP6641283A 1983-04-15 1983-04-15 Semiconductor device Pending JPS59193043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6641283A JPS59193043A (en) 1983-04-15 1983-04-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6641283A JPS59193043A (en) 1983-04-15 1983-04-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59193043A true JPS59193043A (en) 1984-11-01

Family

ID=13315053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6641283A Pending JPS59193043A (en) 1983-04-15 1983-04-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59193043A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863878A (en) * 1987-04-06 1989-09-05 Texas Instruments Incorporated Method of making silicon on insalator material using oxygen implantation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935029A (en) * 1972-08-03 1974-04-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935029A (en) * 1972-08-03 1974-04-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863878A (en) * 1987-04-06 1989-09-05 Texas Instruments Incorporated Method of making silicon on insalator material using oxygen implantation

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