JPS59191367A - Structure of multilayer interconnection - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device, into which inductance is incorporated, by alternately connecting conductors for wirings for an upper layer and conductors for wirings for a lower layer and forming inductance. CONSTITUTION:The end B1 of a wiring 3 as a lower layer on an insulator 2 for the main surface of a semiconductor substrate 1 is connected to the end C1 of a wiring 4 as an upper layer through a through-hole. The end D1 of the upper- layer wiring 4 is connected similarly to the end A2 of a wiring 3 as a lower layer. The end B2 of a wiring 3 as a lower layer is connected similarly to the C2 of a wiring 4 as an upper layer. Accordingly, the ends AxBx of wirings 3 as lower layers and the ends CxDx of wirings 4 as upper layers are connected alternately. A coil wound (n) times is formed by repeating said process (n) times.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multilayer wiring structures, and more particularly to inductance structures in integrated circuits.

Conventionally, it has been very difficult to incorporate inductance into semiconductor devices, and inductance has rarely been used in monolithic integrated circuits. For this reason, circuits using inductance use a coil as a separate component in addition to the integrated circuit, resulting in a reduction in integration density.

In addition, there was little freedom in circuit design to avoid changing the inductance as much as possible.

The present invention solves the above-mentioned drawbacks by forming a -C inductance using multilayer wiring conductors, and provides a semiconductor device incorporating an inductance.

In this invention, a multilayer wiring structure includes multilayer wiring conductors on or within a substrate, and the upper layer wiring conductors and the lower layer wiring conductors are alternately connected to increase inductance. This is a multilayer wiring structure characterized by forming.

FIG. 1 is a diagram showing a portion in which an inductance is incorporated into an integrated circuit in which two-layer wiring is formed using metal such as aluminum on a semiconductor substrate in one embodiment of the present invention. An end B of the lower layer wiring 3 on the insulator 2 on the main surface of the semiconductor substrate 1 is connected to an end C1 of the upper layer wiring 4 via a through hole. Upper layer wiring 4
Similarly, the end DI is connected to the end AJ of the lower layer wiring 3. End a of the lower layer wiring 3 is similarly connected to C7 of the upper layer wiring 4. In this way, the end AXBx of the lower layer wiring 3 and the end axDx of the upper layer wiring 4 are alternately connected. By repeating the edges n times, a coil with n turns is formed.

According to the present invention, when the width of the wiring conductor is 12 μm, the interval is 4 μm, and the interlayer insulating film thickness is 1 μm, and a 25-turn coil is formed, the self-inductance of the coil is:
Approximately 2.4 x 10-1 according to the calculation formula for a rectangular cylindrical coil
'(H) is calculated.

When a coil with the same area as this is formed on an insulator 2 on the main surface of a semiconductor substrate as shown in FIG. The self-inductance is approximately 0.7X10' according to the calculation formula for a rectangular spiral-wound coil.

[H] is calculated.

From this, according to the trap of the present invention, it is possible to obtain a coil having a self-inductance more than three times larger than that of the conventional method shown in FIG. 2 with the same area.

Further, the coil formed according to the present invention includes: 1. Since the electrode terminals have recesses at both ends and the shape and length and width can be designed relatively freely, the layout within the integrated circuit becomes easy. As described above, according to the present invention, an inductance can be incorporated inside a semiconductor device. Therefore, even in a circuit using inductance, there is no need to use a coil as a separate component in addition to the integrated circuit, and there is no reduction in integration density. Furthermore, since inductance can be used in circuit design of integrated circuits, the degree of freedom in design increases.

Note that the present invention is applicable not only to semiconductor substrates but also to structures on or within dielectric substrates such as S7I.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and is a diagram showing an inductance formed on a semiconductor substrate. FIG. 2 is a diagram showing one method of configuring a conventional inductance. In the figure, 1...semiconductor substrate, 2...insulator, 3
... Single-layer metal wiring, 4, Double-layer metal wiring, 5...
...Metal wiring. 1st muscle 2 times

Claims (1)

[Claims] In a thorn layer wiring structure including multilayer wiring conductors configured on or within a substrate, the upper layer wiring conductor and the lower layer wiring 4 conductors are alternately connected to form an inductance. multilayer wiring structure.