JPS59190722A - Josephson logical gate - Google Patents

Josephson logical gate

Info

Publication number
JPS59190722A
JPS59190722A JP6364883A JP6364883A JPS59190722A JP S59190722 A JPS59190722 A JP S59190722A JP 6364883 A JP6364883 A JP 6364883A JP 6364883 A JP6364883 A JP 6364883A JP S59190722 A JPS59190722 A JP S59190722A
Authority
JP
Japan
Prior art keywords
junction
gate
magnetic field
inductance
quantum interferometer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6364883A
Other languages
Japanese (ja)
Other versions
JPH0155782B2 (en
Inventor
Norio Fujimaki
藤巻 則夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP6364883A priority Critical patent/JPS59190722A/en
Publication of JPS59190722A publication Critical patent/JPS59190722A/en
Publication of JPH0155782B2 publication Critical patent/JPH0155782B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • H03K19/1952Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with electro-magnetic coupling of the control current

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a Josephson logical gate which has a large operation margin and small occupation area by applying an input signal current to a dual-junction superconductive quantum interferometer through a magnetic field coupled control line. CONSTITUTION:Inductance L3 and L4 of the magnetic field coupled control line LC and bias current lines Lb1 and Lb2 couple with inductance L1 and L2 of 3:1 through a magnetic field. Then, the input signal current is passed through the magnetic field coupled control line LC and then applied to the dual-junction superconductive quantum interferometer having the superconductive inductances L1 and L2. A figure shows threshold value characteristics when the L.I product of this gate is phi0. Thus, the intersections B and B' of the threshold value characteristic curve and a segment 0A are decrease and the margin becomes about + or -17% wider.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は、1対のジョセフソン接合と超伝導インダクタ
ンスを有する2接合超伝導量子干渉計を用いたジョセフ
ノン論理ゲートに関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a Josephson logic gate using a two-junction superconducting quantum interferometer having a pair of Josephson junctions and a superconducting inductance.

(b)  従来技術と問題点 従来、動作マージンの大きなジ萱セ7ン/論理ゲートと
しては、T 、R,GheewalaがI BM、’J
、 Re s 。
(b) Prior art and problems Conventionally, as a logic gate with a large operating margin, T, R, Gheewala, IBM, 'J
, Res.

Develop、Vol、24.No、2(1980)
pp、130−142に述べているCIL (Curr
ent Injection Logic)7テミリー
が知られている。ジョセフソン接合の臨界電流値の設定
値に対する製造工程におけるズレの許容範囲を±20優
とする場合に、CILファミリーの中の3接合超伝導量
子干渉計を用いたORゲートの動作マージンは±26%
であシ、CID(Current Injection
Device)と呼ばれる2接合超伝導量子干渉計を用
いたANDゲートは±17チである。他のゲートファミ
リーの動作マージンはこれよシ小さいO H−Beha et alが、IEEE、 Mag−1
7,No、6(1981)pp3423−3425に述
べているHTCID(High Torelance 
Current Injection Device 
)は±33%の動作マージンを有するが、ANDゲート
であ、90Rゲートではない。ところでCILファミリ
ーのORゲートである3接合超伝導量子干渉計は占有面
積が大きく、25μmルールにおいて、50ItmX1
00μm程度で6D、CIDの約5倍の面積となシ、高
集積化に制限を与えていた。従って集積度をさらに上げ
ようとする場合、動作マージンが大きく、占有面積の小
さIORゲートが必要とされる。また、S1M、Far
isカICCC(19,80)の論文集pp、 119
6−1201に述べたゲートは、前述のCIDを注入型
のORゲートとして用いるものであシ、面積は小さいが
ORとしての動作マージンが小さい。これを電流増幅回
路によりて改善しようとすると、その結果占有面積を大
きくシ、消費電力の増大と動作マージンの低下を招く。
Develop, Vol. 24. No. 2 (1980)
CIL (Curr
ent Injection Logic) 7 Temily is known. If the allowable range of deviation in the manufacturing process from the set value of the critical current value of the Josephson junction is ±20, the operating margin of an OR gate using a three-junction superconducting quantum interferometer in the CIL family is ±26. %
Adashi, CID (Current Injection)
The AND gate using a two-junction superconducting quantum interferometer called ``Device'' has ±17 chi. Other gate families have smaller operating margins. O H-Beha et al.
7, No. 6 (1981) pp. 3423-3425.
Current Injection Device
) has an operating margin of ±33%, but it is an AND gate and not a 90R gate. By the way, the three-junction superconducting quantum interferometer, which is the OR gate of the CIL family, occupies a large area, and in the 25 μm rule, it is 50 Itm
At about 0.00 μm, the area is about five times that of 6D and CID, which limits high integration. Therefore, if the degree of integration is to be further increased, an IOR gate with a large operating margin and a small occupied area is required. Also, S1M, Far
iska ICCC (19, 80) collection of papers pp, 119
The gate described in No. 6-1201 uses the above-mentioned CID as an injection type OR gate, and although the area is small, the operating margin as an OR is small. If an attempt is made to improve this by using a current amplification circuit, the occupied area will increase, leading to an increase in power consumption and a decrease in operating margin.

以下、従来のジョセフソン論理ゲートについて具体的に
見る。
Below, we will look specifically at conventional Josephson logic gates.

2接合超伝導量子干渉計の1つであるCIDの等価回路
を第1図(a)に、またL・工状が1.74Φ0の場合
におけるその閾値特性を第1図(b)に示す。
FIG. 1(a) shows an equivalent circuit of a CID, which is one of the two-junction superconducting quantum interferometers, and FIG. 1(b) shows its threshold characteristics when the L/shape is 1.74Φ0.

第1図(a)においてJl、  J2は臨界電流比が1
:3であるジョセフソン接合、L++  LtH3: 
1ノインダクタンス、Lbはバイアス電流線である。
In Figure 1(a), Jl and J2 have critical current ratios of 1.
:3 Josephson junction, L++ LtH3:
1 noise inductance, and Lb is a bias current line.

また第1図(b)において、横軸Iaは入力信号電流の
和であり、縦軸Ibはバイアス電流線Lbを通じて供給
されるバイアス電流である。
In FIG. 1(b), the horizontal axis Ia is the sum of input signal currents, and the vertical axis Ib is the bias current supplied through the bias current line Lb.

入力信号電流を注入するので、ファンアウトは並列とな
るが、ファンアウト数を2とする場合に、第1図(bl
の線分OAとしきい値特性との交点Bと、無人力信号状
態でのしきい値C点との間がバイアスのマージンである
。実際には臨界電流値の製造工程上のズレを±20%許
容しなければならず、バイアスの範囲はB′とC′の間
となるため、動作マージンは、±10チしかない。
Since the input signal current is injected, the fan-outs are parallel, but when the number of fan-outs is 2, as shown in Figure 1 (bl
The bias margin is between the intersection point B of the line segment OA and the threshold characteristic and the threshold point C in the unmanned signal state. In reality, it is necessary to allow a deviation of ±20% in the critical current value due to the manufacturing process, and the bias range is between B' and C', so the operating margin is only ±10 inches.

(C)発明の目的 本発明の目的は、動作マージンが大きく、占有面積の小
さなジョセフソン論理ゲートを提供することにある。
(C) Object of the Invention An object of the present invention is to provide a Josephson logic gate with a large operating margin and a small occupied area.

(d)  発明の構成 上記目的を実現するための本発明は、臨界電流比がl:
3である1対のジョセフソン接合および超伝導インダク
タンスを有する2接合超伝導量子干渉計と、該2接合超
伝導量子干渉針の該伝導インダクタンスを3:1に分割
する点にバイアス電流を供給する手段と、該超伝導イン
ダクタンスに磁界結合するコントロール線を有し、入力
信号電流は該コントロール線を通った後に該2接合超伝
導量子干渉計に注入されるようにしたことを特徴とする
(d) Structure of the invention In order to achieve the above object, the present invention has a critical current ratio of l:
A bias current is supplied to a two-junction superconducting quantum interferometer having a pair of Josephson junctions and a superconducting inductance of 3, and a point dividing the conducting inductance of the two-junction superconducting quantum interference needle at a ratio of 3:1. and a control line magnetically coupled to the superconducting inductance, and the input signal current is injected into the two-junction superconducting quantum interferometer after passing through the control line.

(e>  発明の実施例 以下、本発明の実施例を図面を用いて説明する。(e> Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

第2図(a)は、本発明の一実施例を示す図である。FIG. 2(a) is a diagram showing an embodiment of the present invention.

図において、L8+  L4は磁界結合コントロール線
Lcのインダクタンスを、Lb++ Lbz ハバイア
ス電流線を示し、これらは3:1のインダクタンスLe
t  Ltと磁界結合している。尚、他の第1図と同じ
符号は同じものを示す。
In the figure, L8+L4 indicates the inductance of the magnetic field coupling control line Lc, Lb++Lbz indicates the bias current line, and these have an inductance Le of 3:1.
t Magnetically coupled with Lt. Note that the same reference numerals as in other FIG. 1 indicate the same things.

図に明らかなように、入力信号電流IBは磁界結合コン
トロール線Lcを通った後臨界電流比が1=3のジョセ
フソン接合JI、Jtと超伝導インダクタンスLl、L
、を有する2接合超伝導量子干渉計に注入される。
As is clear from the figure, after the input signal current IB passes through the magnetic field coupling control line Lc, it is connected to the Josephson junction JI, Jt with a critical current ratio of 1=3 and the superconducting inductance Ll, L.
, into a two-junction superconducting quantum interferometer.

このようなゲートのL・工状がΦ。の場合の閾値特性は
第2図(b)に示される。これに明らかなように閾値特
性曲線と線分OAとの交点BおよびB′は低下し、マー
ジンは±17%に広がった。尚、第2図(a)において
バイアス電流はバイアス電流線Lb+またはLbtから
与えられる。
The L shape of such a gate is Φ. The threshold value characteristic in the case of is shown in FIG. 2(b). As is clear from this, the intersections B and B' between the threshold characteristic curve and the line segment OA decreased, and the margin widened to ±17%. In FIG. 2(a), the bias current is applied from the bias current line Lb+ or Lbt.

第3図は本発明の第2の実施例を示す図で、インダクタ
ンスL、、L6を有する磁界結合コントロール線をさら
に設け、入力信号電流を2本のコントロール線を通した
後超伝導量子干渉計に注入する構成である。
FIG. 3 is a diagram showing a second embodiment of the present invention, in which magnetic field coupling control lines having inductances L, L6 are further provided, and the input signal current is passed through the two control lines, and then the superconducting quantum interferometer is connected to the superconducting quantum interferometer. It is configured to be injected into

この場合占有面積は増大するが、動作マージンは第1の
実施例よりも大きくなる。
In this case, the occupied area increases, but the operating margin becomes larger than in the first embodiment.

第4図は、本発明の第3の実施例を示す図である。本実
施例は抵抗rl、  rlを設け、注入電流が入力信号
電流の□倍となシ、抵抗rl+ r3のrl+r2 値をかえて注入電流のレベルが調整可能としたものであ
る。
FIG. 4 is a diagram showing a third embodiment of the present invention. In this embodiment, resistors rl and rl are provided so that the injection current is □ times the input signal current, and the level of the injection current can be adjusted by changing the rl+r2 value of the resistor rl+r3.

第5図は、本発明の第4の実施例を示す図である。本実
施例は入・出力の分離を図るものであ広分離用ジョセフ
ソン接合はJs、J41 Js−Jaのいずれかの位置
に接続され、分離用抵抗はrl、r21rsのいずれか
の位置に接続される。
FIG. 5 is a diagram showing a fourth embodiment of the present invention. This embodiment aims to separate input and output, and the Josephson junction for wide isolation is connected to either position Js or J41 Js-Ja, and the isolation resistor is connected to either position rl or r21rs. be done.

第6図は、本発明の第5の実施例は入力数を4にして4
人力OR動作を行うものである0次に、これら本発明に
よるジョセフソン論理ゲートの適用例を以下に示す。
FIG. 6 shows that in the fifth embodiment of the present invention, the number of inputs is 4.
Application examples of these Josephson logic gates according to the present invention will be shown below in order to perform a manual OR operation.

第2図体)に示したゲートを簡単に第7図に表わす記号
で示す。
The gate shown in Figure 2) is simply indicated by the symbol shown in Figure 7.

第8図は、抵抗RT、 RstXジ田セフソン接合J。Figure 8 shows resistance RT, RstX Jita Sefson junction J.

を有する電流増幅回路CAを接続した例を示す。An example is shown in which a current amplification circuit CA having the following is connected.

出力を並列に2つ取出す場合、閾値特性上の動作線は第
2図(b)の線分OA’となシ、大きな信号電流で次段
が駆動できる。
When two outputs are taken out in parallel, the operating line on the threshold characteristic is line segment OA' in FIG. 2(b), and the next stage can be driven with a large signal current.

尚、出力数を3にすると、動作線は第2図(b)の線分
OA”となシ、電流増幅回路を接続しない出力数2と同
じマージンが得られる0 第9図は、2つのORゲートに抵抗RT+ 、RTtを
介してジョセ7ンン接合JIGを接続してAND動作を
行わせる構成を示す。
Note that if the number of outputs is 3, the operating line will be the line segment OA'' in Figure 2(b), and the same margin as the number of outputs of 2 without connecting the current amplifier circuit will be obtained. A configuration is shown in which a Joseon junction JIG is connected to an OR gate via resistors RT+ and RTt to perform an AND operation.

第10図は、第9図の構成と同様にAND動作を行わせ
る構成で、破線で囲む電流注入型ゲートによシ2つのO
Rゲートを接続したものである0(f)発明の詳細 な説明したように、本発明によれば占有面積カ小すく、
動作マージンの大きいジョセフソン論理ゲートが提供さ
れる。
FIG. 10 shows a configuration that performs an AND operation similar to the configuration shown in FIG. 9, in which two O
As described in detail of the 0(f) invention in which R gates are connected, according to the present invention, the occupied area is small;
A Josephson logic gate with large operating margin is provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は、従来のジョセフソン論理ゲートを示す
図、第1図(b)は、その閾値特性を示す図、第2図(
a)は、本発明の第1実施例を示す図、第2図(blは
、その閾値特性を示す図、第3図は本発明の第2の実施
例を示す図、第4図は、本発明の第3の実施例を示す図
、第5図は、本発明の第4の実施例を示す図、第6図は
、本発明の第5の実施例を示す図、第7図は、本発明の
ゲートを表示する記号を示す図、第8図乃至第10図は
それぞれ本発明のゲートの適用例を示す図である。 図においてJ+、Jxはジョセ7ノン接合、Ll。 L2は超伝導インダクタンス、Lbはバイアス電流線、
Lcは磁界結合コントロール綜を示す。 出願人   工業技碕院長 1・1田倦峙答 (図 (a)1 鯵 zI2] ((2)
FIG. 1(a) shows a conventional Josephson logic gate, FIG. 1(b) shows its threshold characteristics, and FIG.
a) is a diagram showing the first embodiment of the present invention, FIG. 2 (bl is a diagram showing its threshold characteristic, FIG. 3 is a diagram showing the second embodiment of the present invention, and FIG. 4 is a diagram showing the second embodiment of the present invention. FIG. 5 is a diagram showing a fourth embodiment of the invention, FIG. 6 is a diagram showing a fifth embodiment of the invention, and FIG. 7 is a diagram showing a fifth embodiment of the invention. , a diagram showing symbols indicating the gate of the present invention, and FIGS. 8 to 10 are diagrams each showing an application example of the gate of the present invention. In the figures, J+ and Jx are Jose7 non-junctions, Ll. L2 is superconducting inductance, Lb is bias current line,
Lc indicates a magnetic field coupling control head. Applicant: Director of the Institute of Industrial Science and Technology

Claims (1)

【特許請求の範囲】[Claims] 臨界電流比が1:3である1対のジョセフソ/接合およ
び超伝導インダクタンスを有する2接合超伝導量子干渉
計と、該2接合超伝導量子干渉計の超伝導インダクタン
ス金3:1に分割する点にバイアス電流を供給する手段
と、該超伝導インダクタンスに磁界結合するコントロー
ルAn有し、入力信号電流は該コントロール線七通った
後に該2接合超伝導量子干渉計に注入されるようにした
ことを特徴とするジョセ7ン/論理ゲート。
A two-junction superconducting quantum interferometer having a pair of Joseph So/junction and superconducting inductance with a critical current ratio of 1:3, and a point where the superconducting inductance of the two-junction superconducting quantum interferometer is divided into 3:1. and a control An for magnetically coupling the superconducting inductance, and the input signal current is injected into the two-junction superconducting quantum interferometer after passing through the seven control lines. Characteristic Jose7/logic gate.
JP6364883A 1983-04-13 1983-04-13 Josephson logical gate Granted JPS59190722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6364883A JPS59190722A (en) 1983-04-13 1983-04-13 Josephson logical gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6364883A JPS59190722A (en) 1983-04-13 1983-04-13 Josephson logical gate

Publications (2)

Publication Number Publication Date
JPS59190722A true JPS59190722A (en) 1984-10-29
JPH0155782B2 JPH0155782B2 (en) 1989-11-27

Family

ID=13235375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6364883A Granted JPS59190722A (en) 1983-04-13 1983-04-13 Josephson logical gate

Country Status (1)

Country Link
JP (1) JPS59190722A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315180A (en) * 1992-02-13 1994-05-24 Fujitsu Limited Synchronizing interface circuit between semiconductor element circuit and a Josephson junction element circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315180A (en) * 1992-02-13 1994-05-24 Fujitsu Limited Synchronizing interface circuit between semiconductor element circuit and a Josephson junction element circuit

Also Published As

Publication number Publication date
JPH0155782B2 (en) 1989-11-27

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